200913264 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種積體微電子元件的製造方法’特別 是關於一種平面環繞閘極場效電晶體的製造方法。 【先前技術】 隨著金屬氧化物半導體場效電晶體（metal oxide semiconductor filed effect transistor ; MOSFET)的製造技術 曰新月異，MOSFET的閘極厚度與閘極長度不斷地縮減至 幾十個奈米（nm)，環繞閘極（surrounding gate)元件結構成 為未來元件開發的指標已是眾所周知，而矽奈米線的製作 為閘極環繞元件製程的關鍵。如美國專利公告號第 6,583,014號及美國專利公開號第2004051150號所揭示， 圖1至圖5係習知平面環繞閘極MOSFET的製造方法。參 照圖1，在一基板1〇〇上形成一絕緣層1〇2及一單晶矽層 1〇4 以構成一絕緣碎（silicon_on-insulator; SOI)基板。參照 圖2 ’圖案化單晶矽層104形成源極區域ι〇6、汲極區域 110以及一通道區域108連接源極區域106與汲極區域 110。參照圖3 ’利用濕式化學等向性蝕刻將通道區域ι〇8 下方的絕緣層102移除，使通道區域1〇8藉由源極區域1〇6 與沒極區域（未示於圖中）的支撐而懸掛在源極區域1〇6與 200913264 汲極區域（未示於圖中）之間。參照圖4，利用再氧化法在 通道區域108上形成一犧牲層112。參照圖5，利用部分 蝕刻移除法形成一圓柱型奈米線114懸掛於源極區域106 與汲極區域110之間，作為一電子傳輸通道，之後在圓柱 型奈米線114上成長閘極氧化層及複晶矽，並圖案化該閘 極氧化層及複晶矽以定義出閘極。習知平面環繞閘極 MOSFET的製程經由濕式化學等向性独刻、再氧化法及部 分蝕刻移除法形成圓柱型奈米線，導致奈米線的表面因蝕 刻而產缺陷或變得粗糙，造成元件效能的劣化，例如漏電 流增加或在光波導或微鏡上造成散射損耗，尤其當元件的 尺寸為奈米等級時情況更為嚴重。此外，經由一次氧化及 二次蝕刻形成圓柱型奈米線的步驟，亦使得製程變得複雜 而導致製造成本增加。 因此，一種具有高效能且製程複雜度低的平面環繞閘 極場效電晶體及其製造方法，乃為所冀。 【發明内容】 本發明的目的，在於提出一種具有高效能且製程複雜 度低的平面環繞閘極場效電晶體及其製造方法。 根據本發明，一種平面環繞閘極場效電晶體包括一基 板，一絕緣層位於該基板上，一源極區域及一没極區域位 200913264 於該絕緣層的上方’-圓柱型奈米線懸掛於該源極區域與 汲極區域之間，以及一閘極環繞該圓柱型奈米線，該閘極 包括一磊晶層位於該圓柱型奈米線上，一導電層位於該磊 晶層上，以及一介電層介於該磊晶層與該導電層之間。 根據本發明，一種平面環繞閘極場效電晶體的製造方 法包括提供一基板，該基板包括一絕緣層位於該基板上， 以及一單晶矽層位於該絕緣層上，圖案化該單晶矽層以形 成源極區域、汲極區域與通道區域，該源極區域與汲極區 域位於該通道區域的兩端，進行一锻燒(annealing)製程， 使該通道區域形成一圓柱型奈米線懸掛於該源極區域與 ;及極區域之間，以及形成一閘極，該閘極環繞該圓柱型奈 米線。 本發明利用與積體電路製程相容的煅燒製程，形成懸 掛於源極和汲極之間的圓柱型奈米線，作為平面環繞閘極 場效電晶體的電子傳輸通道，該電子傳輸通道具有平滑的 表面’且元件的閘極包圍該電子傳輸通導，達到體積反轉 (volume-inversion)的效果，大幅增加元件的單位電流進而 谷許較大的驅動電流，同時控制短通道效應（short channel effect)的發生，減少次臨限漏電（sub_threshold leakage)的現 象’達到提升元件效能及降低製程複雜度的目的。 200913264 【實施方式】 如圖1所示，在基板100上形成絕緣層102及單晶矽 層104構成SOI基板’基板1〇〇包括單晶石夕基板，絕緣層 102包括二氧化矽，單晶矽層104的厚度約為2〇nm至 60nm。參照圖6 ’圖案化單晶矽層1〇4形成源極區域222、 '/及極區域224以及一通道區域216連接源極區域222與汲 極區域224。參照圖7及圖8，進行一锻燒製程，包括氫 煅燒、咼真空烺燒或在惰性氣體（例如氬氣）下的高溫緞 燒，通道區域216的表面原子由凸出處往凹陷處擴散，使 得通道區域216的四個角呈圓弧狀，同時侵蝕位於通道區 域216下方的絕緣層102，通道區域216的表面原子經擴 散後，由於表面張力的因素，微小物體傾向維持最小的表 面積，使得通道區域216由位於絕緣層1〇2上的長方體細 長條結構成為懸掛在源極區域222與汲極區域224之間的 圓柱型奈米線236，作為一電子傳輸通道。參照圖9，在 圓柱型奈米線236上成長一介電層218及一導電層22〇, 介電層218包括氧化物，導電層22〇包括複晶石夕，圖案化 介電層218及導電層22〇以形成環繞圓柱型奈米線236的 閘極226。參照圖1〇，進行沉積保護層、形成接觸窗、沉 積金屬層以狀義酬料後段金屬連線製程，形成具有 源極接觸區232、沒極接觸區234及閘極接觸區230的平 200913264 面環繞閘極場效電晶體。 參照圖U，在不同的實施例中，在形成圓柱型奈米線 236後，以圓柱型奈米線236中的石夕為晶種，利用有機金 屬化學氣相沉積法(MOCVD)在圓柱型奈米線2妬上成長 -遙晶層228 ’蠢晶層228包括石夕鍺蟲晶層，接著在蟲晶 層228上成長一介電層218及一導電層22〇，介電層218 包括氧化物，導電層220包括複晶矽，圖案化磊晶層228、 "電層218及導電層220以形成環繞圓柱型奈米線236的 閘極226 ’隨後進行後段金屬連線製程，形成電子遷移能 力較大的矽鍺奈米線平面環繞閘極場效電晶體。 圖12及圖13係本發明形成奈米線的示意圖。參照圖 ^ ’在一 SOI基板上形成源極區域222、汲極區域224以 及一通道區域216 ’通道區域216為一位於源極區域222 與沒極區域224之間的細長條結構，其截面為扁平狀，例 如一100nmx20nm的矩形。參照圖13，進行一煅燒製程， 通道區域的表面原子經擴散形成一圓柱型奈米線236懸掛 於源極區域222與汲極區域224之間，其截面為圓形，例 如一直徑為50nm的圓形，由於表面原子擴散不會損耗或 増加整體的體積，因此在煅燒製程之前通道區域216的截 面積等於煅燒製程之後奈米圓柱236的截面積，藉由此特 性’可設計在形變後元件的大小。此外，此種表面原子擴 200913264 散的機制不僅改善表面粗糙度，同時元件中幾何結構也產 生三維形變，使幾何結構中尖角的部分變得圓滑，此現象 類似玻璃或有機材質的熱迴焊(refl〇w)，但不同的是此擴散 機制僅發生於表面，其内部仍維持單晶矽結構，因此形成 在其他製程難以達到的球形立體結構，例如圖14所示的 微圓柱體結構及圖15所示的微圓球體結構。再者，藉由 二維形變的現象，進一步縮小元件的尺寸，以便製作不同 的奈米元件。 本發明以煅燒製程形成的奈米線，除了簡化製程步驟 外，更可利用步進曝光機形成次微米的線條寬度再形成奈 米線，而不需使用到電子束直寫系統來形成奈米線，有效 降低設備的成本，其次，奈米線表面平滑無蝕刻製程造成 的缺陷’且其截面為圓形可避免角落效應（c〇rner effect)。 【圖式簡單說明】 圖1係習知形成絕緣矽基板後的示意圖； 圖2係習知形成源極、汲極及通道區域後的示意圖； 圖3係習知形成通道懸掛在源極區域與汲極區域之間 後的示意圖； 圖4係習知在通道上形成犧牲層後的示意圖； 圖5係習知形成奈米線後的示意圖； 200913264 圖6係本發明形成源極、汲極及通道區域後的示意圖； 圖7係本發明進行煅燒製程的示意圖； 圖8係本發明形成奈米線後的示意圖； 圖9係本發明形成環繞閘極後的示意圖； 圖10係本發明形成源極、汲極及閘極接觸點後的示 意圖； 圖11係本發明形成環繞閘極後的示意圖； 圖12係本發明形成源極、汲極及通道區域後的示意 圖， 圖13係本發明形成奈米線後的示意圖； 圖14係本發明形成微圓柱體結構的示意圖；以及 圖15係本發明形成微圓球體結構的示意圖。 【主要元件符號說明】 100 基板 102 絕緣層 104 單晶矽層 106 源極區域 108 通道區域 110 汲極區域 112 犧牲層 200913264 114 216 218 220 222 224 226 228 230 232 234 236 奈米線 通道區域 介電層 導電層 源極區域 〉及極區域 閘極 蠢晶層 閘極接觸區 源極接觸區 汲極接觸區 奈米線 12BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating an integrated microelectronic device, and more particularly to a method of fabricating a planar surrounding gate field effect transistor. [Prior Art] With the rapid development of metal oxide semiconductor filed effect transistor (MOSFET) technology, the gate thickness and gate length of MOSFETs are continuously reduced to several tens of nanometers. (nm), the surrounding gate structure has become an indicator of future component development, and the fabrication of the nanowire is the key to the gate-surrounding process. Figures 1 through 5 illustrate a method of fabricating a planar planar gate MOSFET as disclosed in U.S. Patent No. 6,583,014 and U.S. Patent Publication No. 2004051150. Referring to Fig. 1, an insulating layer 1〇2 and a single crystal germanium layer 1〇4 are formed on a substrate 1 to form a silicon-on-insulator (SOI) substrate. Referring to Fig. 2', the patterned single crystal germanium layer 104 forms a source region ι6, a drain region 110, and a channel region 108 connecting the source region 106 and the drain region 110. Referring to FIG. 3', the insulating layer 102 under the channel region ι8 is removed by wet chemical isotropic etching so that the channel region 1〇8 is separated from the source region by the source region 1〇6 and the gate region (not shown in the figure). The support is suspended between the source region 1〇6 and the 200913264 drain region (not shown). Referring to Figure 4, a sacrificial layer 112 is formed over the channel region 108 by a reoxidation process. Referring to FIG. 5, a cylindrical nanowire 114 is formed by partial etching removal between the source region 106 and the drain region 110 as an electron transport channel, and then the gate is grown on the cylindrical nanowire 114. An oxide layer and a germanium layer are patterned, and the gate oxide layer and the germanium layer are patterned to define a gate. Conventional planar surround gate MOSFET processes are formed by wet chemical isotropic, reoxidation, and partial etch removal to form cylindrical nanowires, resulting in defects or roughening of the surface of the nanowire due to etching. Deterioration of component performance, such as increased leakage current or scattering loss on an optical waveguide or micromirror, especially when the size of the component is nanometer. Further, the step of forming the cylindrical nanowire through the primary oxidation and the secondary etching also complicates the process and causes an increase in manufacturing cost. Therefore, a planar surrounding gate field effect transistor having high performance and low process complexity is a method for manufacturing the same. SUMMARY OF THE INVENTION An object of the present invention is to provide a planar surrounding gate field effect transistor having high performance and low process complexity and a method of fabricating the same. According to the present invention, a planar surround gate field effect transistor includes a substrate, an insulating layer is disposed on the substrate, a source region and a immersed region 200913264 above the insulating layer '-cylindrical nanowire suspension Between the source region and the drain region, and a gate surrounding the cylindrical nanowire, the gate includes an epitaxial layer on the cylindrical nanowire, and a conductive layer is on the epitaxial layer. And a dielectric layer is interposed between the epitaxial layer and the conductive layer. According to the present invention, a method of fabricating a planar surround gate field effect transistor includes providing a substrate including an insulating layer on the substrate, and a single crystal germanium layer on the insulating layer to pattern the single crystal germanium The layer is formed to form a source region, a drain region and a channel region. The source region and the drain region are located at both ends of the channel region, and an annealing process is performed to form a cylindrical nanowire. Suspended between the source region and the pole region, and forming a gate that surrounds the cylindrical nanowire. The invention utilizes a calcination process compatible with the integrated circuit process to form a cylindrical nanowire suspended between the source and the drain, as an electron transport channel of the planar surround gate field effect transistor, the electron transport channel has A smooth surface' and the gate of the component surrounds the electron transport conduction to achieve a volume-inversion effect, which greatly increases the unit current of the component and thereby drives a large drive current while controlling the short channel effect (short The occurrence of channel effect) reduces the phenomenon of sub_threshold leakage' to achieve the purpose of improving component performance and reducing process complexity. [Invention] As shown in FIG. 1, an insulating layer 102 and a single crystal germanium layer 104 are formed on a substrate 100 to constitute an SOI substrate. The substrate 1 includes a single crystal substrate, and the insulating layer 102 includes germanium dioxide, single crystal. The thickness of the germanium layer 104 is approximately 2 nm to 60 nm. The source region 222, the '/ and the pole region 224, and the one channel region 216 are connected to the source region 222 and the drain region 224 with reference to Fig. 6' patterned single crystal germanium layer 1〇4. Referring to FIGS. 7 and 8, a calcination process is carried out, including hydrogen calcination, vacuum calcination or high temperature satin burning under an inert gas such as argon, and surface atoms of the channel region 216 are diffused from the convex portion to the depression. The four corners of the channel region 216 are arcuate, while etching the insulating layer 102 under the channel region 216. After the surface atoms of the channel region 216 are diffused, the microscopic object tends to maintain a minimum surface area due to surface tension. The channel region 216 is formed by a rectangular parallelepiped strip structure on the insulating layer 1〇2 as a cylindrical nanowire 236 suspended between the source region 222 and the drain region 224 as an electron transport channel. Referring to FIG. 9, a dielectric layer 218 and a conductive layer 22 are grown on the cylindrical nanowire 236. The dielectric layer 218 includes an oxide, and the conductive layer 22 includes a polycrystalline stone, a patterned dielectric layer 218, and The conductive layer 22 is formed to form a gate 226 surrounding the cylindrical nanowire 236. Referring to FIG. 1A, a deposition protection layer is formed, a contact window is formed, and a metal layer is deposited to form a metal wiring process for forming a source contact region 232, a gate contact region 234, and a gate contact region 230. The surface surrounds the gate field effect transistor. Referring to Figure U, in a different embodiment, after forming the cylindrical nanowire 236, the seed crystal of the cylindrical nanowire 236 is seeded by organometallic chemical vapor deposition (MOCVD) in a cylindrical shape. The nanowire 2 grows up - the telecrystalline layer 228 'the stray layer 228 comprises a layer of stone worms, and then a dielectric layer 218 and a conductive layer 22 成长 are grown on the layer 228, the dielectric layer 218 comprising The oxide, conductive layer 220 includes a polysilicon layer, a patterned epitaxial layer 228, an electrical layer 218, and a conductive layer 220 to form a gate 226' surrounding the cylindrical nanowire 236, followed by a post-metal wiring process to form The nanowire line with large electron mobility is surrounded by a gate field effect transistor. 12 and 13 are schematic views showing the formation of a nanowire of the present invention. Referring to the drawings, 'the source region 222, the drain region 224, and the channel region 216' are formed on an SOI substrate. The channel region 216 is an elongated strip structure between the source region 222 and the gate region 224. It is flat, for example, a rectangle of 100 nm x 20 nm. Referring to FIG. 13, a calcination process is performed in which a surface atom of the channel region is diffused to form a cylindrical nanowire 236 suspended between the source region 222 and the drain region 224, and has a circular cross section, for example, a diameter of 50 nm. Circular, since the surface atom diffusion does not deplete or add to the overall volume, the cross-sectional area of the channel region 216 before the calcination process is equal to the cross-sectional area of the nano-cylinder 236 after the calcination process, by which the characteristic can be designed after the deformation component the size of. In addition, the surface atom diffusion mechanism of 200913264 not only improves the surface roughness, but also the three-dimensional deformation of the geometric structure in the component, which makes the sharp corners of the geometric structure become smooth, which is similar to the thermal reflow of glass or organic materials. (refl〇w), but the difference is that the diffusion mechanism only occurs on the surface, and the single crystal structure remains in the interior, thus forming a spherical solid structure that is difficult to achieve in other processes, such as the microcylinder structure shown in FIG. The microsphere structure shown in Fig. 15. Furthermore, by the phenomenon of two-dimensional deformation, the size of the components is further reduced to make different nano components. In the nanowire formed by the calcination process, in addition to simplifying the process steps, a stepper can be used to form a submicron line width to form a nanowire, without using an electron beam direct writing system to form a nanometer. The wire effectively reduces the cost of the device. Secondly, the surface of the nanowire is smooth and has no defects caused by the etching process, and its cross section is circular to avoid the c〇rner effect. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a state in which an insulating germanium substrate is formed; FIG. 2 is a schematic view showing a source, a drain, and a channel region; FIG. 3 is a conventionally formed channel suspended in a source region and FIG. 4 is a schematic view showing a formation of a sacrificial layer on a channel; FIG. 5 is a schematic view showing a conventional formation of a nanowire; 200913264 FIG. 6 is a source, a bungee and a cathode of the present invention. Figure 7 is a schematic view of the calcination process of the present invention; Figure 8 is a schematic view of the present invention after forming a nanowire; Figure 9 is a schematic view of the present invention after forming a surrounding gate; Figure 10 is a source of formation of the present invention BRIEF DESCRIPTION OF THE DRAWINGS FIG. 11 is a schematic view of the present invention after forming a surrounding gate; FIG. 12 is a schematic view of the present invention after forming a source, a drain and a channel region, and FIG. 13 is a schematic diagram of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Figure 14 is a schematic view showing the formation of a microcylinder structure of the present invention; and Figure 15 is a schematic view showing the structure of the microsphere formed by the present invention. [Main component symbol description] 100 substrate 102 insulating layer 104 single crystal germanium layer 106 source region 108 channel region 110 drain region 112 sacrificial layer 200913264 114 216 218 220 222 224 226 228 230 232 234 236 nanowire channel region dielectric Layer Conductive Layer Source Region> and Polar Region Gate Stupid Layer Gate Contact Region Source Contact Region Bungee Contact Region Nanowire 12