WO2020151477A1

WO2020151477A1 - Method for manufacturing gate-all-around nanowire device

Info

Publication number: WO2020151477A1
Application number: PCT/CN2020/070214
Authority: WO
Inventors: 刘金彪; 王桂磊; 杨涛; 王垚; 李俊峰
Original assignee: 中国科学院微电子研究所
Priority date: 2019-01-21
Filing date: 2020-01-03
Publication date: 2020-07-30
Also published as: CN109742025A

Abstract

Provided is a method for manufacturing a gate-all-around nanowire device, the method comprising: first forming a fin (102) on a substrate, the fin (102) being a trench for forming a nanowire; then forming, on either side of the fin (102), a layer stack in which an oxygen-containing thermal reaction layer (1202) and an oxygen-free isolation layer (1201) are alternately arranged; performing a thermal annealing process, wherein at this time, the fin (102) is made to react with the oxygen in the thermal reaction layers (1202) on two sides thereof to form a fin oxide layer (103), so the fin (102) is partitioned off by the fin oxide layers (103) in a direction perpendicular to the substrate, and the remaining fin (102) is a nanowire; and then releasing the nanowire and forming a gate electrode, thereby forming a gate-all-around nanowire device. In this method, the fin (102) is partitioned off to form a nanowire by means of forming a layer stack in which an oxygen-containing thermal reaction layer (1202) and an oxygen-free isolation layer (1201) are alternately arranged, and by means of a thermal annealing process, and this does not require the development of a new process or the introduction of new equipment, the manufacturing difficulty thereof is low, and same is compatible with existing processes, and is conducive to the mass production of gate-all-around nanowire devices.

Description

Method for manufacturing ring gate nanowire device

This application claims the priority of a Chinese patent application filed with the Chinese Patent Office on January 21, 2019, the application number is 201910054471.3, and the invention title is "a method for manufacturing a ring-gate nanowire device", the entire content of which is incorporated by reference In this application.

Technical field

The invention relates to the field of semiconductor devices and their manufacturing, in particular to a method for manufacturing a ring-grid nanowire device.

Background technique

With the continuous development of integrated circuit manufacturing technology, the critical size of semiconductor devices, especially field-effect transistors (MOSFETs), has been continuously reduced, and has even been reduced to 10nm and below nodes. The short channel effect of devices has become more and more significant. The device has been unable to meet the performance and integration requirements of the device.

At present, a three-dimensional device structure is proposed, which increases the gate control ability by increasing the number of gates, so that the device has a stronger driving current, which can effectively suppress the short channel effect. The gated ring nanowire device is a multi-gate device whose gate completely surrounds the channel region of the nanowire, which has better gate control capability and lower energy consumption. It is the most suitable for silicon-based devices at 10nm and below. Potential solutions. However, the nanowire structure, especially the stacked nanowire structure, is more complicated in process realization, reduces the manufacturing difficulty, and has good compatibility with the existing process, which is a key issue for realizing mass production of gate-around nanowire devices.

Summary of the invention

In view of this, the purpose of the present invention is to provide a method for manufacturing a gate-around nanowire device with low manufacturing difficulty and good compatibility with existing processes.

In order to achieve the above objectives, the present invention has the following technical solutions:

A manufacturing method of a gate-around nanowire device includes:

Providing a substrate on which a fin and a supporting structure at both ends of the fin are formed, and the fin is a semiconductor channel material;

On both sides of the fins, an oxygen-free isolation layer and an oxygen-containing thermal reaction layer are alternately laminated layers;

Perform a thermal annealing process to make the fin react with the oxygen in the thermally reactive layer on both sides to form a fin oxide layer. In the direction perpendicular to the substrate, the fin oxide layer clamps off the fin, and the remaining fin Form nanowires;

Removing the laminated layer and the fin oxide layer to release the nanowires;

A gate surrounding the nanowire is formed.

Optionally, the substrate is a semiconductor substrate, and the fin and the supporting structure are formed by etching the semiconductor substrate.

Optionally, the support structure is used to form source and drain regions.

Optionally, before forming the laminated layer, the method further includes: forming source and drain regions in the support structure.

Optionally, before forming the laminated layer, the method further includes:

A thermal oxidation process is performed to oxidize the surface of the fin and remove the surface of the oxidized fin.

Optionally, the thermally reactive layer is silicon oxide, and the isolation layer is silicon nitride.

Optionally, the thermal annealing process is performed in an oxygen atmosphere.

Optionally, after releasing the nanowire, before forming the gate surrounding the nanowire, the method further includes:

The modification process of the nanowire is performed.

Optionally, forming a gate surrounding the nanowire includes:

Covering the nanowires to form a dielectric layer;

Patterning the dielectric layer to expose a part of the length of the nanowire;

A gate is formed surrounding the exposed nanowires.

Optionally, the gate includes a metal gate.

In the method for manufacturing a gate-around nanowire device provided by an embodiment of the present invention, a fin is now formed on the substrate, and the fin is a channel for forming the nanowire. Then, an oxygen-containing thermal reaction layer and a non-conductive layer are formed on both sides of the fin. The oxygen isolation layer is alternately stacked, and a thermal annealing process is performed. At this time, the fin and the oxygen in the thermally reactive layer on both sides of the fin react to form a fin oxide layer. In this way, the fin oxide layer is perpendicular to the substrate. The layer clamps off the fins, and the remaining fins are nanowires, which in turn release the nanowires and form a gate, thereby forming a gate-around nanowire device. In this method, by forming an oxygen-containing thermal reaction layer and an oxygen-free isolation layer alternately stacked layers, and then through a thermal annealing process, the fin is pinched off to form nanowires, without the need for new process development and the introduction of new equipment, and its manufacturing is difficult It is low and has good compatibility with the existing technology, which is beneficial to realize the mass production of the ring-gate nanowire device.

Description of the drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are For some of the embodiments of the present invention, for those of ordinary skill in the art, other drawings may be obtained based on these drawings without creative work.

Fig. 1 shows a schematic flow chart of a method for manufacturing a gate-around nanowire device according to an embodiment of the present invention;

2-8 show three-dimensional schematic diagrams of the device structure in the process of forming a grid-around nanowire device according to the manufacturing method of an embodiment of the present invention, wherein FIGS. 2A-7A are schematic cross-sectional three-dimensional structures of FIGS. 2-7 respectively.

detailed description

In order to make the above-mentioned objects, features and advantages of the present invention more obvious and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

In the following description, many specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways different from those described here, and those skilled in the art can do so without departing from the connotation of the present invention. Similar to the promotion, the present invention is not limited by the specific embodiments disclosed below.

Secondly, the present invention will be described in detail in conjunction with schematic diagrams. When describing the embodiments of the present invention in detail, for ease of description, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic diagram is only an example, which should not be limited here. The scope of protection of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual production.

As described in the background art, the gate-around nanowire device is a multi-gate device whose gate completely surrounds the channel region of the nanowire, and has better gate control capabilities and lower energy consumption. It is oriented towards 10nm and The most potential solutions for silicon-based devices at the following nodes. However, the nanowire structure, especially the stacked nanowire structure, is more complicated in process realization, reduces the manufacturing difficulty, and has good compatibility with the existing process, which is a key issue for realizing mass production of gate-around nanowire devices.

To this end, the present application proposes a method for manufacturing a gate-around nanowire device. Now a fin is formed on the substrate, and the fin is a channel for forming the nanowire, and then an oxygen-containing thermal reaction is formed on both sides of the fin. Layers and oxygen-free isolation layers are alternately stacked, and a thermal annealing process is performed. At this time, the fin and the oxygen in the thermally reactive layer on both sides of the fin react to form a fin oxide layer, so that in the direction perpendicular to the substrate The fin oxide layer clamps off the fins, and the remaining fins are nanowires, which then release the nanowires and form a gate, thereby forming a gate-around nanowire device. The method does not require the development of new processes and the introduction of new equipment, has low manufacturing difficulty, has good compatibility with existing processes, and is conducive to mass production of ring-gate nanowire devices.

In order to better understand the technical solutions and technical effects of the present application, specific embodiments will be described in detail below in conjunction with the flowcharts in Figure 1 and Figures 2-7A.

1, in step S01, a substrate 100 is provided. The substrate 100 is formed with a fin 102 and a supporting structure 104 at both ends of the fin 102. The fin 102 is a semiconductor channel material. Refer to FIGS. 2 and 2A (FIG. 2) is shown in the cross-sectional perspective view.

The substrate 100 is a supporting substrate, and the substrate 100 can be used to form the fin 102 and/or the supporting structure 104 at the same time. In the embodiment of the present invention, the substrate 100 can be a semiconductor substrate, for example, Si Substrate, Ge substrate, SiGe substrate, SOI (Silicon On Insulator) or GOI (Germanium On Insulator, Germanium On Insulator), Group III and Group five compounds, Group II and Group IV compound semiconductors, etc. In other embodiments, the substrate may also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, etc., may also be a stacked structure, such as Si/SiGe, etc., or other epitaxial structures. , Such as SGOI (Silicon Germanium on Insulator) and so on.

The fin 102 is a semiconductor material that can be used as a channel of a device, for example, it can be a semiconductor material in the aforementioned substrate, such as Si, Ge, SiGe, and so on. The supporting structure 104 is formed at both ends of the fin 102, and is used to support the nanowire after the nanowire is formed by the fin. At the same time, the supporting structure can be formed by using a semiconductor material to further form the source of the nanowire device. Drain area.

The source and drain regions can be formed after the support structure is formed. Specifically, the mask layer can be covered on the area outside the support structure 104, and then, according to the type of device to be formed, ion implantation is performed to perform N in the support structure. Type or P-type doping, and activate the doping by annealing to form source and drain regions. The N-type doped dopant ions can be, for example, N, P, As, S, etc., and the P-type doped doped particles For example, it can be B, Al, Ga or In.

In this embodiment, the substrate 10 may be a semiconductor substrate, such as a silicon substrate, as shown in FIG. 2 and FIG. 2A, which may be formed by etching the substrate 10. Specifically, the substrate 10 A mask layer is formed on the upper layer, and the pattern is transferred to the mask layer by photolithography. After that, under the mask of the mask layer, the substrate 10 is etched to form the fin 102 and the supporting structure 104 at both ends of the fin 102. The fin 102 The number can be multiple, after which the mask layer is removed.

The fin 102 is used to form nanowires, and the size of the fin is related to the final nanowire device. With the continuous improvement of integration, it is hoped to form nanowires of smaller size. Further, after the fins are formed, a thermal oxidation process can be performed. In the thermal oxidation process, referring to FIGS. 3 and 3A (a cross-sectional perspective view of FIG. 3), the surface of the fin is oxidized, and then the oxidized The surface of the fin is removed. In this way, on the one hand, the surface damage of the fin and the supporting structure during the etching process can be repaired, and on the other hand, by controlling the oxidation process, the size of the fin can be made to reach the required target width, which is close to the channel width of the nanowire. In the specific oxidation process, a low-temperature thermal oxidation process can be used, and the temperature range of the low-temperature thermal oxidation can be 750-850°C, and typically, the temperature can be about 800°C.

It is understandable that in the thermal oxidation process, as shown in FIGS. 3 and 3A, the surface of all exposed semiconductor materials will be oxidized. In this embodiment, the substrate 100 is a semiconductor substrate, and the fin 102 and the supporting structure 104 pass The substrate is formed by etching. In this way, during the thermal oxidation process, the exposed surfaces of the substrate 100, the fin 102, and the support structure 104 will all form a thermal oxide layer 110. The thermal oxidation process will repair these surfaces. At the same time, Make the size of the fin reach the required target width.

In step S02, stacked layers 120 with alternate oxygen-free isolation layers 1201 and oxygen-containing thermal reaction layers 1202 are sequentially formed on both sides of the fin 102, as shown in FIG. 4 and FIG. 4A (the cross-sectional perspective view of FIG. 4).

Wherein, the oxygen-containing thermally reactive layer 1202 means that the material of the film layer contains oxygen atoms, and the material will thermally react with the fins in the subsequent thermal annealing process, and the oxygen-free isolation layer 1201 means that the material of the film layer does not Without oxygen, the isolation layer 1201 functions to isolate the fin into several parts along the direction perpendicular to the substrate 100, and the isolation layer 1021 does not thermally react with the fin during the subsequent thermal annealing process. In specific applications, suitable materials can be selected to form the isolation layer 1021 and the thermally reactive layer 1202 according to needs. Typically, the oxygen-containing thermally reactive layer 1202 can be silicon oxide (SiO ₂ ) or an oxygen-free isolation layer 1201 It may be silicon nitride (Si ₃ N ₄ ). For ease of description, the direction along the vertical substrate 100 will be referred to as the vertical direction in the following.

In addition, according to specific needs, the number and thickness of the isolation layer 1021 and the thermally reactive layer 1202 in the laminated layer 120 are related to the number of nanowires in the vertical direction. The more the number of stacked layers, the more The more layers of the nanowire array formed in the vertical direction, their thickness is related to the thickness of the nanowire in the vertical direction.

In this embodiment, a low pressure chemical deposition (LPCVD) method can be used to alternately deposit silicon nitride and silicon oxide layers, and the thickness of the silicon oxide layer can be 5-30 nm, thereby forming an isolation layer 1021 composed of silicon nitride and silicon oxide. As shown in FIG. 4 and FIG. 4A, the fin 102 is covered by the stacked layer 120 alternately.

In step S03, a thermal annealing process is performed to cause the fin 102 to react with the oxygen in the thermally reactive layer 1202 on both sides to form a fin oxide layer 103. In the direction perpendicular to the substrate 100, the fin oxide layer 103 The fin 102 is clamped off, and the remaining fin 102 forms a nanowire, as shown in FIG. 5 and FIG. 5A (the cross-sectional perspective view of FIG. 5).

In the thermal annealing process, the oxygen in the thermally reactive layer 1202 undergoes a thermal oxidation reaction with the fins on the side. By controlling the process conditions, such as process temperature, process atmosphere, and flow rate, the fins between the thermally reactive layers 1202 can be in the lateral direction. The upper surface is completely oxidized, and the formed fin oxide layer 103 clamps the fin 102 in the vertical direction. The clamped fin 102 is the remaining unreacted fin, which is divided into several parts in the vertical direction. Nanowires are formed. By controlling the number of layers of thermally reactive layers and isolation layers, nanowire arrays with different numbers of layers can be formed. In one application, as shown in Figures 5 and 5A, the number of layers of thermally reactive layers and isolation layers Is 2, and finally a nanowire array with two layers in the vertical direction is formed.

In this embodiment, the thermal annealing is performed in an oxygen atmosphere. A low-flow oxygen atmosphere is used. The oxygen flow rate can be 8-12L/min, the cavity pressure can be 10-60 Torr, and the process temperature can be 50- At 950°C, a rapid heating method can be used during the heating process to control the thermal budget of the annealing process, and the heating rate can be 50-100°C/sec. After thermal annealing, a silicon oxide fin oxide layer 103 is formed, and the silicon oxide fin oxide layer 103 clamps the fin to form a nanowire.

In step S04, the laminated layer 120 and the fin oxide layer 103 are removed to release the nanowire 130, as shown in Fig. 6 and Fig. 6A (a cross-sectional perspective view of Fig. 6).

In this step, the nanowire 130 surrounded by the laminated layer 120 and the fin oxide layer 103 is released, that is, the laminated layer 120 and the fin oxide layer 103 surrounding the nanowire 130 are selectively removed.

In this embodiment, a high selective ratio chemical release method is used, that is, acid etching is used to release the nanowires. Specifically, the isolation layer 1201 of silicon nitride, the thermally reactive layer 1202 of silicon oxide, and the oxidation The silicon fin oxide layer 103 is removed. Among them, silicon nitride can be removed with hot phosphoric acid (Hot H ₃ PO ₄ ), and silicon oxide can be removed with buffered hydrofluoric acid vapor (Buffer HF). Thus, between the support structures 104 The nanowire 130 is formed as shown in FIGS. 6 and 6A.

In step S05, a gate 150 surrounding the nanowire 130 is formed, as shown in FIG. 8.

Before forming the gate, the nanowire 130 can be further modified, as shown in FIGS. 7 and 7A (the cross-sectional perspective view of FIG. 7), so that the size of the nanowire 130 is more suitable and the surface 140 is flatter. The oxidation process is used for modification. After oxidation, the damage on the surface of the nanowire can be repaired, and then the oxide layer can be removed.

The nanowire 130 is the channel of the device, and the length of the gate on the nanowire 130 determines the length of the channel. In the embodiment of the present application, before the gate is formed, the length of the channel is predefined to realize the channel length The flexible adjustment. It should be noted that the length direction in this embodiment refers to the length direction of the nanowire, that is, the connection direction of the support structures at both ends of the nanowire.

Specifically, first, the nanowire 130 is covered to form a dielectric layer 150, as shown in FIGS. 7 and 7A.

The dielectric layer 150 covering the nanowire 130 can be formed by depositing a dielectric material, such as silicon oxide, silicon oxynitride, silicon nitride, or a stack thereof, and then performing planarization.

Next, the dielectric layer 150 is patterned to expose a part of the length of the nanowire 130, as shown in FIG. 8.

The dielectric layer 150 is patterned by an etching process, and a part of the dielectric layer 150 in the region 152 is removed in the length direction. The nanowires 130 in the region 152 are exposed, and the nanowires 130 in the region 152 will be covered with the gate. In this way, By limiting the length of the nanowire 152, the length of the channel is further defined, and the flexible adjustment of the channel length is realized.

The exposed area 152 may be located in the middle of the entire nanowire, and the length of the area covering the dielectric layer 152 at both ends may be the same or different. The part of the nanowire still covering the dielectric layer 152 may or may not be used to form the source and drain extension regions. .

Then, a gate surrounding the exposed nanowire 130 is formed.

A gate dielectric layer surrounding the exposed nanowire 130 may be formed first, and then a gate surrounding the exposed nanowire 130 may be formed on the gate dielectric layer. Among them, the gate dielectric layer can be, for example, a thermal oxide layer or other suitable dielectric materials, such as silicon oxide or high-k dielectric materials, and high-k dielectric gate materials such as hafnium-based oxides, HFO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, etc. One or a combination of several. The gate may be, for example, polysilicon, amorphous silicon, or a metal gate or a combination thereof, and the metal gate material may be one or more combinations of TiN, TiAl, Al, TaN, TaC, and W.

So far, the gate-around nanowire device of the embodiment of the present application is formed.

The above are only the preferred embodiments of the present invention. Although the present invention has been disclosed as above in preferred embodiments, it is not intended to limit the present invention. Anyone familiar with the art, without departing from the scope of the technical solution of the present invention, can use the methods and technical content disclosed above to make many possible changes and modifications to the technical solution of the present invention, or modify it into equivalent changes. Examples. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments without departing from the technical solution of the present invention based on the technical essence of the present invention still fall within the protection scope of the technical solution of the present invention.

Claims

A method for manufacturing a gate-around nanowire device, characterized in that it comprises:

Providing a substrate on which a fin and a supporting structure at both ends of the fin are formed, and the fin is a semiconductor channel material;

On both sides of the fins, an oxygen-free isolation layer and an oxygen-containing thermal reaction layer are alternately laminated layers;

Perform a thermal annealing process to make the fin react with the oxygen in the thermally reactive layer on both sides to form a fin oxide layer. In the direction perpendicular to the substrate, the fin oxide layer clamps off the fin, and the remaining fin Form nanowires;

Removing the laminated layer and the fin oxide layer to release the nanowires;

A gate surrounding the nanowire is formed.
The manufacturing method according to claim 1, wherein the substrate is a semiconductor substrate, and the fin and the supporting structure are formed by etching the semiconductor substrate.
The manufacturing method according to claim 1 or 2, wherein the support structure is used to form source and drain regions.
The manufacturing method according to claim 3, wherein before forming the laminated layer, further comprising: forming source and drain regions in the support structure.
The manufacturing method according to any one of claims 1 to 4, characterized in that, before forming the laminated layer, further comprising:

A thermal oxidation process is performed to oxidize the surface of the fin and remove the surface of the oxidized fin.
The manufacturing method according to any one of claims 1 to 5, wherein the thermally reactive layer is silicon oxide, and the isolation layer is silicon nitride.
The manufacturing method according to any one of claims 1-6, wherein the thermal annealing process is performed in an oxygen atmosphere.
7. The manufacturing method according to any one of claims 1-7, wherein after releasing the nanowire, before forming a gate surrounding the nanowire, the method further comprises:

The modification process of the nanowire is performed.
8. The manufacturing method according to any one of claims 1-8, wherein forming a gate surrounding the nanowire comprises:

Covering the nanowires to form a dielectric layer;

Patterning the dielectric layer to expose a part of the length of the nanowire;

A gate is formed surrounding the exposed nanowires.
The manufacturing method according to claim 9, wherein the gate includes a metal gate.