200912648 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種晶片糸統’尤指一種•接式 (Cascaded)晶片系統及其啟動方法與訊號傳輸方法。 【先前技術】 晶片系統係經由晶片間同步串列通信介面（Inter- chip synchronous serial communication interface)來傳輸訊號。 常見之標準晶片間同步串列通信介面包括有I2C ( Inter integrated circuit)、SPI (Serial peripheral interface)與微 線介面（Microwire interface )等三種，其中採取二線式傳 輸的I2C以及由I2C所簡化之SMbus利用單一資料線與時 脈線便可雙向通訊，因此被廣泛應用於晶片系統級的通信 控制實務之中。 請參閱第一圖’該圖係為習知技術之串列式晶片系統 之系統架構示意圖。如第一圖所示’晶片系統1 〇包括有一 主控制器晶片12以及複數個從屬晶片]41〜14N，主控制器 晶片12為晶片系統10的控制核心，而從屬晶片mi〜14N 則接受主控制器晶片12的控制，執行週邊應用功能。串列 匯流排16包括有一時脈線162與一資料線164，主控制器 晶片12與從屬晶片141〜14N個別之傳輸谭係平行搭載於 時脈線162與資料線164，主控制器晶片12經由標準協定 與從屬晶片141〜14N溝通，並按照從屬晶片14〗〜14N的個 別位址對晶片作存取與功能控制。 本木1¾明人珠入串列式晶片系統之應用領域，將習知 串列式晶片系統之缺點歸納如下：首先，晶片系統中，每 200912648 的位址值，以利主控制器晶片之識 l 功:r，則極可能造成位址 錯;再者’-般標準串列匯流排 ，从並且’由於匯流排訊躺損耗值將隨傳輸距離的增 大，故而不利於長距離的訊號傳輸。 *v〜、广 个百汉I；又 受曰曰片糸統的連接通信方式。有鑑於此，本案發明人從而 提出本發明’期藉由本纽善以往㈣式S流排的諸多缺 點，以優化晶片糸統的通信控制。 針對上述缺失，業界通常係以附加的驗證程序來防止 位址重複’亚以控制晶片分散度來控制匯流排的傳輸距 離’然其仍囿於固有串列式匯流排的思維，而未f思及改 【發明内容】 因此，本發明之目的係在於提供一種串接式晶片系統 及其啟動方法與訊號傳輪方法，其藉由串接方式來連接主 控制器晶片與每一從屬晶片，並依序設定每一從屬晶片的 位址及啟動從屬晶片的傳輸埠，係可避免位址重複，並使 得晶片系統達成高速傳輪、易除錯與適用於長距離傳輸等 功效。 本發明係揭示一種串接式晶片系統，包括有—主控制 态晶片以及複數個從屬晶片，且該等從屬晶片具有個別之 傳輸琿啟動系統。其中該等從屬晶片其中之一從屬晶片係 以一資料線耦接於主控制器晶片，主控制器晶片及該等從 屬晶片係依序排列，且每一從屬晶片係以一資料線與其前 200912648 級晶片相互耦接。其令 個別之傳料啟等從屬晶片 址值，對該等從屬曰^有專屬位址值，以根據專屬位 r亥寻仗屬晶片執行功能控制。 曰片ΐΓ„—種啟動方法’係適用於所述之串接式BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer system, and more particularly to a Cascaded wafer system, a method for starting the same, and a signal transmission method. [Prior Art] The wafer system transmits signals via an inter-chip synchronous serial communication interface. Common standard inter-chip synchronous serial communication interfaces include I2C (Inter Integrated Circuit), SPI (Serial peripheral interface) and Microwire interface, among which I2C adopts two-wire transmission and is simplified by I2C. SMbus can be used for two-way communication with a single data line and clock line, so it is widely used in wafer system level communication control practices. Please refer to the first figure, which is a schematic diagram of a system architecture of a conventional tandem wafer system. As shown in the first figure, 'wafer system 1 〇 includes a main controller chip 12 and a plurality of subordinate wafers 41 to 14N, the main controller chip 12 is the control core of the wafer system 10, and the subordinate wafers mi~14N accept the main Control of the controller chip 12 performs peripheral application functions. The serial bus bar 16 includes a clock line 162 and a data line 164. The main controller chip 12 and the slave wafers 141 1414N are separately mounted on the clock line 162 and the data line 164 in parallel, and the main controller chip 12 The slave wafers 141 14 14N are communicated via standard protocols, and the wafers are accessed and functionally controlled in accordance with the individual addresses of the slave wafers 14 to 14N. The disadvantages of the conventional tandem wafer system are summarized as follows: First, in the wafer system, the address value of each 200912648 is used to benefit the master controller chip. l Work: r, it is very likely to cause address error; in addition, '---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- . *v~, a wide range of Baihan I; and the connection communication method of the cymbal system. In view of this, the inventors of the present invention have proposed the present invention to optimize the communication control of the wafer system by the many disadvantages of the previous (four) type S flow of the present New Zealand. In view of the above-mentioned shortcomings, the industry usually uses an additional verification procedure to prevent the address from being repeated to control the wafer dispersion to control the transmission distance of the bus. However, it is still in the thinking of the inherent tandem bus. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a tandem wafer system, a method of starting the same, and a signal transmission method for connecting a main controller chip and each subordinate wafer by a serial connection, and By sequentially setting the address of each slave wafer and starting the transmission of the slave wafer, the address repetition can be avoided, and the wafer system can achieve high-speed transmission, easy debugging, and long-distance transmission. SUMMARY OF THE INVENTION The present invention is directed to a tandem wafer system including a master control wafer and a plurality of slave wafers, and the slave wafers have individual transfer port startup systems. One of the slave wafers is coupled to the main controller chip by a data line, the main controller chip and the slave wafers are sequentially arranged, and each slave wafer is connected with a data line and its previous 200912648. The level wafers are coupled to each other. It allows individual subordinate wafer address values to be transmitted, and these subordinates have unique address values to perform functional control according to the exclusive bit.曰 ΐΓ — — 种 启动 启动 启动 启动 启动 启动 启动 启动 启动 启动 启动 启动
統之每一從屬晶片具有㈣存 2輸埠，其中後級傳輪埠係為禁 U 輸-系統資料至—特定從屬晶片； 屬晶嶋-專屬位址定： 出^ «啟動後級傳輸埠，以回應系統資料之設定。 接式日 揭示—種訊號傳輸方法，係適用於所述之串 生 I、先之中斷控制。此訊號傳輸方法之步驟係首 二主控制H晶片對該等從屬晶片下達—中斷要求封包； 等從屬晶片其中之最終一級從屬晶片產生一中斷 =2’以回應中斷要求封包；最後’該最終—級從屬 日曰片經由各個前級從屬晶片’將該中斷回應封 控制器晶片。 于心王土Each subordinate wafer of the system has (4) memory 2 transmission, wherein the rear stage transmission system is forbidden U-transmission-system data to-specific subordinate wafers; belongs to the crystal crucible-specific address setting: output ^ «starting stage transmission埠In response to the setting of system data. The connection type reveals that the signal transmission method is applicable to the serial I and the first interrupt control. The steps of the signal transmission method are that the first two main control H chips issue the interrupt request packets to the slave wafers; the slave level wafers of the slave chips generate an interrupt = 2' in response to the interrupt request packet; finally 'the final one- The level slave slaves respond to the controller chip via the respective slave slave wafers. Yu Xin Wang Tu
At、以上之概述與接下來的詳細說明以及附圖，皆是為了 匕進v #明本發明為達成預定目的所採取之方式、^段 以及功效。而有關本發明的其他目的以及優點，將 的說明以及圖式中加以闡述。 、、 【實施方式】 本發明之串接式（Cascaded)晶片系統係以串接方式 200912648 依序連接主控制器晶片與每— 晶片系統。珠夂關楚_闽 处屬曰日片，從而構成串接式 戈曰月㈣—圖’該®1係為本發明所揭示之串接 弟一具體實施例之系統架構示意圖。如第二 從屑晶片241〜細，且主㈣器晶片22及複數個 主控制器晶月 22鱼Μ曰ίΐ 241〜24N係依序排列，其 曰曰月22與攸屬曰曰片 器晶片2 2為晶片純2 Q 為—大於1之整數。主控制At, the above summary, the following detailed description and the accompanying drawings are all for the purpose, the paragraph and the effect of the present invention in order to achieve the intended purpose. Other objects and advantages of the invention will be set forth in the description and drawings. [Embodiment] The Cascaded wafer system of the present invention sequentially connects the main controller chip and the per-wafer system in a serial connection mode 200912648. The 夂 夂 闽 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ For example, the second chip wafer 241 is thin, and the main (four) wafer 22 and the plurality of main controllers are arranged in sequence, and the 2222 22 and the 曰曰 曰曰 器 wafer are sequentially arranged. 2 2 is the wafer pure 2 Q is an integer greater than 1. Master control
則接受主控制器曰另22^工制核心’而從屬晶片241〜24N σ日日 的控制，執行週邊應用功能。 付Μ明的是，主控制器晶片 中未不），根據主機所下達之指 要曰、主機（圖 的運作。舉例來說，於曰曰片241〜期 , 电細系統中，主機係指電腦之中 域，早&而主控制器晶片22可為中央處 = 肷入式控制器，一般而言，主控制器日曰 ^邊之 控制功能；至於從屬晶片241〜24N則為μ mi予多種 12所控制之通用輸出入埠擴充器、馬達驅：器。=片 器）與背光板驅動器等功能晶片。 風羽控制 主控制器晶片22與從屬晶片241〜24ν 定引擎（Protocol engine)，所述之協定 =具有協 硬體電路資源共同運作，並按照一預定串列體協同 包格式及訊號處理流程，對封包訊號作編解碼^疋之封 部命令訊號組成為串列封包訊號，以及將接將晶片内 包訊號處理轉換為晶片内部訊號格式。又，所^的串列封 列通信協定可為任-標準通信協定或為 4之預定串 定。 蒹自叮之通信協 晶片系統20中，主控制器晶片22產 毅·訊號輸 200912648 出至日"^'脈線260上傳輸，而所有從屬曰 時耦接於眭脱仏 1负伙7离曰曰片241〜24N則同 脈線以接收時脈訊號。主控制器晶 ::ΠΓ81_表級晶片（即從屬晶片如); 2\4 (,ρ^ 從屬晶片20並以另一貝料:線282輪於其後級晶片（即 一、、曰曰 以此類推，最終一級從屬晶片24Ν係以一 資料線28Ν耦接於其前级晶片。 、 晶 晶片（ 241 片系統20啟動時，主控制器晶片22將對每—從屬 241 ' 、24Ν)設定其個別之專屬位址值，以便根 據每-從屬晶片（24卜、24Ν)個別之位址值，來執行 雙向通信與功能控制。為了確保晶片系統20通信的正確性 及避免產生位址重複問題，在尚未完成位址設定之前，從 屬晶片241〜24Ν的傳輸功能係被禁制，經由主控制器晶片 22逐一依序設定每一從屬晶片（241、 、24Ν)的專屬位Then, the main controller is controlled by the main controller and the slave chips 241 to 24N σ day and day, and the peripheral application function is executed. Fu Yuming is, in the main controller chip, not according to the instructions issued by the host, the host (the operation of the figure. For example, in the 241 241 期, period, the system, the host refers to The domain of the computer, early & and the main controller chip 22 can be the central = intrusive controller, in general, the main controller control function; as for the slave wafer 241~24N is μ mi A variety of 12 controlled general-purpose output 埠 expander, motor drive: = chip) and backlight board driver and other functional chips. The wind feather control main controller chip 22 and the slave wafer 241~24ν protocol engine, the protocol=co-hardware circuit resources work together, and according to a predetermined serial body cooperative packet format and signal processing flow, The packet command signal is coded and decoded into a serial packet signal, and the chip internal signal processing is converted into a chip internal signal format. Further, the serial concatenation communication protocol may be a any-standard communication protocol or a predetermined sequence of four. In the communication co-deacon system 20, the main controller chip 22 produces Yi·signal input 200912648 to the day "^' pulse line 260 transmission, and all subordinates are coupled to the 眭 dislocation 1 negative group 7 The 241 to 24N are separated from the pulse line to receive the clock signal. The main controller crystal:: ΠΓ 81_ table-level wafer (ie slave wafers such as); 2 \ 4 (, ρ ^ slave wafer 20 and another shell material: line 282 rounds to its subsequent wafer (ie, one, 曰曰By analogy, the final first-level slave chip 24 is coupled to its pre-stage wafer by a data line 28, and the crystal chip (when the 241-chip system 20 is activated, the main controller chip 22 will be set for each slave 241 ', 24 Ν). The individual unique address values are used to perform two-way communication and function control according to the individual address values of each of the slave chips (24, 24 Ν). In order to ensure the correctness of the communication of the wafer system 20 and avoid address duplication problems Before the address setting is completed, the transfer functions of the slave chips 241 to 24 are prohibited, and the exclusive bits of each of the slave chips (241, 24) are sequentially set via the main controller chip 22 one by one.
址值等系統資料之後，再啟動其與後級晶片間之傳輸功 月匕而主·!工制盗晶片22在設定位址時，係同時芬考之前完 成設定的位址值，以防止位址重複，如此便可使得每一從 屬晶片（241、 、24N)均具有晶片系統20中唯一存在 的位址值。 為了達成上述功能，本案係於每—從屬晶片（24卜 、 24N )内部均設置一傳輸埠啟動系統，以接受位址值設定 及控制其與後級晶片間之傳輸功能。請同時參閱第二圖以 及第三圖’第三圖係為本發明所揭示之從屬晶片之傳輸埠 啟動系統之系統架構圖。如第三圖所示，從屬晶片241具 有一傳輸琿啟動系統2410，傳輸埠啟動系統2410包括有 9 200912648 一前級傳輪埠24n 在哭留0 ^U、—訊號處理模組2412、一系統資料暫 廿 口口早 7〇 24 1 4·丨、/ ϋ y/ ^ 2419 1.,. 及—後級傳輸埠2415。其中訊號處理模 資料斬f π 則級傳輸埠2411、後級傳輸淳2415與系統 前級 耦接於系統資料暫存器單元2 414。 ^Mih '〇輪〗阜24U為讯號收發器（Transceiver)，藉由 ·8/_接於前級之主控制器晶片22，以雙向收發封 ^對Ϊ I訊號處理模組2412轉接於前級傳輸埠2411，用 理疒纟列封包矾號編解碼；後級傳輸埠2415耦接於訊號處 2412與後級之從屬晶片242之間，後級傳輸槔2415 二二:不制狀態，必須接受一致能訊號EN，才能啟動訊 旒傳輪功能。 於-具體實闕’後級傳輸埠2415為—可控制式缓衝 二。BUffei) ’用以暫存經由訊號處理模組2412傳輸之資 π A旎，並根據致能訊號，控制資料訊號之傳輸。After the system data such as the address value, the transmission power between the chip and the subsequent chip is restarted, and when the address is set, the address value is set before the Fen test to prevent the bit. The addresses are repeated so that each of the slave wafers (241, 24N) has an address value that is uniquely present in the wafer system 20. In order to achieve the above functions, the present invention is provided with a transfer start system inside each of the slave chips (24b, 24N) to accept the address value setting and control the transfer function between the chip and the subsequent chip. Please refer to the second figure and the third figure. The third figure is a system architecture diagram of the transmission/deactivation system of the slave chip disclosed in the present invention. As shown in the third figure, the slave wafer 241 has a transfer start system 2410, and the transfer start system 2410 includes 9 200912648. The front stage transfer wheel 24n is crying 0 ^U, the signal processing module 2412, a system. The data is temporarily closed at 7〇24 1 4·丨, / ϋ y/ ^ 2419 1.,. and - after the transmission 埠 2415. The signal processing mode data 斩f π level transmission port 2411, the second stage transmission port 2415 and the system pre-stage are coupled to the system data register unit 2 414. ^Mih '〇轮〗 阜 24U is a signal transceiver (Transceiver), connected to the main controller chip 22 of the previous stage by ·8/_, and the two-way transceiver module is connected to the I signal processing module 2412. The pre-stage transmission port 2411 encodes and decodes the code with the block number; the post-stage transmission port 2415 is coupled between the signal portion 2412 and the slave chip 242 of the subsequent stage, and the latter stage transmits the port 2415 22: The consistent energy signal EN must be accepted in order to activate the signal transmission function. After the - concrete implementation, the transmission 2415 is - controllable buffer 2. The BUffei) ’ is used to temporarily store the π A旎 transmitted by the signal processing module 2412, and controls the transmission of the data signal according to the enable signal.
系統資料暫存器單元2414包括有複數個暫存器 )eglster)’用以暫存從屬晶片24ι個別之專屬位址值等 糸統資料，純倾暫存器單力⑷彳接受系崎料的設定 之後，將輸出致能訊號EN啟動後級傳輸埠2415。 处θ晶片系統20啟動前，從屬晶片241〜24N間的傳輸功 疋被禁制的。晶片系統2〇啟動期間，主控制器晶片22 ，，對其後級之從屬晶片241作存取，傳送系統資料到從 鎢_片24卜訊號處理模組24Π透過前級傳輸埠2411接 ，系统資料，並將系、统資料解碼為内部訊號格式，經由設 疋控制單元2413將專屬位址值等系統資料寫入系統資料 10 200912648 暫存器單元2414。系統資料暫存器單元2414接受系統資 料的設定之後，便隨即輸出致能訊號EN啟動後級傳輸埠 2415。 從屬晶片241的後級傳輸埠2415被啟動之後，主控制 器晶片22便可透過從屬晶片241將系統資料傳輸到下一級 從屬晶片242, k定其專屬位址值，並啟動其後級傳輸埠。 之後，再逐一將系統資料傳輸到從屬晶片243〜24N，設定 每一從屬晶片（241、 、24N)個別之傳輸埠啟動系統均 具有唯一存在之專屬位址值，並啟動其個別之後級傳輸 埠，使得其與後級晶片之間能夠雙向通信。 請參閱第四圖，該圖係為本發明所揭示之串接式晶片 系統之第二具體實施例之系統架構示意圖。如第四圖所 示，晶片系統30包括有一主控制器晶片32及複數個從屬 晶片341〜34N，主控制器晶片32係以時脈線361以及資料 線381耦接於其後級晶片（即從屬晶片341);從屬晶片341 係以時脈線361以及資料線381耦接於前級晶片（即主控 制器晶片32)，並以另一時脈線362以及資料線382耦接 於後級晶片（即從屬晶片342);以此類推，最終一級的從 屬晶片34N係以時脈線36N以及資料線38N耦接於其前級 晶片。 第二圖與第四圖之差異在於第二圖之從屬晶片241〜 24N係同時耦接於時脈線260以接收時脈訊號，而第四圖 之從屬晶片341〜34N則是接收前級晶片所傳輸的時脈訊 號。晶片系統20、30的連接方式使其具有不同特點，首先， 晶片系統30的時脈訊號係經由前級晶片輸出至下一級晶 11 200912648 片=訊號強度可藉由傳輪路徑上之晶片放大，如此一來， 轉如仍可保持穩定的訊號強度，賴通訊正罐 而曰曰片系、、先20的結構則較為簡單，適用於從属晶片 241〜遍^布於主控制器晶片22周圍，訊號傳輸路徑較短 的應用型恶，且相較方t曰g 。λ ^ / 平乂 J、曰日片糸統30，晶片系統20之各級 攸屬晶片（241、 、24ΧΓ λ ία t-. 24N)均可省下一輸出入埠以供其他 應用0吾人可按押會狄去·旦士上山 、、貫矛力考夏來決定晶片系統20、30其中之 任一結構付諸應用。 又串接式曰曰片系統3〇中，從屬晶片均具 有個別之傳輸埠啟動系統，其⑽架構與第三圖之傳輸蜂 ，動系統241G類似’其差異為從屬晶片如〜遍之前級 f輸埠與後級傳解制時傳輪咖喊與㈣訊號，故 於-具體實施例，後級傳輸埠2415包括有二可控制式緩衝 ^分別暫存資料訊號與時脈訊號，並根據系統資料暫存 益早70輸出之錢職控制#料_與時脈城之傳輸。 、接著’請參閱第五圖，該圖係為本發明所揭示之串接 气BB片系4之啟動方法之步驟流程圖，其中相關之系統架 構請同時參閱第二、三圖。如第五圖所示，所述之晶片系 統之啟動方法包括下列步驟： 首先’提供從屬晶片241〜24N分別具有一系統資料暫 存為以及-後級傳輸埠（如第三圖所示，提供從屬晶片24ι 具有一系統資料暫存器單元2414及—後級傳輸埠2415)， 其中後級傳輸埠2415為禁制狀態（步驟S5〇〇 ); 其•人，主控制益晶片22傳輸一系統資料到從屬晶片 241 (步驟 S502); 12 200912648 之後，從屬晶片261將糸統貢料轉換為内部訊號格 式，以將系統資料寫入系統資料暫存器單元2414，使得從 屬晶片241具有一專屬位址值（步驟S504); 最後，系統資料暫存器單元2414輸出一致能訊號EN 啟動後級傳輸埠2415，以回應系統資料之寫入（步驟 S506) 〇 主控制β晶片22完成從屬晶片241的糸統貢料設定’ 使其具有專屬位址值，並啟動其後級傳輸淳2415之後，將 再按照步驟S502〜S506以啟動從屬晶片241之同一程序， 經由從屬晶片241傳輸系統資料到從屬晶片242，將系統 資料寫入從屬晶片242的系統資料暫存器單元2414，使得 從屬晶片242具有一專屬位址值，並啟動其後級傳輸埠。 其後，再逐一依序將系統資料寫入從屬晶片243〜24Ν 的系統資料暫存器單元，使其具有個別之專屬位址值，並 啟動其個別之後級傳輸埠。由以上說明可知，主控制器晶 片22 —次僅設定單一特定從屬晶片之系統資料及啟動其 後級傳輸璋，至晶片糸統之所有從屬晶片241〜24Ν均 被啟動之後，主控制器晶片22便可按照預定串列通信協定 的封包格式與訊號處理流程’對從屬晶片241〜24Ν作§買、 寫控制與中斷控制。 特別提出的是，基於串接式晶片系統20的結構係與串 列式晶片系統截然不同，因此，本案再提出一種訊號傳輸 方法，適用於串接式晶片系統20之中斷控制。請參閱第六 圖，該圖係為本發明所揭示之牟接式晶片系統之中斷控制 之訊號傳輸方法之步驟流程圖，其中相關之系統架構請同 13 200912648 時參閱第二圖。如第六圖所示 輸方法包括下列步驟： 处中斷控制之訊號傳 Μ 7L· 241〜遍下達-中:要求封包 281傳輸至從屬晶片24] =要求封包經由資料線 之後，識別主控制器晶片22:;^ 求封包作解碼“，轉析鱗㈣便對中斷要 料線282將中斷要求封包傳送到下—級從屬：片=由資 從屬晶片242執行與從屬晶片 曰曰片如’而 求封包的詳細内容，並將中斷要求封二二== 推，中斷要求封包將被傳送到最終= 处屬晶片24Ν (步驟S600); 其次’最終—級從屬晶片2你對中斷要求封包作解碼 ，理’識別主控制器晶#22戶斤下達之中斷控制，並解析其 坪細内容之後，便產生-情回應封包，以回應主控制器 晶片22所下達之中斷要求封包（步驟S6〇2);以及 最後，最終一級從屬晶片24N再經由各個前級從屬晶 片將中斷回應封包傳送至主控制器晶片22 (步驟S6〇4)。 請同時參閱第七圖，該圖係為本發明之中斷回應封包 之封包格式之一具體實施例之結構示意圖。如第七圖所 示’中斷回應封包700包括有一起始位元71〇、一最終位 元730以及一回應資料攔720，其中起始位元71〇與最終 位元730係用以確認封包之完整性，而回應資料欄720進 —步被區分為IRQ1〜IRQN等N個部分，其包括至少一位 元資料，用以分別填入每一從屬晶片241、 、24N個別 14 200912648 之中斷回應值。當最終一級從屬晶片24N產生中斷回應封 包700傳送至前級從屬晶片後，其各個前級從屬晶片將按 照中斷要求封包之内容，判斷是否需要回應主控制器晶片 22的中斷控制，倘若判斷結果為是，則需作中斷控制回應 之從屬晶片在接收到中斷回應封包700之後’便會將個別 之中斷回應值寫入中斷回應封包7〇〇内。主控制器晶片7〇〇 接收到中斷回應封包700之後’便能夠知悉從屬晶片 241〜24N的中斷狀態，從而進行後續控制。 藉由以上實例詳述，當可知悉本發明所揭示之串接式 晶片系統及其啟動方法與訊號傳輸方法，係依序設定從屬 晶片個別之位址值’可避免位址值重複；其次，由於串接 式晶片系統的資料訊號是經由晶片次第傳輸，與習知平行 搭載於匯流排的結構迥異’因此當晶片系統發生通信錯等 時’循訊號中斷處，便可容易地找出錯誤原因，達到易除 錯之功效；再者’本發明之串接式晶片系統可利用簡化的 硬體電路來組成與處理封包’以取代標準協定的複雜邏輯 程序，故而可達到高速傳輸之功效；此外，基於串接式曰曰 片系統具有放大訊號強度之功能’故而適用於長距離之訊 號傳輸。 惟’以上所述，僅為本發明的具體實施例之詳細說明 以及圖式而已，並非用以限制本發明，本發明之所有範圍 應以下述之申請專利範圍為準，任何熟悉該項技藝者在本 發明之領域内，可輕易思以及之變化或修飾皆可涵蓋在以 下本案所界定之專利範圍。 15 200912648 【圖式簡早說明】 第一圖係為習知技術之串列匯流排晶片系統之系統架 構示意圖； 第二圖係為本發明所揭示之串接式晶片系統之第一具 體實施例之系統架構示意圖 第三圖係為本發明所揭示之從屬晶片之傳輸埠啟動系 統之系統架構示意圖； 第四圖係為本發明所揭示之串接式晶片系統之第二具 體實施例之系統架構示意圖； 第五圖係為本發明所揭示之串接式晶片系統之啟動方 法之步驟流程圖； 第六圖係為本發明所揭示之串接式晶片系統之中斷控 制之訊號傳輸方法之步驟流程圖；以及 第七圖係為本發明之中斷回應封包之一具體實施例之 結構示意圖。 【主要元件符號說明】 10、20、30 :晶片系統 12、22、32 :主控制器晶片 141〜14N、241〜24N、341〜34N :從屬晶片 16 :串列匯流排 162、260、361 〜36N :時脈線 164、281〜28N、381 〜38N :資料線 2410 :傳輸埠啟動系統 2411 :前級傳輸埠 16 200912648 2412 :訊號處理模組 2413 :設定控制單元 2414 :系統資料暫存器單元 2415 :後級傳輸埠 700 :中斷回應封包 710 :起始位元 720 :回應資料欄 730 :最終位元 S500〜S604 :各個步驟流程The system data register unit 2414 includes a plurality of temporary registers (eglster) for temporarily storing the unique address values of the slave wafers, and the like, and the pure dump register single force (4) After setting, the output enable signal EN starts the post-stage transmission 埠 2415. Before the θ wafer system 20 is started, the transfer function between the slave wafers 241 to 24N is prohibited. During the startup of the wafer system 2, the main controller chip 22 accesses the slave wafer 241 of the subsequent stage, and transfers the system data to the preamplifier transmission 2411 from the tungsten chip 24 processing module 24, the system The data is decoded into an internal signal format, and system data such as a dedicated address value is written into the system data 10 200912648 register unit 2414 via the setting control unit 2413. After the system data register unit 2414 accepts the setting of the system data, it outputs the enable signal EN to initiate the post-stage transmission 埠 2415. After the subsequent stage transfer 2415 of the slave wafer 241 is activated, the master controller chip 22 can transfer the system data to the next-level slave wafer 242 through the slave wafer 241, k determine its unique address value, and initiate its subsequent stage transfer. . Thereafter, the system data is transferred to the slave chips 243 to 24N one by one, and each of the slave chips (241, 24N) is set to have a unique unique address value and start its individual subsequent stage transmission. So that it can communicate bidirectionally with the latter wafer. Please refer to the fourth figure, which is a schematic diagram of the system architecture of the second embodiment of the tandem wafer system disclosed in the present invention. As shown in the fourth figure, the wafer system 30 includes a main controller chip 32 and a plurality of slave wafers 341 to 34N. The main controller chip 32 is coupled to the subsequent wafer by the clock line 361 and the data line 381 (ie, The slave chip 341 is coupled to the front stage chip (ie, the main controller chip 32) by the clock line 361 and the data line 381, and coupled to the rear stage chip by another clock line 362 and the data line 382. (ie, slave wafer 342); and so on, the final stage slave wafer 34N is coupled to its pre-stage wafer with clock line 36N and data line 38N. The difference between the second and fourth figures is that the slave chips 241 to 24N of the second figure are simultaneously coupled to the clock line 260 to receive the clock signal, and the slave chips 341 to 34N of the fourth figure are the receiving front stage chips. The transmitted clock signal. The connection of the wafer systems 20, 30 has different characteristics. First, the clock signal of the wafer system 30 is output to the next stage crystal through the front stage wafer. 200912648 = the signal intensity can be amplified by the wafer on the transfer path. In this way, if the signal strength is still stable, the structure of the communication device is simple, and the structure of the first 20 is relatively simple, and is suitable for the slave wafer 241 to be disposed around the main controller chip 22. The signal transmission path is short and the application type is evil, and compared with the square t曰g. λ ^ / 乂 乂 J, 曰 糸 30 30, all levels of wafer system 20 (241, 24 ΧΓ λ ία t-. 24N) can save the input and output for other applications 0 According to the adjournment of the D.D., the singer, the singer, and the singer, decided to apply any of the wafer systems 20 and 30 to the application. In the tandem splicing system, the slave wafers each have an individual transmission 埠 start-up system, and the (10) architecture is similar to the transmission diagram of the third diagram, and the dynamic system 241G is similar to the slave wafer, such as the previous stage f. In the case of the transmission and the post-stage transmission system, the slogan and the (4) signal are transmitted. Therefore, in the specific embodiment, the post-stage transmission 埠2415 includes two controllable buffers, respectively, for temporarily storing the data signal and the clock signal, and according to the system. Data temporary storage benefits 70 output of the money control #料_ and the transmission of the city. Next, please refer to the fifth figure, which is a flow chart of the steps of the method for starting the series BB film system 4 disclosed in the present invention. Please refer to the second and third figures for the related system architecture. As shown in the fifth figure, the method for starting the wafer system includes the following steps: First, 'providing the slave wafers 241~24N respectively have a system data temporary storage and a rear stage transmission buffer (as shown in the third figure, The slave wafer 24i has a system data register unit 2414 and a post-stage transfer unit 2415), wherein the rear stage transfer port 2415 is in a forbidden state (step S5〇〇); the person, the main control chip 22 transmits a system data. After the slave wafer 241 (step S502); 12 200912648, the slave wafer 261 converts the system material into an internal signal format to write system data to the system data register unit 2414 so that the slave wafer 241 has a dedicated address. Value (step S504); Finally, the system data register unit 2414 outputs the coincidence energy signal EN to activate the post-stage transmission port 2415 in response to the writing of the system data (step S506). The main control β chip 22 completes the slave wafer 241. After the system stipulates that it has a unique address value and starts its subsequent stage transfer 淳 2415, it will follow the steps S502 to S506 to start the same process of the slave wafer 241, via The slave wafer 241 transfers system data to the slave wafer 242, and writes the system data to the system data register unit 2414 of the slave wafer 242 such that the slave wafer 242 has a unique address value and initiates its subsequent stage transfer. Thereafter, the system data is sequentially written one by one to the system data register units of the slave chips 243 to 24, so that they have individual dedicated address values and start their individual subsequent stage transfers. As can be seen from the above description, the main controller chip 22 sets only the system data of a single specific slave wafer and activates its subsequent stage transfer, after all the slave chips 241 to 24A of the wafer system are activated, the main controller chip 22 §Buy, write control and interrupt control can be performed on the slave chips 241 to 24 in accordance with the packet format and signal processing flow of the predetermined serial communication protocol. In particular, the structure of the tandem-based wafer system 20 is quite different from that of the tandem wafer system. Therefore, the present invention further proposes a signal transmission method suitable for the interrupt control of the tandem wafer system 20. Please refer to the sixth figure, which is a flow chart of the steps of the signal transmission method for the interrupt control of the spliced chip system disclosed in the present invention, and the related system architecture is the same as that of 13 200912648. As shown in the sixth figure, the input method includes the following steps: Signal transmission at the interrupt control 7L·241~pass-down: medium: 281 is required to be transmitted to the slave wafer 24] = after the packet is requested to pass through the data line, the master controller chip is identified 22:; ^ Seeking the packet for decoding ", the scaling (4) will be sent to the interrupt request packet 282 to the lower-level slave: slice = dependent slave chip 242 performs with the slave chip 如The details of the packet, and the interrupt request is sealed === push, the interrupt request packet will be transferred to the final=subordinate wafer 24Ν (step S600); secondly, the final-level slave chip 2 decodes the interrupt request packet, After the identification of the interrupt control of the main controller crystal #22, and parsing the details of the ping, the response packet is generated in response to the interrupt request packet issued by the main controller chip 22 (step S6〇2). And finally, the final first-level slave chip 24N transmits the interrupt response packet to the main controller chip 22 via each of the preceding-stage slave chips (step S6〇4). Please also refer to the seventh figure, which is an interruption of the present invention. A schematic diagram of a specific embodiment of a packet format that should be encapsulated. As shown in the seventh figure, the interrupt response packet 700 includes a start bit 71 〇, a final bit 730, and a response data block 720, wherein the start bit is The element 71〇 and the final bit 730 are used to confirm the integrity of the packet, and the response data field 720 is further divided into N parts such as IRQ1~IRQN, which include at least one piece of metadata for filling each of the pieces. The interrupt response value of a slave chip 241, 24N individual 14 200912648. When the final level slave chip 24N generates the interrupt response packet 700 to the previous slave chip, each of the preceding slave chips will judge according to the content of the interrupt request packet. It is necessary to respond to the interrupt control of the main controller chip 22. If the result of the determination is yes, the slave chip that needs to respond to the interrupt control will write the individual interrupt response value to the interrupt response packet after receiving the interrupt response packet 700. After the main controller chip 7〇〇 receives the interrupt response packet 700, it can know the interrupt status of the slave chips 241~24N, and thus Subsequent control. As will be apparent from the above examples, when the tandem wafer system disclosed in the present invention and its startup method and signal transmission method are known, the individual address values of the slave wafers are sequentially set to avoid duplicate address values. Secondly, since the data signal of the tandem wafer system is transmitted through the wafer, the structure is parallel to the conventional bus in parallel. Therefore, when the wafer system has a communication error, etc., it can be easily found by the signal interruption. The cause of the error is to achieve the effect of easy debugging; in addition, the serial-connected chip system of the present invention can use a simplified hardware circuit to form and process a packet to replace the complex logic program of the standard protocol, thereby achieving high-speed transmission. In addition, the tandem-based sputum system has the function of amplifying the signal strength', so it is suitable for long-distance signal transmission. The above description is only for the purpose of illustration and illustration of the embodiments of the present invention, and is not intended to limit the scope of the invention. In the field of the invention, the scope of the invention as defined in the following paragraphs can be easily changed and modified. 15 200912648 [Description of the drawings] The first figure is a schematic diagram of the system architecture of the tandem bus system of the prior art; the second figure is the first embodiment of the tandem wafer system disclosed by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 3 is a schematic diagram of a system architecture of a transmission/deactivation system of a slave wafer disclosed in the present invention; and FIG. 4 is a system architecture of a second embodiment of the tandem wafer system disclosed in the present invention. The fifth figure is a flow chart of the steps of the method for starting the serial chip system disclosed in the present invention; the sixth figure is the flow chart of the signal transmission method for the interrupt control of the serial chip system disclosed in the present invention. FIG. 7 is a schematic structural diagram of a specific embodiment of an interrupt response packet of the present invention. [Description of main component symbols] 10, 20, 30: wafer system 12, 22, 32: main controller chips 141 to 14N, 241 to 24N, 341 to 34N: slave wafer 16: serial bus bars 162, 260, 361 ~ 36N: clock line 164, 281~28N, 381~38N: data line 2410: transmission 埠 startup system 2411: pre-stage transmission 埠16 200912648 2412: signal processing module 2413: setting control unit 2414: system data register unit 2415: After-stage transmission 埠700: Interrupt response packet 710: Start bit 720: Response data field 730: Final bit S500~S604: Step flow
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