TW200912338A - CMOS process compatible MEMS probe card - Google Patents

Abstract

A probe card includes a CMOS chip and a print circuit board. The said CMOS chip based on the standard CMOS-MEMS process is characterized by integrating a probe head with a space transformer. Because of having characteristic of fine pitch and high density, it could be served as a cantilever or a vertical probe card. The standard CMOS process provides multi-layer interconnections, which could assist the probe head in connecting with the external devices, giving the convenience in wiring layout. Furthermore, some passive components or signal-conditioning circuits are easily to be integrated into said CMOS chip to increase the frequency bandwidth and ensure better measuring quality. An array of bumps protruded as testing probes in said CMOS chip are fabricated with an electroforming process, and followed by a polishing process to improve their coplanarity. By several standard MEMS etching processes, the probes can be released and the back via-hole of said CMOS chip can be formed and filled with certain conductive material as solder balls. The final CMOS chip is prone to bond with the print circuit board into a probe card.

Description

200912338 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD The present invention relates to a method for fabricating a probe card, and more particularly to a method for fabricating a probe module, which uses a standard CM〇s process technology to design a probe and a space conversion structure. And the knot and the research and the new technique to make the bump wire copper, and finally read the electromechanical technology to complete the suspension and through hole of the probe. 〇[Prior Art] Under the increasingly advanced and in-depth manufacturing technology of the material body, the crystal shrinkage-i natural 'pad' is also reduced, and the probe device and the probe card can be quickly and accurately surfaced and welded. Pad contact has become a key development direction for wafer inspection technology in the future. Under the consideration of reducing the cost of testing, effectively reducing the test time is also the development direction pursued by various industry players. Therefore, increasing the number of chips (Multi-DUT) tested at the same time is also the goal of probe card manufacturers. Depending on the type of product, the number of grains that can be tested simultaneously (4) varies depending on the number of (10). Because the integrated circuit (1C) is getting smaller and smaller, and the function is getting more and more (the number of strong I/O pins is increasing, the IC soldering arrangement is also changed from the edge arrangement to the matrix two-density arrangement, The traditional cantilever probe card (CantileverProbe Card) does not release κ required 'unit area can not be placed more probes' instead of vertical arrangement of scales' so high-density vertical probe card (ffigh 200912338

The demand side of the Verbal Probe Card is thus revealed. The probe card is divided into the cantilever type and the vertical type probe card according to the difference between the I/O pad and the I/O pad. In the future, the four major directions for the development of probe cards: 卄u,, 'Tianhua·From the semiconductor factory, the micron process was launched in 2001, mixed in 2GG4 years, 9G nanometers, and 65nm in the next year. In the extreme ice-human micron process, the macro probe of the wafer probe card is self-compliant.

Exhibition trend. X 2 'synchronization Xigong this. System single-chip (s〇c) has become the trend of semiconductor development, high-accumulation, high-capacity IC has gradually become the mainstream of semiconductors, the future busy work 5 will be more complicated 'including logic, record The analogy and other Wei block will be completely concentrated on the same wafer, which makes the wafer detection technology more difficult. 3. Applicable wafer level sealing: As the IC gradually moves to the technical level of FlipChip and Wafer Levelpackage, it will be the most critical technology in the future. . 4. Probes for communication chips: Communication is a star industry that continues to expand. The most important part of communication chips is RF Ic. Because of its low current usage, the impedance of external circuits is easy to affect signal transmission. Therefore, the pin The design and manufacturing precision of the card line is the key to developing RF IC testing. As for the structural design of the 揼 card, at present, the semiconductor wafer test at home and abroad still uses the % oxygen to determine the probe square wire, and the gamma probe can be configured according to the position of the electrode plate and the probe can be used. (4) The direct division of the division is large, 200912338. There is good electrical contact between the probe and the electrode plate. In addition, each probe can be positioned in the vertical direction, and it is easy to turn over the electrode plate without the high and low, so it can be applied to the system test of the wafer. In addition, if the needle is damaged, the side probe can be replaced without replacing the whole test module; but the disadvantage is that the electrical and mechanical noise generated by the high frequency component in the measurement process will affect the whole test. As a result, needle measurement was not possible for the electrode plates of minute pitch. The micro-probes made by using micro-electromechanical technology can overcome the above shortcomings, especially in the communication high-frequency "test and female wafer test with small pitch electrode plate, and consider the cost reduction of mass production." The advanced microprobe cards in the development of electromechanical technology are mainly as follows, for example: Yanwei Zhang et al., 1997 [Ref. γ. Zhang, γ.

Zhang, D. Worsham, D. Morrow, and RB Marcus, New MEMS Wafer Pr〇be Card,» MEMS^97, Nagoya, Japan, Jan, 1997, pp. 〇邪5-399·] using MEMS technology to produce Bimorph metal film edge form micro-probe matrix structure, the test principle is mainly to use a double-layer aluminum film to make a layer of heater, the high-frequency way to deform the micro-probe by applying voltage, and use the deformation The planar structure measures the electrode plate or bump (bUmpS) located on the wafer. When the microcantilever is in the length (300~500μπ〇 and the width (40~60μπ〇), the heater power supply is about 50mW. 'The microcantilever has a displacement distance of about 150μηη, and its contact structure and metal electrode have a contact resistance of less than 1Ω. Among them, because this mechanical structure can be actuated to reach the same plane to be tested 200912338 pole The contact can reduce the measurement trouble caused by the height of the electrode plate. However, the disadvantage is that extra __ road must be added, which makes the circuit layout increase difficulty and complexity, and the other side uses high temperature. The method of heating to activate the micro-shadow will affect the resolution and reliability of the afl number 1. Into Takahiro et al. 2000 [Ref. h Takahir〇, R. 如财如, e.

Higurashi, "Fabrication Of Micro IC Probe For LSI Testing,,, 〇Sensors and Actuators A, V〇l. 8〇, 2000, pp. 126-131. Using the SOI wafer technology to create a product of a small arc (arch_shaped beam) Body circuit (IC) probe. Its size is less than 3 breaks 8_ 'the spacing is called μιη, the contact resistance is G. 5ω. It makes (4) the technology of the layer with the film deposition technology, the most used Wei process to strengthen its structure _ Sex, the finished micro-probe can be used as a large integrated circuit (LSI) measurement. 2000 Dong-Seok Lee et al. [Reference D· s. Lee, j γ park, D κ

Kim, and J. H. Lee, "Fabrication Of A Bump-Type Si Probe,,

Microprocesses and Nanotechnology Conference, Tokyo, Japan, July 2000, pp. 76 - 77.] Using SOI wafers and Shi Xi's engraving technology, the probe head is made about 35μηι' cantilever beam about 15μηι′ and the deformation displacement is about 80. |1111 microprobe structure. The structure design can shorten the distance between the probe head and the measuring instrument and the signal connection, so that the signal is not distorted during the high-frequency measurement, and the cost is reduced. 2〇01 Robert B. Marcus et al [Ref. R. B. Marcus, ‘‘A New 10 200912338

Coiled Microspring Contact Technology; 5 2001 Electronic Components and Technology Conference, St. Petersburg, Florida, June 2001, pp. 1227 - 1232 ·] proposes a novel contact technology (c〇ntact technology), the author uses a crimped structure to do To contact the electrode of the analyte. The method is to use the residual stress of the two-layer metal (Cu, Cr), with the sacrificial layer, and then annealed (400~900) °C to cause the cantilever beam to curl. According to the experimental results, under the structure of the crimp diameter of 60 μm, the load can be subjected to a load of 5 〇 mN and the elastic compression deformation position p and 1 of the ΙΟμηι can be generated. 20〇2 years Bong-Hwan Kim et al. [Ref. Β. Η. Kim, S. Park, B. Lee, JH Lee, Β. G. Min, SD Choi, DI Cho, and K. Chun, 4tA Novel MEMS Silicon Probe Card," MEMSO2, Las, Vegas, Nevada, January 2002, pp. 368 - 371.] Fabrication of three-dimensional microprobe structures using (100) single crystal germanium wafers, surface micromachining using microelectromechanical technology and bulk micro Machining, making micro-probe arrays with a pitch less than Q 7 (Vm 'contact force Ug.) The micro-probe structure can be properly laid out and designed with automatic test equipment for wafer level (wafer lever) Test. Kenichi Kataoka et al. 2002 [Ref. K. Kataoka, S. Kawamura, T. Itoh, T. Suga, K. Ishikawa, and Η· Honma, "Low Contact-Force And

Compliant MEMS Probe Card Utilizing Fritting Contact, M MEMSO2, Las, Vegas, Nevada, January 2002, pp_ 364-367.] Using two electro-recording nickel processes in combination with a sacrificial layer to create residual stress during electroforming, enabling electroforming Cantilever 200912338 The beam produces a flat deformation. The advantage is that the electroformed nickel probe has good surface contact characteristics with the aluminum electrode, and the nickel has a lower contact resistance than other metal materials, thereby improving the reliability of the signal measurement.

2003 Y_ghak CHO et al [Ref. Ch Ch, T. Kuki, γ Fukma, H

Fujita, and Β. Kim, "Si_Based Micro Probe Card With Sharp Kmfe-Edged Tips Combined Metal Deposition," Actuators and 〇Microsystems, 12th International Conference, Boston, Massachusetts, Vol.l, June 2003, PP. 774 _ 777 .] Using a KOH anisotropic etch to fabricate a cantilever beam with a tip recess on a single-crystal shredded wafer, and then deposit the probe head by metal deposition, you can make an array by this fabrication process. Microprobe cards with a pitch of less than 40 μm. The advantage is that the probe head can pierce the insulating oxide layer on the surface of the metal electrode, so that the contact effect between the probe head and the electrode plate is increased, thereby reducing the contact resistance and achieving good signal pinning results. 2004^Sang-Jun Park ^ H. Kim, S. J. Park, K. Chun,

D. I. Cho, W. K. Park, T. U. Jun, and S. Yun, “a Fine pitch MEMS

Probe Unit For Flat Panel Display As Manufacturing MEMS Application,» Sensors and Actuators A, Vol A, March 2004, pp. 46-52·] proposed for computer LCD panel TFT (thin_fiim tmnsist〇r)-LCD (liqUid crystal displays ), plasma television (pDp) and flat panel television (FDP) produce blade-type microprobes for measuring various display driver ic and panel quality tests. 12 200912338 K. Kataoka, 2004 [Ref. K. Kataoka, T. Itoh, K. Incme, and τ

Suga, «Multi-Layer Electroplated Micro-Spring Array For MEMS Probe Card; 5 MEMSO4, Maastricht, The Netherlands, January 2004, pp. 733 - 736.] Multilayer Membrane Electroformed Spring-Type Microprobe Arrays, Authors Cast nickel technology, the S-shaped three-dimensional spring structure of seven-layer nickel film, the micro-spring probe structure can be continuously contacted and tested more than 10,000 times at 10mN. The advantage is that the micro-elastic yellow structure can be directly fabricated with the circuit board. Because the direction of its deformation displacement is (vertical direction, when the probe is in contact with the electrode to be tested, there will be no movement in the left and right direction, and it will not damage the electrode surface in a large area.) Si-Hyung Lee, 2005 With Bruce C. Kim [Ref. Si-Hyung Lee, and Bruce C. Kim, "Curled micro-cantilevers using benzocyclobutene polymer and Mo for wafer level probing, Sensors and Actuators A,

Vol. 121, 2005, pp 472-479.] published in the Journal of Sensors and Actuators (j) Cantilever beam and test probes made using BCBandMo layers. They mainly use both Mo layers and BCB layers. The stress relationship causes the structure to curl. However, since this probe structure is also a two-layer film structure, when it is actually used in a probe card, structural delamination and damage are more likely to occur due to the vibration of the machine. -Min Kim [Review Young-Min Kim, Ho-Cheol Yoon, and Jong-Hyun Lee, "Silicon Micro-probe Card Using Porous Silicon Micromachining Technology," ETRI Journal, Vol. 27, Number 4, August 2005, pp 433 -438.] proposed to use KOH etching and annealing treatment 13 is not a flaw

G 200912338 ―Pure (10)) to make the microprobe structure. Its structural specifications are long-term purchase m and thickness 5, while the highest displacement is fine and the contact resistance is small. However, the microprobe structure needs to be annealed for the high temperature equipment of the ankle c. Here, the process towel is very precise (4) the displacement of the microstructure is easily deformed, and the process is easy. Based on the above-mentioned reference _ external reference reading, you can know the micro-probe card made by 枷 机电 micro-electromechanical process, whether it is fine-type micro-addition, surface micro-machining or LIGA technology & 疋下—a semiconductor generation can not The lack of test components, but f high frequency, day m « m and mass manufacturing practices are more favorable to the low-cost & However, the micro-probe card made by the above micro-electromechanical technology is basically a cantilever type, which is difficult to realize the vertical probe card; in addition, it is basically not completed by using a CMOS process, and it is difficult to build a passive component and a circuit, and a passive component. It still needs to be realized on the printed circuit board; it is not easy to realize the small-turning space to turn the brain; therefore, the design and manufacture of the chicken of the present invention, regardless of how the semiconductor technology evolves, the micro-electro-probes fabricated by the micro-electromechanical It can be effectively matched, especially the micro-electromechanical microstructure can be integrated with the circuit, so the advantages of the probe card can be improved, such as smaller size design, increased signal measurement function and increased reliability. The technology of System On Chip is unmatched by conventional assembly probes. 14 200912338 SUMMARY OF THE INVENTION The present invention combines the advantages of a cantilever probe card and a _ electro-acupuncture card card, and has a higher probe density, and uses a moment _ or a plurality of κ at the same time to perform a test with a hybrid configuration. The arm probe technique cannot be overcome, so the advantages of the vertical probe card are gradually revealed. However, at present, the probe side J drawing process or the assembly material of the vertical probe card is difficult to be oiled with precision and miscellaneous control, and the lead element is introduced into the probe type, and the micro-electromechanical residual is used again. Technology, through the lithography, f casting and grinding technology for high-yield, high-precision bump probes, to complete the probe card production. Therefore, the features and advantages of the entire design and process of the present invention are as follows: (1) The vertical probe is fabricated by using a standard CMOS process and an electroformed bump (Bump), and the CMOS multilayer interconnect (interc〇nnecti〇n) is used to complete the small probe. Turn the wiring, even the test circuit. (2) Standardization of CMOS probe wafers, the position of the probe can be determined by the post-process, and the array CM0S probe wafers with different pitches can be provided. When used, the standard CM0S process and electroformed nickel can be used according to customer requirements. The block and the unique precision grinding technology make vertical probes, which can improve the problem of the traditional cantilever probe pin header, and can greatly reduce the gap of the pin. . (4) The probe and the small-to-large space converter (printed into the MOS masking chip and printed with a tin-plated solder ball (s) der Bump) directly on the back side of the wafer with the printed circuit of the probe card The board (PCB) is directly joined to greatly enhance the coplanarity of the entire probe card to less than l〇um, leading the international level of 15_2〇um. 15 200912338 (5) Using the ~® Wei material as part of the probe structure, To improve the past literature, the force of the bump or the metal layer as the probe cannot reach the contact force of several grams or more. (6) «The IIC port is 3, and the ic designer can design the test (5) (10).罙 晶片 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The CMOS probe wafer 33 (hereinafter referred to as the probe wafer) is joined to the printed circuit board 32 for connecting the test instrument. The probe wafer 33 is mainly characterized by designing a cantilever probe structure using standard (10) & round process technology, so that Probe array and space converter (cafe bribe fGrmer) - body As shown in FIG. 2, taking the probe array η of (8) as an example, the 4-space conversion || has a small transition, and the internal connection layout (lnterconnection) of the fine-cut process is included in the connection space of the probe space conversion. The connecting line is provided with a bump from the (four) miscellaneous fixed end to the edge of the U-shaped needle crystal U. The free end of the cantilever probe is provided as a probe probe, and is mostly from the needle chip 33; After the micro-electromechanical processing, the through hole = the edge of the needle wafer 33, and the conductive material % is filled, so that the solderer's wafer 33 has a solder ball on the back surface. Please note that the probe wafer of the present invention is strongly implemented. As shown in Figure 2, the 5X5 probe array is taken as an example, but it is not limited to this. In the figure, the probe of 16200912338 can be smaller and denser. The layout can be intermediate. Each of the 20 probes on the 33 can be array type 21. For the probe head 19, it can be a manufacturing process of a new $CMGS probe card surrounded by a wrapper, which is composed of several main ones = yes _ Process, micro_, simple grinding process ',, ', and the county and equipment are described as follows: CMOS TSMC provides Almost the ⑽_ [Yi in this process is not limited to {) 'probe designed structure, c s perspective 3.~ FIG. 4) with an external circuit connected to the planning. , 'U疋 uses a positive photoresist, a negative photoresist, a polyimide (polyimide) or the like spin-coated on the surface of the substrate' and is exposed by a photomask or a mesh to develop a defined bump 12 structure. From the electric mine, the main structure of the multi-layered bump 丨2 is manufactured by using a combination of a power supply, a clock tank, a heater, and a temperature-controlled feedback device. The simple polishing process is a combination of a polishing device having a polishing pad, a polishing liquid, a wafer carrier, and a polishing liquid to disturb the pump, which can be used to planarize the uniformity after plating and the structure of the bump 12 having a poor thickness. It has the characteristics of good coplanarity and small surface roughness. 17 200912338 Etching process refers to the process of removing the vias 13 and the excess Shixia substrate 4 by means of DRIE or ICP. Sometimes it can also be referred to as wet cooking process. [Manufacturing Program] Step 1: Design the bump 12 probe and circuit wiring using a standard semiconductor process such as TSMC 2p4MCM〇s.35um process (refer to Figure 3 and Figure 4). Step 2: After the finished wafer is off-line (Fig. 5(8)), the copper or metal bump 12 probe structure is fabricated by micro-electric prayer technique and ground to enhance its coplanarity and retain its thick photoresist 3 (Fig. 5). (b)). Applying an adhesive layer 38 to the carrier wafer 37 is bonded to the probe wafer 39 (Fig. 5(c)). Step 4: The crucible substrate 4 is thinned by a grinding technique (Fig. 5(d)). Step 5: Laying the polymer material 15 on the back surface of the probe wafer 39, and then defining the place where the opening is to be etched by using an excimer uv laser as a mask 16 for etching the vias 13 in the next step (Fig. 5(e)). Step 6: Etch a small portion of the hole 17 using ICP (Fig. 5 (cut. Step 7: remove the polymer material 15, re-lay a layer of polymer material 15, and then use an excimer UV laser to open the hole) The place is defined as the next icp to etch the vias 13 and the masks of the excess Shixia substrate 4 ls (graphic system). 18 200912338 5(8)fStep 8: Xian 1CP Remnant Through Hole (ViaS) 13 and Excess Shixia Substrate 4 (Figure 9: Reuse DRIE to engrave the unwanted tears 7 to make the probe away from the step ίο: Use the screen printing technique to fill the vias 13 with the solder ball material ( S〇lder)l4 'and re-weld into a solder ball. In addition, in order to make the inner wall of the through hole (10) can be insulated, the semiconductor hiding of the substrate 4 can be reduced to the leakage current of the transmission shunt (especially high frequency). P高分子lymer Deposition System (PDS), such as the brand and model: pDS2〇1(), can be used to deposit poly(p-phenylene) on the inner wall surface (P〇ly-para_xylylene; In addition to this, other methods of depositing an insulating layer may also be performed, for example, atomic layer deposition (at 〇 mic layer . Oxidized scale conductive ceramics (alumi surface xide n〇nC〇ndUCt1Ve ceramic), plasma chemical vapor deposition of tetraethyl silicon dioxide ("PECVDTE0S"), and passivation layer coating (Bosch passivation) Further, for the smaller through hole 13, the electroless nickel plating may be used to fill the through hole 13 (Fig. 5(D). Step 11: using a wafer cutter, the probe crystal 9 7 CJ is cut and removed. Step 12: Using the flip chip technology, the above-mentioned completed probe crystal #% is combined with the printed circuit board 32, and then the carrier wafer is separated and the thick photoresist 3 is removed to complete the probe card manufacturing step ( Figure 5 (k), the printed circuit board 32 is not shown in the figure), and the probe card assembly diagram is shown in Figure 1. The new method and technique proposed above, for the probe card test integrated circuit chip 'design can be based on Functional integrated circuit (IC) design and synchronization completed, the purpose is to test the functional integrated circuit (ic), including the design of the probe array, 19 200912338; space converter

The design of Cspace tmnsformer), with small turns and large wiring, is done using CMOS multilayer interconnects. For the test integrated circuit chip, the layout required for the design can be simultaneously set with the layout of the functional IC on the same batch of reticle to be taken offline, or separately from the layout of the function 1C. The reason is that the method of the present invention is designed in a CMOS compatible manner, and the size of the probe is also similar to the size of the pad 0ad of the functional integrated circuit (IC), and the dimensional compatibility can be The following three examples are known. [Embodiment 1] Cantilever probe structure In general, the fine pitch cantilever probe structure is used for the LCD driver 1C test. Basically, the LCD Ic pad _) 2 sinks _ is a gold bump ((4)

Bump) 'The force range of the cantilever probe is about %, mainly to avoid scratching the surface of the gold bump by excessive force. So set the simulated force to (10)n to simulate. First of all, consider the process limitation of TSMC .35 2Ρ4Μ, which can be used as the material of the film structure, such as oxidized stone eve, 11, nitriding dream, Ming and so on. Among them, nitriding seconds, oxidized stone eve, good choice of materials (because of the Young's coefficient and the lodging strength are better than the rest). Moreover, in the future, the material _ spacing of the LCD will be smaller and smaller, and the length of the seven-array and coffee to simulate the length of the cantilever is selected as ^^ claw, 1.4mm, l.6mm, Umn^2mm. However, the support by the film is not sufficient for the design to retain a portion of the 矽 (thickness of 53μηι, 63μηι, 73μηι, and 83μιη, respectively) to enhance the strength of the support cantilever. After the analysis of the simulated software (Fig. 6(a)~6(c)), when the displacement of the probe measuring point needs to be 75.9μηι, and the width is set to 20μηι: a• If the thickness is 53μιη, the length can be Select 1mm b·If Shishi eve thickness 63μιη, length can choose 1.2mm c. If 矽 thickness 73μηι, length can choose 1.4mm d. If 矽 thickness 83μηι, length can choose l.6mm more in line with specifications, and its maximum stress Does not exceed the material's own lodging stress. However, as the resolution of the LCD is higher and the width of the process line is smaller, the number of pads 2 will be smaller and closer. The width and spacing of each cantilever can be adjusted by applying this process. When the width is narrowed, it is easy to measure the application end by simply adjusting its length or etching the thickness of the substrate 4. For example, when the probe width is 15|1111, a• if the thickness is 53μηι, the length can be selected as 95.95mm b. If the thickness is 63μπ], the length can be selected l lmni c. If the thickness is 73μιη, the length can be selected as usmm d.矽 thickness 83μ [η, length can be selected 丨 4mm [Embodiment 2] The cantilever probe structure can be a folded curved type 35 to implement a high density vertical array probe card. Use the 2P4M CMOS 0.35um process to design the bump 12 probe and the 200912338 circuit layout (Figure 7(a) and Figure 7(b)). Using the flip chip technique, the completed wafer 33 is bonded to the printed circuit board 32 to complete the fabrication of the probe card (Fig. 1). [Embodiment 3] The cantilever probe structure may be a spiral type 36 to implement a high-density vertical array probe card. The bump 12 probe and circuit wiring were designed using a 2P4M CMOS 0.35um process (Fig. 8(a) and Fig. 8(b)). Using the flip chip technique, the completed wafer 33 is bonded to the D printed circuit board 32 to complete the fabrication of the probe card (Fig. 1). Two vertical probe structures of the second and third embodiments: since the coplanarity of the contact bumps 12 is similar after grinding, the force range of the vertical probe is set to be about 3 g. The force of the needle contact was set to 0.0294N for simulation. First, the TSMC .35 2P4M process is still taken as an example to consider its limitations. The process can be used as a material for thin film structures such as tantalum oxide, tantalum, tantalum nitride, aluminum, and the like. 〇 Among them, gasification and oxidation are the best choice materials. For the purpose of the probe wafer test function 1C, consider the pad 2 pitch of the IC, and simulate the side area of the probe to be ΙΟΟμηι and 80μηη, and select 2〇μιη in terms of width. Since it is not enough to support by the film, a part of the 矽 (thickness of 2 〇μπι, ΙΟμηι, and 5μιη) is retained in the design to enhance the strength of the support cantilever. After the results of the simulation software analysis (Fig. 9(a) to 9(c)), the safety factor is set to 3, and the displacement of the probe point is set to 20 to 40 μm. For the second and third embodiments, if the length is ΙΟΟμιη, the I degree 20μπι, the thickness is ΙΟμπι; if the length is 8〇μπι: the width ΐ6μπι, 22 200912338, the thickness of the stone can meet the specifications, and the most regional force is not Will exceed its own lodging stress. However, as the IC process is smaller, the number of transfer 2 will be smaller, and the more it will rely on the secret to hide the handle, the only miscellaneous materials will be cantilever = degree and spacing arbitrary. When the width is narrowed, only f is adjusted to see the thickness of the substrate 4, and it is easy to reach the demand of the measuring application. Although the present invention has been reduced by the above-described preferred embodiment, it is not used. To limit Γ

The invention is to be construed as being limited by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS In order to make the above and other objects, features and advantages of the present invention more obvious, the detailed description of the drawings is as follows: ', Figure 1. The probe card of the present invention, respectively It consists of a probe wafer and a printed circuit board. 2 is a layout diagram of a CMQS vertical probe circuit of the present invention. Figure 3. The layout of the CMOS probe of the present invention. Figure 4. Various layouts of the CM〇s probe card of the present invention. Figure 5(8) is a flow chart showing the process steps of the CM〇s probe of the present invention. Figure 6 (a) to ϋ 6_ The present invention is the maximum stress value of the elongated needle, 23 200912338 maximum strain value, maximum displacement amount, Figure 7 (8) to Figure 7 (b) is the second embodiment of the CMOS sensor of the present invention Layout on top view with perspective view. 0 8 (8) to 8 (b) is a top view and a perspective view of a layout of a third embodiment of the CMOS probe of the present invention. /, Max. Fig. 9 (8) to Fig. 9 (8) are stress values, maximum strain values, and maximum displacement amounts of the vertical probes of the second and third embodiments of the present invention.

[Main component symbol description] 1· 5x5 array probe (including bump) 2·pad used for small turn large 3. Thick photoresist 4. Shi Xi substrate (3) Substrate) 5. Metal layer (Matel) 6. Window Via (tungsten metal plunger) 7·Oxide layer 8·Polycrystalline metal layer (n+p〇i) 9·Polycrystalline metal layer (N+p〇2) 10. Nitrogen Nitride 11. Copper wire 12·copper pilh bumps laid on a printed circuit board 13. Throughs holes (vias) etched by DRIE or ICP 24 200912338 14. Solder (Solder) 15. Polymer material 16. Mask engraved with vias 17. Use ICP to etch a small portion of Vias holes 18. #刻透孔 (vias) and the mask of the excess Shixi substrate 19. Slim type Probe 20. Ring probe 21. Array probe 22. Part of the Array probe Figure 23. Improved type 1 probe at unit area 10 〇 "mx 100//m 24. Modified type 2 probe in unit area 10〇"mx 100//m 25. Modified type 1 probe in unit area 80"mx 80/zm 26. Modified type 2 probe is returned after the line area is 80/zm x 80/zm 27. Electroplated probe position 28. Piezoresistive structure 2 9. Signal line 30. Connect Vout 31. Connect Vin(+) 32. Printed circuit board 33. Probe chip 34. Conductive material 25 200912338 35. Folded curved type 36. Spiral type 37. Carrier wafer (Carrier Wafer) 38 Adhesive Layer 39. Probe Wafer Γ 〇26

Claims (1)

200912338 X. Patent application scope: 1. - The needle card card is mainly made up of the printing of the probe chip and the connection tester (4). The probe chip is mainly characterized by the use of standard complementary gold = body and Micro-electromechanical (Na 4_) process technology designed to produce cantilever probe knots with multiple probe arrays and space converters (combat e transf〇rmer) - body _ space converter with small turn large function, is the use of (10) s process interconnect Line system bureau / (such as (10) Tenetet (10)) Naren probe as the connection of the ride, the road «arm type _ set (four) outside the expansion probe crystal "edge = (four) Na arm probe free end with convex The block acts as a probe, and the probe hole is probed by the micro-electromechanical post-process through the micro-electromechanical post-process. 2 = coffee, and filled with conductive material, so that the back of the probe crystal has tin: • According to the prospect of the applicant city Needle card, the structure of the needle can be slender, to carry the cantilever probe card with fine pitch. ',,, 3. Please use the probe card of i, the cantilever probe structure can be Folding the bow in the m "density vertical type ship needle card. 1 _ Shenxiang Township 1 probe card, the cantilever probe structure can be used to implement the density vertical array probe card. ',,, ', 疋 5 · ^ Please use a simple needle card, the clearing type tearing structure in the thick household side 2 _ process of the interconnected metal layer and _ layer, you can enter: step 3 etching Retain the different thickness of the wafer material to adjust the force of the probe / 6. According to the patented magical probe card, the probe space conversion connection line 27 200912338, further can be included in the transmission line compensation passive Component or signal processing circuit to increase the bandwidth and quality of the measurement signal. 7. The probe card according to claim 1, wherein the bumps are made by microelectroforming technology and the coplanarity is increased to within ±3//m via a grinding process. 8. The test integrated circuit chip used in the probe card is completed by the standard CMOS process and the micro-electromechanical process. The design is synchronously completed according to the functional integrated circuit (1C) design, in order to test the functional product. The body circuit (1C), including the design of the probe array; the design of the space transformer, with small to large wiring, is done using CMOS multilayer interconnects. 9. According to the test integrated circuit chip of the application patent No. 8, the layout required for the design can be simultaneously arranged with the layout of the function 1C on the same batch of the mask to be simultaneously taken offline. 〇 1〇. According to the test integrated circuit chip of the application patent No. 8, the layout required for the design can be obtained separately from the layout of the function 1C. Ι〇. According to the test article of the patent application No. 8, the free end of the probe array can use a micro-electroformed bump to make a vertical probe. U. According to the test integrated circuit chip of the application patent No. 8, the design advancement can be incorporated into the transmission line compensation passive component or signal processing circuit to increase the bandwidth and quality of the measurement signal. 12, according to t, please make a thorough test of 8 integrated circuit ", the probe array of its towel 28 200912338 probe structure can be slender type, to implement the cantilever probe of fine pitch. The 8th product of the township circuit chip, wherein the probe array has a 1 probe structure which can be folded and bent to implement a high-density vertical array probe. The test integrated circuit according to claim 8 of the patent application The wafer, wherein the probe array has a 1 & needle structure, can be a spiral type to implement a high density vertical scale probe. 15', according to the patent application No. 8 _ prototype f-channel wafer, the probe array of the towel has a ferrule structure in the thickness direction except for the metal layer and the _ layer of the (10) s process _ connection, The thickness of the probe is adjusted by retaining different thicknesses of wafer material by silver engraving. 6' A method of using a standard (10) S_MEMS process technology to apply a magnetic needle card, the main steps of which include: ~ shoulder 1.1 designing a bump probe and circuit wiring on a CMOS process on a probe wafer; Exhaustion 2. Micro-electroforming technology to make copper or metal bump probe structure; Step 3: f-loading the coating on the wafer - the adhesion layer and the front side of the probe day and day δ, step 4: using grinding technology矽The substrate is thinned; and the step is to penetrate through the pitting step 5: a mask is formed on the back surface of the probe wafer with a small portion of the hole in the polymer material; Step 6: etching a small portion of the through hole; 7: Remove the polymer material 're-layered with a layer of polymer material, then 29 200912338 'Step to etch through, define the wire where the hole is opened, as a mask for the lower hole and the excess enamel substrate; · Step 8^ Continue to make the detachment of the squid in the probe crystal „secret before the hole and remove the unnecessary oxygen cut from the side of the stone 基 步 step·^ 9′; Step 10: Fill the through hole with the solder ball Material and reflowed into a solder ball; Step probe wafer and carrier wafer - touch and remove to become a probe wafer, V step 12. Using the flip chip technology to combine the completed probe wafer with the printed circuit board to remove the polymer material, complete the exploration The steps for making the needle card. 17. The test integrated circuit wafer according to claim 16, wherein the step 8 further enables the inner wall of the through hole to have an insulating material. 30 200912338 VII. Designation of Representative Representatives (1) The representative representative of the case is: (4) Figure (2) The symbol of the symbol of the representative figure is simple: 2. The Pad 19. Slender probe used when turning small 100/zm 100 /zm 80 //m 80 //in 23. The modified type probe is 10 〇//m per unit area: 24. The modified type 2 probe is 100/zm per unit area: 25. Improved one type probe The needle is in the unit area of 80/zmx 26. The modified type II probe is in the unit area δΟμπιχ VIII. If there is a chemical formula in this case, please disclose the chemical formula that best shows the characteristics of the invention: 200912338 Patent specification W/33/7r (The format, order and bold text of this manual should not be changed at all. ※Please do not fill in the marking part. ※Application number: 096133175 ※Application date: 96.09.06 Classification: 1. Name of the invention: (Chinese/English) Qb/夂 (2006.01) CMOS process compatible MEMS probe card.丨& 1/0^( (2006.01) CMOS process compatible MEMS probe card II. Applicant: (1 person in total) Name: (Chinese/English) Huang Rongtang / Huang, Jung-Tang Representative: (Chinese / English) Address of residence or business office: (Chinese/English) 5F, 5th Floor, 7th Floor, No.7, Lane 10, Bade Road, Taipei, China, 5, Section 2, Bade Rd., Taipei Nationality: (Chinese/English) Chinese Republic of China / Republic of China III. Inventor: (5 in total) Name: (Chinese / English) Huang Rongtang / Huang, Jung-Tang Xu Houyi / Hsu, Hou-Jun Wu Changxiu / Wu, Chan-Shoue Li Guozhen / Lee , Kuo-Yu Zhao Benshan/Chao, Pen-Shan Nationality: (Chinese/English) Republic of China / Republic of China Republic of China / Republic of China 200912338 probes can be smaller and denser. Figure 3 supplement, layout 'can Sigh in the middle of the double row 20, can be _ type 21. His needle 19 'can be surrounded by the brewing of the entire new CM0S probe card manufacturing process, is made up of several major clothing U made ' respectively CM0S process , lithography process, micro-test process, simple grinding Process and rotten process. Its __ and equipment first explained as follows: CMOS process is _ TSMC provides 2p4M cm 〇 s (four) process (but not this secret), probe structure design, complex OS probe various layout (Figure 3·~Fig. 4.) Planning with external connection circuit. The lithography process is to spin the photoresist, silk, pGlyimide_qing, etc. on the surface of the substrate, and expose it with a mask or mesh. The structure of the bump 12 is a micro-electroplating process with a power supply, a new tank, a heater, a temperature-controlled feedback device, etc., which can make a main structure of the multi-layered bump 12. The simple grinding process is It is a combination of a polishing device having a polishing pad, a polishing liquid, a wafer carrier, and a slurry agitation pump, which can be used to planarize the structure of the bump 12 with uniformity after plating and roughness, so that the coplanarity is good. And the surface roughness is small. 17 200912338 Step 8: Etch the vias 13 with the excess tantalum substrate 4 using ICP (Fig. 5(h)” Step 9: Reuse the DRIE money to engrave the unwanted xide7, Making the prototype of the probe (Fig. 5(i)) Step 10: The vias 13 are filled with solder ball material 14 by screen printing techniques and soldered back to solder balls. In addition, in order to enable the inner wall of the vias 13 to have an insulating material to reduce the leakage current of the semiconductor substrate of the germanium substrate 4 to the transmission signal (especially high frequency), a polymer chemical vapor deposition system can be used ( P〇lymer (DePositlon System (PDS)), for example, Wei brand and model: PDS2010 deposits poly-para-xylylene (paryiene) on the inner wall surface. In addition, other methods of depositing insulation layers can also be used. For example, atomic layer deposition (At〇mic layer d印 Siti〇n). ("ALD") using Alumi_ 〇xide non-conductive ceramic, plasma chemical vapor deposition of tetraethyl Tetraethyl silicon dioxide ("PECVDTE0S"), and Bosch passivation coating. Further, for the smaller through holes 13', electroless nickel plating may be used to fill the through holes 13 (Fig. 5(j)) Step 11: Using the wafer dicing machine, the probe wafer 39 is cut and removed together with the carrier wafer 37. Step 12: Using the flip chip technology, the completed probe wafer 33 is Printed circuit board 32 combined Separating the carrier wafer and removing the thick photoresist 3, completing the probe card fabrication step (Fig. 5 'the printed circuit board 32 is not shown in the figure), and the probe card assembly diagram is shown in Fig. 1. The new method proposed above And the technology, the test integrated circuit chip for the probe card, the design can be completed synchronously according to the design of the functional integrated circuit (10), the purpose is 19 200912338 road, further can be included in the passive component or signal processing circuit of the transmission line compensation, increase Measuring the bandwidth and quality of the signal 7. According to the probe card of the first application of the patent, the bumps are made by micro-electroforming technology and the coplanarity is improved to ±3//[11 within the polishing process) 8. The test integrated circuit chip used in the probe card is completed by the standard process and the micro-electromechanical process, and the design is synchronously completed according to the functional integrated circuit (IC) design. Test the functional integrated circuit (IC), including the probe array's ό 、, space converter (Space fransf 〇rmer) design, with small turn large wiring, is the use of CMOS multilayer interconnect (interconnecti〇n) is completed. 9. According to the financial application, the eighth item _ trial miscellaneous·, the layout required for the design can be simultaneously set with the layout of the function 1c on the same batch of reticle to obtain the same line at the same time. 10. According to the test integrated circuit chip of the application patent No. 8, the layout required for the design can be obtained separately from the layout of the functional IC. 11. According to the test integrated circuit chip of claim 8, the free end of the probe array of the towel can be made of a micro-electroformed bump to form a vertical probe. U According to the test integrated circuit chip of the patent application No. 8, the design can further be incorporated into the passive component or signal processing circuit of the transmission line compensation, increasing the bandwidth and quality of the measurement signal. 13. The test integrated circuit wafer according to claim 8 of the patent application, wherein the probe array has a slender type to implement a fine pitch cantilever probe. Detecting the ride to the township 8 to the post of Long Wei, the simple needle array of its 〖5 basis, kiss the relay array probe. Exploring the two touches, ", the array of shots / structure can be turned over to implement high-density vertical array probes. Probe: Two: test the integrated circuit chip of the factory, the axis U direction except by (4) The process of interconnecting the metal layer disk via Cj: step by adjusting the thickness of the wafer material to adjust 17.- Using the standard (10) S-MEMS silk wire gamma card method, the steps include: 〃 Steps Use CMOS process, route wiring; design bump probe and electrical on the probe wafer. Step 2: Make copper or metal bump probe structure using micro-electroforming technology. Step 3: Coating on the carrier wafer - The adhesion layer of the layer is connected to the front surface of the probe wafer. Step 4: The ruthenium substrate is thinned by a grinding technique; and the penetration of the ruthenium substrate is defined. Step 5: Laying a polymer material on the back surface of the probe wafer and engraving a small hole Step 6: Etching a small portion of the through hole; Step 7··Removing the polymer material, re-laying a layer of polymer material, and then 29 200912338 ==== to 'below the next step' 8: y money needle crystal _ surface _ continuous material and casting excess step 9: _ unwanted oxygen cutting, making a probe _; V step perforated shell 10. The solder balls fill material, and back into a fresh solder ball; The thiol step probe wafer and the carrier wafer are cut and removed to become probe crystals. Step 12: Completed probe wafer and printed circuit board '. After the molecular material is transferred, the probe card is completed. 18. According to the project, 17 items of the test circuit are used, and the stepping step can make the inner wall of the through hole have an insulating material. 30