CN111693738A - Low-temperature test structure of multichannel high-frequency chip - Google Patents
Low-temperature test structure of multichannel high-frequency chip Download PDFInfo
- Publication number
- CN111693738A CN111693738A CN202010402144.5A CN202010402144A CN111693738A CN 111693738 A CN111693738 A CN 111693738A CN 202010402144 A CN202010402144 A CN 202010402144A CN 111693738 A CN111693738 A CN 111693738A
- Authority
- CN
- China
- Prior art keywords
- chip
- circuit board
- tested
- interface circuit
- printed circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
- G01R1/0416—Connectors, terminals
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
- G01R31/2874—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature
- G01R31/2877—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature related to cooling
Abstract
The invention relates to a low-temperature test structure of a multi-channel high-frequency chip, which comprises a chip positioning printed circuit board, a multi-channel interface circuit board and a pressure device, wherein the chip positioning printed circuit board is used for placing a chip to be tested; the multichannel interface circuit board is provided with a plurality of paths of metal probe structures, and the metal probe structures are used for realizing signal input and output of a chip to be tested and external equipment; the pressure applying device is used for applying pressure to enable the pins pad of the chip to be tested on the chip positioning printed circuit board to be in contact with the multi-path metal probes on the multi-channel interface circuit board so as to realize electric connection. The invention can ensure the integrity and the non-damage of the chip in the test.
Description
Technical Field
The invention relates to the technical field of superconducting digital integrated circuit testing, in particular to a low-temperature testing structure of a multi-channel high-frequency chip.
Background
Future developments in superconducting digital integrated circuits require extensive testing using a large number of input/output (I/O) lines to apply independent bias control, input test signals and monitor the output of the different sub-circuits. There is an increasing demand for standardized test structures corresponding to various complex superconducting chips and multi-chip modules. Such test structures must support multiple I/O lines, be easy and cost effective to operate, and support long-term automated testing. Furthermore, in the development cycle of superconducting integrated circuit chips, since the design infrastructure and the manufacturing process of integrated circuits are relatively immature, there is often a need to iteratively improve superconducting integrated circuit designs by obtaining feedback from test manufactured chips. It is necessary to perform a rapid test after manufacturing a plurality of chips to shorten the design-manufacturing-test period. Therefore, it is required to design a chip test module that can rapidly evaluate a superconducting chip and can perform a long-time test.
The existing test scheme basically realizes the electric connection by carrying out gold wire bonding on the chip and the lead circuit board, and the mode can cause certain pollution (such as gold wire residue or scratch on a chip pin) and even damage to the chip, so that the chip can not be kept intact, and repeated tests are carried out for a plurality of times. Basically, these superconducting chips, in most cases, become candidates for installation in existing systems or new systems if the development cycle is completed, and require more extensive testing. Typically, they will be evaluated comprehensively under various operating conditions (e.g., different temperatures) and in conjunction with other portions of the system (e.g., other low and room temperature electronics). To ensure compatibility with existing systems and their external interfaces, as well as the development of other electronic devices, it is often necessary to perform a large number of different modes of testing, and to run these candidate systems plugged into the device for several weeks in a serial fashion. Therefore, a universal modular chip test structure needs to be designed to meet the diversified test requirements of the superconducting integrated circuit chip.
The prior patent publication No. CN104764909A is entitled "convenient chip test seat for extremely low temperature measurement", which uses vertical metal spring needle to realize the up-and-down connection of sample test point and Pad on PCB circuit board, and has the following disadvantages: 1. the size of the metal spring pins is limited (the metal spring pins cannot be machined too small, the minimum size is about phi 0.4mm, a certain gap is required between the spring pins and is at least 1mm), the test point spacing of a sample chip capable of being tested cannot be too small, the contact Pad of the test point cannot be too small, and the test point Pad of the sample chip is required to be more than or equal to 0.4mm, and the Pad spacing is required to be more than 1 mm). However, the Pad of many integrated circuit chips is smaller than phi 0.4mm, and the Pad pitch is smaller than 1 mm; 2. the metal spring needle structure vertically connected up and down can not be used for high frequency, is only suitable for low frequency, and has serious high-frequency impedance mismatch and great loss.
Disclosure of Invention
The invention aims to provide a low-temperature test structure of a multi-channel high-frequency chip, which can be suitable for chips of various sizes and ensure the integrity and the non-damage of the chips in the test.
The technical scheme adopted by the invention for solving the technical problems is as follows: the low-temperature test structure of the multichannel high-frequency chip comprises a chip positioning printed circuit board, a multichannel interface circuit board and a pressure device, wherein the chip positioning printed circuit board is used for placing a chip to be tested; the multichannel interface circuit board is provided with a plurality of paths of metal probe structures, and the metal probe structures are used for realizing signal input and output of a chip to be tested and external equipment; the pressure applying device is used for applying pressure to enable the pins pad of the chip to be tested on the chip positioning printed circuit board to be in contact with the multi-path metal probes on the multi-channel interface circuit board so as to realize electric connection.
And a digging groove with the same size as the chip to be detected is arranged in the middle of the chip positioning printed circuit board.
The chip positioning printed circuit board is provided with a first screw hole on an extension line of a diagonal line of the digging groove.
The multi-channel interface circuit board is characterized in that a through hole with the same size as a chip to be tested is formed in the middle of the multi-channel interface circuit board, multiple paths of metal probe structures are arranged on four sides of the through hole, one end of each multiple path of metal probe structure extends into the position, where the chip to be tested is placed, of the chip positioning printed circuit board, and the other end of each multiple path of metal probe structure is connected with high-frequency connectors welded around the multi-channel interface circuit board through wiring.
And the multichannel interface circuit board is provided with a second screw hole on an extension line of a diagonal line of the through hole.
The pressing device comprises a base, a suspension, a threaded screw rod and a pressing block, wherein a pressing hole is formed in the middle of the base, the pressing block is arranged in the pressing hole, and a bulge is formed at the bottom of the pressing block; the base is provided with the suspension, and the middle of the suspension is provided with a threaded hole; one end of the threaded screw rod penetrates through the threaded hole to be connected with the pressing block.
Advantageous effects
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages and positive effects:
the invention designs a multi-channel interface circuit, the interface of which connected with the superconducting integrated circuit chip is a broadband multi-needle low-temperature probe structure, and the probe and the chip are electrically connected by using mechanical pressure, thereby ensuring the completeness and the no damage of the chip in the test. In addition, the invention modularizes the test structure of the whole chip, is independent and universal and is convenient to disassemble and assemble.
The invention adopts the multi-channel interface circuit board and the chip positioning printed circuit board, and because the minimum line width of the PCB processing technology can be smaller than 0.1mm, the minimum size of the metal probe structure can be smaller than 0.1mm, and the Pad of the sample chip can also be smaller than 0.1 mm; the minimum distance can be smaller than 0.1mm according to the processing technology of the PCB, and the Pad distance of the sample chip can be smaller than 0.1mm, so that the test point distance of the sample chip is ensured to be too small, and the test can be carried out under the condition that the contact Pad of the test point is too small. In addition, the metal probe structure of the invention is manufactured on the PCB, the probe and the circuit connected with the probe can be manufactured with impedance matching according to the material used by the PCB, and the PCB and the sample chip share the same ground, therefore, the test structure of the invention is suitable for high frequency.
The pressing device adopts a threaded screw rod structure with the height capable of being adjusted up and down, and the pressing block can be controlled to move up and down by rotating the threaded screw rod during testing, so that the pressing block can press the chip to be tested and the metal probe. And the adjustable device is suitable for chips with more thickness sizes.
Drawings
FIG. 1 is a schematic overall structure diagram of an embodiment of the present invention;
FIG. 2 is a schematic diagram of a chip-on-board configuration in an embodiment of the invention;
FIG. 3 is a schematic diagram of a multi-channel interface circuit board according to an embodiment of the invention;
fig. 4 is a schematic structural view of a pressing device in an embodiment of the present invention.
Detailed Description
The invention will be further illustrated with reference to the following specific examples. It should be understood that these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. Further, it should be understood that various changes or modifications of the present invention may be made by those skilled in the art after reading the teaching of the present invention, and such equivalents may fall within the scope of the present invention as defined in the appended claims.
The embodiment of the invention relates to a low-temperature test structure of a multi-channel high-frequency chip, which comprises a chip positioning printed circuit board 1, a multi-channel interface circuit board 2 and a pressure applying device 3, wherein the chip positioning printed circuit board 1 is used for placing a chip to be tested; the multichannel interface circuit board 2 is provided with a plurality of metal probe structures, and the metal probe structures are used for realizing signal input and output of a chip to be tested and external equipment; the pressure applying device 3 is used for applying pressure to enable the pins pad of the chip to be tested on the chip positioning printed circuit board to be in contact with the multi-path metal probes on the multi-channel interface circuit board so as to realize electric connection.
The low-temperature test structure of the multi-channel high-frequency chip of the embodiment can realize the low-temperature test of the multi-channel high-frequency chip which is rapid and lossless (lossless to the chip), wherein an interface of the multi-channel interface circuit board and the superconducting integrated circuit chip is of a broadband multi-pin low-temperature probe structure, the probe is electrically connected with the chip by using mechanical pressure, and the completeness and the lossless of the chip in the test are ensured.
As shown in fig. 2, a groove 11 with the same size as the chip to be tested is formed in the middle of the positioning printed circuit board 1. Chip location printed circuit board 1 is in be provided with a plurality of first screw 12 on the extension of the diagonal of digging groove 11, can fix location printed circuit board 1 on cold platform 4(4.2K) through a plurality of set screws pass first screw 12, and the chip that awaits measuring is put into middle digging groove 11.
As shown in fig. 3, the middle of the multi-channel interface circuit board 2 is provided with through holes 21 having the same size as the chip to be tested, four sides of the through holes 21 are provided with multi-path metal probe structures 22, one ends of the multi-path metal probe structures 22 extend into the positions of the chip positioning printed circuit board where the chip to be tested is placed, i.e., into the grooves 11, and the other ends of the multi-path metal probe structures are connected with high-frequency connectors 23 welded around the multi-channel interface circuit board 2 through wires on the multi-channel interface circuit board 2. In this embodiment, the top layer circuit metal of the multi-channel interface circuit board 2 is beryllium copper, and the metal probe structure is a beryllium copper probe structure. The multichannel interface circuit board 2 is provided with a plurality of second screw holes 24 on the extension line of the diagonal of the through hole 21, and the multichannel interface circuit board 2 can be fixedly covered on the positioning printed circuit board 1 and the chip by a plurality of positioning screws passing through the second screw holes 24, so that the beryllium copper probe on the multichannel interface circuit board 2 is ensured to be positioned above the pad corresponding to the chip to be detected. Therefore, when the beryllium copper probe is contacted with the pad corresponding to the chip to be tested, the input and output of the chip to be tested are led out to the multi-path 50 omega routing 25 on the multi-channel interface circuit board 2 through the beryllium copper probe and then are connected to the high-frequency connector 23(SMP/SSMP/G3PO multi-position connector) welded on the periphery of the multi-channel interface circuit board 2. The interface of the high-frequency connector is connected with a transmission cable, so that the interconnection of low temperature and room temperature is realized.
As shown in fig. 4, the pressing device 3 includes a base 31, a suspension 32, a threaded screw 33 and a pressing block 34, a pressing hole is formed in the middle of the base 31, the pressing block 34 is arranged in the pressing hole, and a protrusion is arranged at the bottom of the pressing block 34; the base 31 is provided with the suspension 32, and the middle of the suspension 32 is provided with a threaded hole; one end of the threaded screw rod 33 penetrates through the threaded hole to be connected with the pressing block 34. The height of the pressing block can be freely adjusted up and down through the matching of the threaded screw rod and the threaded hole, so that the protrusions at the bottom of the pressing block can be pressed above the chip to be detected and the metal probe, and the chip to be detected and the metal probe can be stably connected.
In the embodiment, the multi-channel interface circuit board 2 is in a Printed Circuit Board (PCB) form with a metal probe, the positioning of the chip is realized by adopting the printed circuit board and a positioning screw, the Printed Circuit Board (PCB) is a very mature process in the current circuit processing, and only a certain precision requirement needs to be ensured during processing. The pressing block for applying mechanical pressure and other structural parts of the test module are common machined parts made of epoxy glass fiber reinforced plastic (the pressing block and the connecting part) and copper (the cold platform part), machining is also a mature structural machining process at present, and the machining precision requirement is also in the process range at present, so that the low-temperature test structure of the multi-channel high-frequency chip of the embodiment can be realized without a special process, and the implementation mode is simple.
Claims (4)
1. A low-temperature test structure of a multi-channel high-frequency chip is characterized by comprising a chip positioning printed circuit board, a multi-channel interface circuit board and a pressure device, wherein the chip positioning printed circuit board is used for placing a chip to be tested; the multichannel interface circuit board is provided with a plurality of paths of metal probe structures, and the metal probe structures are used for realizing signal input and output of a chip to be tested and external equipment; the pressure applying device is used for applying pressure to enable the pins pad of the chip to be tested on the chip positioning printed circuit board to be in contact with the multi-path metal probes on the multi-channel interface circuit board so as to realize electric connection.
2. The structure for low-temperature testing of the multi-channel high-frequency chip as claimed in claim 1, wherein a groove with the same size as the chip to be tested is formed in the middle of the chip positioning printed circuit board.
3. The structure for low-temperature testing of the multi-channel high-frequency chip according to claim 1, wherein a through hole having a size consistent with that of the chip to be tested is formed in the middle of the multi-channel interface circuit board, and multiple paths of metal probe structures are formed on four sides of the through hole, one end of each of the multiple paths of metal probe structures extends into a position where the chip to be tested is placed on the chip positioning printed circuit board, and the other end of each of the multiple paths of metal probe structures is connected with the high-frequency connector welded around the multi-channel interface circuit board through the wiring.
4. The structure for low-temperature test of the multi-channel high-frequency chip according to claim 1, wherein the pressure applying device comprises a base, a suspension, a threaded screw rod and a pressing block, a pressure applying hole is formed in the middle of the base, the pressing block is arranged in the pressure applying hole, and a protrusion is arranged at the bottom of the pressing block; the base is provided with the suspension, and the middle of the suspension is provided with a threaded hole; one end of the threaded screw rod penetrates through the threaded hole to be connected with the pressing block.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010402144.5A CN111693738A (en) | 2020-05-13 | 2020-05-13 | Low-temperature test structure of multichannel high-frequency chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010402144.5A CN111693738A (en) | 2020-05-13 | 2020-05-13 | Low-temperature test structure of multichannel high-frequency chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111693738A true CN111693738A (en) | 2020-09-22 |
Family
ID=72477645
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010402144.5A Pending CN111693738A (en) | 2020-05-13 | 2020-05-13 | Low-temperature test structure of multichannel high-frequency chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111693738A (en) |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW382769B (en) * | 1998-04-08 | 2000-02-21 | Samsung Electronics Co Ltd | Apparatus for manufacturing known good dies |
| CN1271178A (en) * | 1999-04-16 | 2000-10-25 | 富士通株式会社 | Probe card for testing semiconductor device and method for testing semiconductor device |
| CN1407612A (en) * | 2001-09-03 | 2003-04-02 | 木本军生 | Detector device |
| US20040169521A1 (en) * | 2001-08-02 | 2004-09-02 | Rincon Reynaldo M. | High density probe card apparatus and method of manufacture |
| TWI345064B (en) * | 2007-09-06 | 2011-07-11 | Jung Tang Huang | Cmos process compatible mems probe card |
| US20120306523A1 (en) * | 2011-06-02 | 2012-12-06 | Duk Kyu Kwon | Probe card |
| CN202758021U (en) * | 2012-08-16 | 2013-02-27 | 国网电力科学研究院 | Electrical performance testing device and system |
| US20130120015A1 (en) * | 2011-11-16 | 2013-05-16 | Kiyoto Nakamura | Test carrier |
| CN103140921A (en) * | 2010-09-07 | 2013-06-05 | 韩国机械研究院 | Probe card and method for manufacturing same |
| CN204359829U (en) * | 2015-01-29 | 2015-05-27 | 中国电子科技集团公司第十三研究所 | A kind of test fixture |
| CN104764909A (en) * | 2015-04-09 | 2015-07-08 | 中国计量科学研究院 | Convenient and fast chip testing base capable of being used for extremely-low temperature measuring |
| CN109031102A (en) * | 2018-09-20 | 2018-12-18 | 北方电子研究院安徽有限公司 | A kind of apparatus for testing chip |
| CN109884505A (en) * | 2019-03-14 | 2019-06-14 | 中国科学院半导体研究所 | A kind of configurable structure for photoelectronic chip detection |
-
2020
- 2020-05-13 CN CN202010402144.5A patent/CN111693738A/en active Pending
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW382769B (en) * | 1998-04-08 | 2000-02-21 | Samsung Electronics Co Ltd | Apparatus for manufacturing known good dies |
| CN1271178A (en) * | 1999-04-16 | 2000-10-25 | 富士通株式会社 | Probe card for testing semiconductor device and method for testing semiconductor device |
| US20040169521A1 (en) * | 2001-08-02 | 2004-09-02 | Rincon Reynaldo M. | High density probe card apparatus and method of manufacture |
| CN1407612A (en) * | 2001-09-03 | 2003-04-02 | 木本军生 | Detector device |
| TWI345064B (en) * | 2007-09-06 | 2011-07-11 | Jung Tang Huang | Cmos process compatible mems probe card |
| CN103140921A (en) * | 2010-09-07 | 2013-06-05 | 韩国机械研究院 | Probe card and method for manufacturing same |
| US20120306523A1 (en) * | 2011-06-02 | 2012-12-06 | Duk Kyu Kwon | Probe card |
| US20130120015A1 (en) * | 2011-11-16 | 2013-05-16 | Kiyoto Nakamura | Test carrier |
| CN202758021U (en) * | 2012-08-16 | 2013-02-27 | 国网电力科学研究院 | Electrical performance testing device and system |
| CN204359829U (en) * | 2015-01-29 | 2015-05-27 | 中国电子科技集团公司第十三研究所 | A kind of test fixture |
| CN104764909A (en) * | 2015-04-09 | 2015-07-08 | 中国计量科学研究院 | Convenient and fast chip testing base capable of being used for extremely-low temperature measuring |
| CN109031102A (en) * | 2018-09-20 | 2018-12-18 | 北方电子研究院安徽有限公司 | A kind of apparatus for testing chip |
| CN109884505A (en) * | 2019-03-14 | 2019-06-14 | 中国科学院半导体研究所 | A kind of configurable structure for photoelectronic chip detection |
Non-Patent Citations (1)
| Title |
|---|
| 汪飞 等: "MEMS悬臂梁式芯片测试探卡", 《传感技术学报》 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8212580B2 (en) | Scalable wideband probes, fixtures, and sockets for high speed IC testing and interconnects | |
| US6194908B1 (en) | Test fixture for testing backplanes or populated circuit boards | |
| US6252415B1 (en) | Pin block structure for mounting contact pins | |
| US20060006892A1 (en) | Flexible test head internal interface | |
| JP2014508944A (en) | Equipment for automatic testing / verification of electronic components | |
| TWI758677B (en) | Interposer, base, base assembly and circuit board assembly | |
| US6636057B1 (en) | Electric part testing apparatus with movable adapter | |
| JP4837866B2 (en) | Temperature compensated vertical pin probe probe | |
| CN111721979B (en) | Probe card testing device and signal switching module thereof | |
| US20080100323A1 (en) | Low cost, high pin count, wafer sort automated test equipment (ate) device under test (dut) interface for testing electronic devices in high parallelism | |
| TWI398640B (en) | Contact assembly and its LSI wafer inspection device | |
| CN102043117B (en) | Test apparatus for electronic device package and method for testing electronic device package | |
| US4488111A (en) | Coupling devices for operations such as testing | |
| US6255832B1 (en) | Flexible wafer level probe | |
| CN1316650A (en) | Device for testing chip with the help of printed circuit board | |
| CN111693738A (en) | Low-temperature test structure of multichannel high-frequency chip | |
| CN107728041B (en) | Electronic circuit board electric property detection device | |
| CN101324636A (en) | Guide connection module for detecting circuit board | |
| US6498299B2 (en) | Connection structure of coaxial cable to electric circuit substrate | |
| US8476919B2 (en) | Prober unit | |
| CN220855089U (en) | Jig tool | |
| US11899058B2 (en) | Automated test equipment for testing one or more devices-under-test and method for operating an automated test equipment | |
| KR20110097529A (en) | Prober unit | |
| KR102501995B1 (en) | Automated test equipment for testing one or more DUTs and methods of operating the automated test equipment | |
| US8854072B2 (en) | High temperature-low leakage probe apparatus and method of manufacturing same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |