TW200905633A - Driving integrated circuit for display device - Google Patents

Driving integrated circuit for display device Download PDF

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Publication number
TW200905633A
TW200905633A TW097115641A TW97115641A TW200905633A TW 200905633 A TW200905633 A TW 200905633A TW 097115641 A TW097115641 A TW 097115641A TW 97115641 A TW97115641 A TW 97115641A TW 200905633 A TW200905633 A TW 200905633A
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TW
Taiwan
Prior art keywords
storage unit
bias
driving
unit
integrated circuit
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TW097115641A
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Chinese (zh)
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TWI408637B (en
Inventor
Hak-Yun Kim
Sang-Jo Seo
Jeong-Bae Bang
Bong-Jo Shin
Ho-Yong Choi
Keun-Hyung Park
Yong-Cheol Jeong
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Nat Univ Chungbuk Ind Acad
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/005—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

Disclosed herein is a driving integrated circuit for a display device which is capable of increasing memory yield. The driving integrated circuit includes a first storage unit for storing image data, a second storage unit for storing reference data for control of levels of various drive signals necessary to an operation of the first storage unit, a power generation unit for setting the levels of the drive signals based on the reference data stored in the second storage unit and supplying the drive signals of the set levels to the first storage unit, and a control unit for controlling an operation of the power generation unit.

Description

200905633 九、發明說明： 【發明所屬之技術領域】 本發明是有關一種運用PSRAM或DRAM以做為圖 形記憶體的驅動積體電路，並且特別是有關一種用於顯 示裝置而能夠提高記憶體良率的驅動積體電路。 【先前技術】 在用以驅動顯示裝置之驅動積體電路，通常運用靜 態隨機存取記憶體（SRAM，，，Static Random Access Memory”)做為圖形記憶體，近來已嘗試應用虛擬SRAM (PSRAM,”Pseudo SRAM”）或動態隨機存取記憶體 (DRAM，，’Dynamic Random Access Memory”)做為該圖形 記憶體。 用於傳統PSRAM之增強偏壓的位準是由暫存器内 的數位資料集合所控制。亦即，在傳統上，對於整合在 晶圓内之所有驅動積體電路的參考偏壓位準是根據該 暫存器内的數位資料集合所一次性地選定，並且最終字 組線路偏壓的位準是按照所選定之參考偏壓位準而決 定。 在此’於各驅動積體電路内之pSRAM由共同程式 供應對應於該相同數位資料集合的參考偏壓。此時，該 參考偏壓可隨著處理環境而改變，原因在於其係為類比 電壓。 、 ^ 換言之’所有個別供應至該等驅動積體電路之數位 資料雖具有相同的數值，然根據這些數位資料所個別產 生之參考偏壓卻可能依處理環境而具有不同的數值。因 此’部分的參考偏壓可能會具有顯著地偏離於目標值的 位準，並且部分供應以此等參考偏壓的驅動積體電路可 200905633 能因此而無法運作。 按此方式所製造的驅動積體電路，速同前述程式儲 存於其内之軟體，一併供應給顯示裝置製造商。此時， 在所供應的驅動積體電路中，因為該程式無法運作，不 得不拋除瑕疵性驅動積體電路，其為如前述具有顯著偏 離於目標值之位準的參考偏壓所供應，。 總結而言，傳統上’對於所有在晶圓内形成之 積體電路，提供的PSRAM，該等參考偏壓位= 其耩由共㈤程式所設定，因此無法補償在用於ς PSRAM因處理變異性所致生之驅動電财面的不^ =亚且由於料穩定性*導致該驅動積體電路内的損 【發明内容】 骑+此二本發明係針對於-種用於顯减置之驅動積 二;多個ΪΪ地減輕因相關技藝之限制與缺點所導致 择脾ί發明岔目的在於提供-種用於顯示裝置之驅動 二电路二夠利用額外的非揮發性纪憶體以#定字 :線路偏壓，並且利用外部 之果沒單元的果沒電壓驅二非揮發 = ; = — =該驅以 =電路之良率而不致顯著地增二:動 本發明之額外優點、 部分在熟悉本項技藝之：陳述於後文， 楚，或可自本發明實作所=檢二下兄明後將更清 ^各知精由在所撰說明與其申 200905633 内特定指陳之結構，及各隨附圖式，可實現 之各項目的與其他優點。 如本文所具其他優點’根據本發明之目的， 驅動積體電路包含m::種:於顯示裝置之 資料；第二儲存單 儲存早兀，二用以儲存影像 對於第’ /、用以儲存參考資料，俾以控制 準；電力產Γ單r = 作所必要的各式驅動信號之位 之參考資以根據儲存在第二儲存單元内 右所 <二’4而5又疋该等驅動信號的位準，同時將該尊星 制單準的驅動信號供應至第一儲存單元了及控 用以控制该電力產生單元的操作。 工 第一;存J動^可包含：字組線路偏壓，其用以驅動 以驅動第字組線路；位域路預充電偏壓，其用 壓，其用的位元線路;及電容器上方電極偏 驅動第一儲存單元之電容器的上方電極。 咖產生單元可藉由根據儲存在第二儲存單元 t = 4考貢料以設定一參考偏壓位準來控制該驅動# 號的位準。 别1口 第一儲存單元可為揮發性記憶體。 較佳地，第一儲存單元為動態隨機存取記憶體 (DRAM)或虛擬靜態隨機存取記憶體(PSRAM)。 第二儲存單元可為非揮發性記憶體。 較佳地’第二儲存單元為電子可抹除及可程式化唯 磧 §己憶體（EEPR〇M，，，Electrically Erasable and Programable Read Only Memory”）、單次可程式化 (OTP，，，One-Time Programmable”）EPROM、鐵電 ram200905633 IX. Description of the Invention: [Technical Field] The present invention relates to a driving integrated circuit using PSRAM or DRAM as a graphic memory, and particularly relates to a display device capable of improving memory yield Drive integrated circuit. [Prior Art] In a driving integrated circuit for driving a display device, a static random access memory (SRAM, (Sic, Random Random Access Memory)) is usually used as a graphic memory, and a virtual SRAM (PSRAM, "Pseudo SRAM") or dynamic random access memory (DRAM, 'Dynamic Random Access Memory) is used as the graphics memory. The level of the enhanced bias used for the conventional PSRAM is controlled by the set of digital data in the scratchpad. That is, conventionally, the reference bias level for all of the driver integrated circuits integrated in the wafer is selected once based on the set of digital data in the register, and the final word line is biased. The level is determined by the selected reference bias level. Here, the pSRAM in each of the driving integrated circuits supplies a reference bias corresponding to the same set of digital data by a common program. At this point, the reference bias can vary with the processing environment because it is analog voltage. ^ In other words, although all the digital data supplied to the driver integrated circuits have the same value, the reference bias generated by these digital data may have different values depending on the processing environment. Therefore, the reference voltage of the portion may have a level that deviates significantly from the target value, and the driver integrated circuit that partially supplies the reference bias may be inoperable. The drive integrated circuit manufactured in this manner is supplied to the display device manufacturer together with the software stored therein in the same manner as the above. At this time, in the supplied driving integrated circuit, since the program cannot be operated, the inertial driving integrated circuit has to be thrown off, which is supplied as a reference bias having a level significantly deviating from the target value as described above. . In summary, traditionally, 'for all integrated circuits formed in the wafer, the PSRAM provided, the reference bias bits = are set by the common (5) program, so it cannot be compensated for the processing variation for the PSRAM. Sexually-induced driving electricity money is not ^ = sub- and due to material stability * causes damage in the drive integrated circuit [Summary of the invention] Ride + these two inventions are for the purpose of the display Driven by two; multiple depressions due to limitations and shortcomings of related art caused by the selection of spleen 岔 the purpose of the invention is to provide a kind of driving device for the display device two circuits 2 enough to use additional non-volatile memory Word: line bias, and the use of external fruit, no unit, no voltage drive, two non-volatile = = = = = the drive = the yield of the circuit without significantly increasing the second: the additional advantages of the invention, part of Familiar with this skill: stated in the following text, Chu, or can be obtained from the practice of the invention = the second brother of the second brother will be more clear ^ each knows the essence of the structure and the structure of the specific reference in the 200905633, And each of the various items and other advantages that can be achieved with the drawings . According to another aspect of the present invention, in accordance with the purpose of the present invention, the driving integrated circuit includes m:: kind: data on the display device; the second storage sheet is stored early, and the second is used to store the image for the '/, for storing References, 俾 控制 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; 电力 电力 电力 电力 电力 电力 电力 电力 电力 电力 电力 电力 电力 电力 电力 电力 电力 电力 电力The level of the signal is simultaneously supplied to the first storage unit and controlled to control the operation of the power generating unit. The first work; the memory J can include: a word line bias, which is used to drive to drive the first word line; the bit field precharge bias, the voltage used, the bit line used; and the capacitor The electrode bias drives the upper electrode of the capacitor of the first storage unit. The coffee generating unit can control the level of the driving ## by setting a reference bias level according to the stored in the second storage unit t=4. Another port The first storage unit can be a volatile memory. Preferably, the first storage unit is a dynamic random access memory (DRAM) or a virtual static random access memory (PSRAM). The second storage unit can be a non-volatile memory. Preferably, 'the second storage unit is EEPR 〇M, (Electrically Erasable and Programable Read Only Memory)), single-programmable (OTP,,, One-Time Programmable") EPROM, ferroelectric ram

(FRAM，’’Ferroelectric RAM”）、磁性 RAM 200905633 (MRAM，Magnetic RAM”)及快閃 該電力產生單元可包 灸體之任一者。 根據來自第二儲存單元的參考’資二器’其用以 ::產ii輪出具該所設定位準的參考考偏墨 =力產生為，其用以自該參考 ^偏堡，及Ram 麗、根據該所收參考偏壓之 讀收該參考偏 位準該設定位準C信號的 產生單元可進一步包含：掛Η各士 其用以將時脈信號提供至該Ram :時脈產生器， 該RAM電力產生器能夠放大並出^生器，藉以讓 —者；R A Μ電力產生控制器，复用出;J 4驅動信號的任 之運作，根據來自提供於該控；單制該偏壓產生器 式控制暫存ϋ的控龍來控制 體操作模 電力產生器及該增強時脈產生器的置產生器、她 路，其用以決定送至該等第一及 丄及開機重置電 壓是否為穩定，俾決定是否應操作m元之驅動電 錯存單元、參考偏置產生器及存注單元、第二 第二儲存單元可透過對於該顯示器。 電路的複數個外料端而分舰供應驅動積體 偏置電壓（well bias voltage)、位元、;路;;二考資料、井 組線路偏壓（word line bias voltage): 電偏壓及字 該驅動積體電路可進一步包含：荛、％ „ 一 / _)，其用以在該㈣單元的控制/^^7= voltage)，·穩定化電路’其用以穩定化來自該系 的泵汲電Μ，俾透過第-至第五切換器而分別地 i 動第二儲存單元及將該所產生偏麼供應至 弟-儲存早摘必要的及參考電壓位準控制解碼 200905633 器’其中該控制單元可包含： 该穩定化電路及第—至第三 ，态，其用以捡 於第二儲存單元之抹 入的操=，藉此控制 ⑽二儲存單元的施用時間及寫及入 的計時及4 控制暫存器’其用以產生該參考 1電力產生货準 f準控制解碼器可自該RAM電力二;、中該參考電壓 接收該參考資料、將該所n生轉控制暫存器 該解碼參考資料供應至第^抖加以解瑪，並且將 該等偏壓可包含井偏壓、位子::路 且線路偏壓，其中該驅動積體電^預；電偏壓及字 =部終端’其用以分別地 步^有：複數 疋；及複數個切換器，並各自用弟二餘存單 下建立或打斷該等終y在=制單元的控制 二儲存單元之間的電子連接細。/、中之一之相對應者與第 元之存詩設定第―錯存單 用：動來r第^=更新峨生器，其 信號，並且將所產/夕存二兀欠的更新資料來產生-更新 應瞭解本發明卞」in^料供應至第—儲存單元。 皆僅為示例性及解^ ^^明與後續詳細說明兩者 釋。 ，且係為提供本發明的進—步解 【實施方式】 在各發明各項，實施例’而 地使用相同的參考編犯在王扁各圖式中盡可能 哼、、扁唬，猎以指稱相同或類似的部分。 200905633 在後文中的本發明說明裡，對 能和組態詳細說明在有 、开^v於本案内之已知功 將予省略。 有了_糊本發明的主題項目時 差二县體實施例 施例=方其顯示根據本發明之第-警 产驅動積體電路的組態。 根據本發明之第—|^ 的驅動積體電路可如第而用於5亥顯示裴置 3 〇 1，其用以儲存影像資料^—不包含二第一儲存單元 儲存用於控制對於第—儲弟存早兀302 ’其用以 弟儲存早凡302内之灸去次刹 專驅動信號的位準，並且將 一 > f貝枓來设定該 電力產生二作及控制單元，其用以控制 形記憶體。=佳:存:：!01!儲存外部影像資料之圖 取記憶體(drIm)，或是了丨可為動態隨機存 機存y_(PSRAM『_AM早元的虛擬靜態隨 揮發Hi單元302係可保留儲存於其内的資訊的非 對其供應電力亦然。較佳地，(FRAM, ''Ferroelectric RAM), magnetic RAM 200905633 (MRAM, Magnetic RAM) and flash This power generating unit can be used for any of the moxibustions. According to the reference 'Secondary Unit' from the second storage unit, it is used to:: Produce the reference level of the specified level of the production of the ii wheel = force generated for, from the reference ^, and Ram 丽The generating unit for setting the level C signal according to the received reference bias may further include: providing a clock signal to the Ram: clock generator, The RAM power generator is capable of amplifying and outputting the device, so that the RA Μ power generation controller is multiplexed; the J 4 driving signal is operated according to the control provided from the control unit; a generator-controlled temporary control unit for controlling the body-operated mode power generator and the generator of the enhanced clock generator, the path for determining the first and second turn-on reset voltages Whether it is stable or not, it is determined whether the m-type drive power storage unit, the reference bias generator and the deposit unit, and the second second storage unit should be operable for the display. The plurality of external ends of the circuit and the sub-ship supply supply the drive bias voltage, the bit, the path; the second test data, the word line bias voltage: the electrical bias and The driving integrated circuit may further include: 荛, % „一/ _) for controlling (^) the unit in the (4) unit, and the stabilizing circuit is used to stabilize the system from the system. Pumping the power, transmitting the second storage unit through the first to fifth switches, respectively, and supplying the generated partial to the younger-storage early reference and the reference voltage level control decoding 200905633 The control unit may include: the stabilization circuit and the first to third states, which are used to smear the smear of the second storage unit, thereby controlling (10) the application time of the two storage units and writing and entering a timing and 4 control register for generating the reference 1 power generation source quasi control decoder can be from the RAM power 2; wherein the reference voltage receives the reference data, and the n-transfer control is temporarily stored The decoding reference material is supplied to the second shaker to solve the problem, and the The bias voltage may include a well bias, a bit:: path and a line bias, wherein the driving body is pre-compressed; the electric bias and the word terminal are respectively used to: have a plurality of turns; and a plurality of switches And each of them uses the second memory list to establish or interrupt the electronic connection between the control unit and the storage unit of the unit. The corresponding one of the ones and the poems of the first one are set. The first---------------------------------------------------------------------------------------------------------------------------------------------------------======================================================================= Storage unit. Both are only examples and solutions ^ ^ ^ Ming and subsequent detailed explanations. And to provide the further steps of the present invention. [Embodiment] In the various inventions, the embodiment uses the same reference composer as much as possible in the various figures of Wang Ping. Refers to the same or similar parts. 200905633 In the description of the invention that will be described hereinafter, the known functions of the power supply and the configuration are described in the following, and the known functions in the present case will be omitted. There is a case in which the subject matter of the present invention is poor. The second embodiment of the invention is shown in the form of a first-alert drive integrated circuit according to the present invention. The driving integrated circuit according to the first embodiment of the present invention can be used for the fifth display device 3 〇1 for storing image data ^ - not including the first storage unit for storing for the first Chu Di Cun early 兀 302 'the use of the younger to store the moxibustion in the 302 to the level of the secondary brake drive signal, and a > f bei to set the power generation two and control unit, its use To control the shape of the memory. =Good: Save::!01! Store external image data to retrieve memory (drIm), or 丨 can be stored as dynamic random memory y_(PSRAM『_AM early virtual virtual with volatile Hi unit 302 system It is also preferable to retain the information stored therein without supplying power thereto. Preferably,

體(EEPROMA 2為笔子可抹除及可程式化唯讀記憶 )、早:人可程式化（OTP) EPROM、鐵電RAM 帝）、磁性RAM (MRAM)及快閃記憶體之任—者。 、电力產生單兀1〇1包含：參考偏置產生器215，其 :以，據來自第二儲存單元3〇2的參考資料來設定一參 偏壓的位準，並且輸出該等設定位準之參考偏壓； 200905633 RAM電力產生器213,其用以自夂 收該參考偏壓，根據所收夾考壓 j產生器215接 動，的位準，並且輸出卿設定之該等驅 ，時脈產生器212，其用以將時脈信號信號；增 ::至RAM電力產生器213,以供RAM電=〒LK2 放大亚輪出該等驅動信號的任一者 器213 :川’其用以根據來自提供自控制單⑦；生， 體操作換式控制暫存器W 之。己 生器215，電力產生器 第:U t電路I其用以決定連至第-及 及迎的RAM驅動電壓是否為穩定， 、疋疋否應操作第一儲存單元3〇1、第二二一 ，，^ ^ «ν ^ yj ^ m ° 參考偏置產生器215包含複數個雙極接合電 ，，，D:— 1 τ · ^ 搬彳考偏置產生器犯及RAM電力產生控制器2早二 此’雜體操作模式控制暫存器411係控制第一 ΐ存”操作之暫存器。暫存器411可藉由待命模 :、眠权式及深度待命模式之任一者來操作第—儲存 早兀301，俾減少該驅動積體電路的電力耗用 m ττ，，〇. 1 . —-X〜丨η人’丨―口电晶體 (，ipolar Juncti〇n Transistor”)及複數個金屬氧化物 石夕質場效電晶體（M0SFET，,，Metal 〇xide snic〇nBody (EEPROMA 2 is a pen erasable and programmable read-only memory), early: human programmable (OTP) EPROM, ferroelectric RAM (M), magnetic RAM (MRAM) and flash memory - . The power generation unit 1〇1 includes: a reference bias generator 215 for: setting a reference level of the reference according to the reference material from the second storage unit 3〇2, and outputting the set level Reference voltage bias; 200905633 RAM power generator 213 for self-collecting the reference bias voltage, according to the level of the clamped pressure tester 215, and outputting the drive a pulse generator 212 for adding a clock signal to the RAM power generator 213 for RAM power = 〒LK2 to amplify any one of the driving signals of the sub-driver 213: In accordance with the self-control unit 7; The generator 215, the power generator: U t circuit I is used to determine whether the RAM driving voltage connected to the first and the welcome is stable, and whether the first storage unit 3〇1, the second two should be operated One, ^ ^ «ν ^ yj ^ m ° The reference bias generator 215 includes a plurality of bipolar junction energies,,, D: - 1 τ · ^ 彳 偏置 bias generator commits the RAM power generation controller 2 In the second time, the 'Milk Operation Mode Control Register 411 is a register for controlling the first buffer." The register 411 can be operated by any of the standby mode: the sleep mode and the deep standby mode. First—storage early 301, 俾 reduce the power consumption of the driving integrated circuit by m ττ, 〇. 1 . — —X~丨η人丨, (ipolar Juncti〇n Transistor) and plural Metal oxide stone solar field effect transistor (M0SFET,,,Metal 〇xide snic〇n

Field-Effect Transistor”)的組合。自參考偏置產生器215 所輪^的參考偏壓約為1V。此參考偏壓的位準可根據儲 存在第二儲存單元302内之參考資料的位準而減少或增 加。來自參考偏置產生器215的參考偏壓係供應至RAM 電力產生器213。RAM電力產生器213根據該參考電壓 而決定由此輸出的驅動信號是否精確具備目標電壓位 準。 12 200905633 元二複路及複數個位 影像資料。 數個電容器以供儲存 該等驅動信號包含：字組 動第一儲存單元301的字組線路；l PP，其用以驅 VBLP’其用以驅動第—儲存單元、二線路預充電偏壓 一電容器上方電極偏壓Vcp，其用 線路；及 3〇1之電容器的上方電極。 動第一儲存單元 除該等字組線路偏壓VPP、彳 醫及電容器上方電極彡路預充電偏壓 生„„ 213可根據該參考偏壓以 力產 3(H之操作所必要的各式偏屋。對於第—儲存單元 考偏電力產生器213自參考偏置產生器215接收炎 考偏壓，並且利用所收參考偏壓以產生二A combination of Field-Effect Transistor"). The reference bias voltage from the reference bias generator 215 is about 1 V. The level of this reference bias can be based on the level of the reference material stored in the second storage unit 302. The reference bias from the reference bias generator 215 is supplied to the RAM power generator 213. Based on the reference voltage, the RAM power generator 213 determines whether the drive signal thus output accurately has the target voltage level. 12 200905633 Yuan 2 re-routing and plural-bit image data. A plurality of capacitors for storing the driving signals include: a word line of the first storage unit 301 of the word group; l PP, which is used to drive the VBLP' Driving the first storage unit, the two-line pre-charging bias-capacitor upper electrode bias voltage Vcp, the line for use thereof; and the upper electrode of the capacitor of 3〇1. The first storage unit is in addition to the word line bias voltage VPP, 彳The upper electrode of the doctor and the capacitor is pre-charged and biased. 213 can be used according to the reference bias to produce 3 (the various partial housings necessary for the operation of H. For the first-storage unit, the partial power generator 213 The reference bias generator 215 receives the test bias and utilizes the received reference bias to generate two

Si::位元線路預充電偏壓VBLP及;容器:‘ 屯極偏壓VCP的驅動信號。換言之，RAM電力產 213可按一預定比值藉由將該參考偏壓步進向上或^ 來產生該㈣練號。因此，鱗_信號的位準 到該參考偏壓的位準所影響。 曰又 字組線路偏壓VPP高於供應至控制單元1〇〇的 電壓VCC。RAM電力產生器213藉由泵汲該操作電麼 VCC予以增強來產生該字組線路偏壓vpp。時脈信號 CLK1及CLK2對於此泵汲操作為必要。為此，增強時 脈產生器212可將這些時脈脈衝CLK1及CLK2供庫$ Ram電力產生器213。 ，、應至 ^該等驅動信號具有在預定範圍之内的位準以驅動 第一儲存單元3(Π。注意到該等驅動信號之位準根據處 13 200905633 理環境可超出允許的錯誤範圍。傳統上並無方法復原供 應有位準超出允許錯誤範圍之驅動信號的驅動積體^ 路。 然而’在本發明裡，由於玎藉由改變儲存在第二儲 存單元302内之參考資料的位準來更改該參考偏壓^位 準，因此是可以將隨處理環境變化之驅動信號的位 變至其原始目標位準。 要在第二儲存單元302内寫入或抹除夂 須將該參考㈣、井偏壓、該位元線路預充電偏壓VBl"p 及該字組祕偏壓vpp供rn料單元搬p 此，^弟-具體實施例裡，複數個用以供應該 料 及該侧電壓(井偏壓、位元線路預充電偏壓;㈡ 字組線路偏壓僧)之外部終端501至u 體電路的外部形成。 通驅動積 亦^第-外部終端5 〇 i係用以供應 終端，弟一外部終端502係用以也庙& # 可貝抖的 第三外部終端503係用以供應^壓的終端’ VBLP的終端，並且第四外部；：二:預充電偏壓 組線路偏壓VPP的終端。這些' '、以供應該字 至5〇4親糊的局W，糊==動^ 體電路形成。經由第-外部終端5CH供應至 元302的參考資料為解碼資料。 弟一儲存早 暑單元302可如前述為驗〇Μ。要料失 考育料寫人此EEPR0Mm要 ，將该參 實施例裡’此電壓係自該驅 门弟-具體 另-方面，第-儲存罝 电路的外部所供應。 保留儲存在第-儲存單^^ 3G1係揮發性記憶體。為 于早兀301之内的資訊，必須將更新 14 200905633 重新輸儲存單元抓二j以將該資訊 老眘偏曰n中。此更新資料係按前述之參 二儲存單i 3〇2 ^透過第—外部終端谢而儲存在第 同2 ’根據本發明之第一具體實施例，用於顯 置之=動積體電路進—步包括更新信號產生器555，^ ^根據來自第二儲存單元规的更新資料輪出該更新^ 亦即，更新信號產生器555自第二儲存 收該更新資料、根據所收更新資料以產生該=接 並且將所產生之更新錢供應至第― :，Si:: bit line precharge bias voltage VBLP and; container: 'drive signal of the drain bias VCP. In other words, the RAM power product 213 can generate the (4) training number by stepping the reference bias voltage up or down by a predetermined ratio. Therefore, the level of the scale_signal is affected by the level of the reference bias. The block line bias voltage VPP is higher than the voltage VCC supplied to the control unit 1〇〇. The RAM power generator 213 generates the block line bias voltage vpp by pumping the operation power VCC. The clock signals CLK1 and CLK2 are necessary for this pumping operation. To this end, the enhanced clock generator 212 can supply these clock pulses CLK1 and CLK2 to the bank $ram power generator 213. The drive signals have a level within a predetermined range to drive the first storage unit 3 (Π. Note that the level of the drive signals may exceed the allowable error range according to the environment. There is conventionally no way to recover a driver integrated circuit that supplies a drive signal having a level beyond the allowable error range. However, in the present invention, by changing the level of the reference material stored in the second storage unit 302 To change the reference bias level, it is therefore possible to change the bit of the drive signal that varies with the processing environment to its original target level. To write or erase in the second storage unit 302, the reference (4) is required. , the well bias, the bit line pre-charge bias voltage VBl " p and the word secret bias vpp for the rn material unit to move, in the specific embodiment, a plurality of supplies for the material and the side voltage (well bias, bit line precharge bias; (2) block line bias 僧) external terminal 501 to u body circuit is formed. Pass drive product also ^ first - external terminal 5 〇i is used to supply the terminal , an external terminal 502 is used The temple &# 可贝的的第三的的 external terminal 503 is used to supply the terminal of the terminal 'VBLP', and the fourth external;: two: the pre-charge bias group line biases the terminal of the VPP. These '', The circuit is formed by the supply of the word to the 〇4 亲4 paste, and the reference data supplied to the element 302 via the first external terminal 5CH is decoded data. The first storage morning heat unit 302 can be as described above. For the inspection, it is necessary to write the EEPR0Mm, and the voltage in the reference example is supplied from the outside of the driver-specific storage area. In the first-storage list ^^3G1 is a volatile memory. For the information within 301, the update 14 200905633 must be re-stored to capture the information. According to the foregoing second storage list i 3〇2 ^ through the first external terminal Xie stored in the second 2' according to the first embodiment of the present invention, for display = galvanic circuit step by step The update signal generator 555, ^ ^ is rotated according to the update data from the second storage unit gauge ^ That update, update signal generator 555 receive the update from the second data storage, based on the received information to generate the updated connection = and supplies the generated money through the update -:,

=由該更新信號將前述資訊重新輪入=存J 的驅動積體電路裡，通常是利用 弟-儲存早疋。相對地，在本發明中， =為 該更新資料儲存在第二儲存單元302裡，可在 境下執行該__電_暫存器設定 一 =的記憶體類型(非揮發性記憶體或揮二： 弟^一具體實施例 第二圖係一方塊圖，其顯示根 實施例而用於顯示裝置之驅動積體電路的組態具體 —現參照第二圖，除第一圖的組態以外，根據 2二具體實施例用於顯示裝置的^月 步包括果沒單元 ’其用以在控制單二::； 15 200905633 汲電壓；及穩定化電路421，其用以 ，:凡420的泵沒電壓，藉以產生對於驅動=自 早兀302，並且透過第一至第三切換哭 一儲存 將該等偏墨分別地供應至第二儲存單^ 3〇2 /W3以 ”壓(井偏壓、位元線路預充電偏壓和字c 昼）。除記憶贿傾式㈣―4U 、=路偏 ⑽進-步包含：控制暫存器412，二4制單元 電及切換器SW1至SW3的操作，俾“ 一儲存早7L 302之抹除操作及寫入操 十於第 儲存單元3〇2的施用時間；&議SI: 發明暫存&413 ’其用以產生該參考#料。根據本 進一牛：一具體實施例用於顯示裝置之驅動積體ί路 參考電壓位準控制解碼器424,其用= 碼所#電 =生位準控制暫存器413接收該參考資料、解 資料’並且將該解碼參考資料供應至第二: 第：= 421及第二儲存單元3Q2係透過第—至 至SW3所互連。議壓係透過第-雷低,供，至第二儲存單元302，該位元線路預充 302，^^過第二切換器撕供應至第二儲存單元 二偏壓係透過第三—則供應至第 凋即态可利用為穩定化電路42卜泵汲單元42〇 懕。^產》»生對於該顯示裴置之操作所必要的泵汲電 體電路^單兀420及穩定化電路421係供應於該驅動積 多考电壓位準控制解碼器424亦可用以在RAM電 16 200905633 ==:==制下’減少在第-及第 考電壓位準控制解碼器Γ產各生式„4誤卡〉亦 俾決定在第一及第二 ：生的參考電壓， 少其中的錯ί 轉考，並觀較之結果減 。…，據本發明之第二具體實施例的組態中 早兀302係自該驅動積體電路之内的相對：^存 供應之該參考資料、井低颅 ί且成兀件所 組線路偏壓。、位70線路職電偏屋及字 ’=即’該參考資料是自控制單元⑽ 电力產生位準控制暫存器413所供應， 的ram 位元線路預充電偏壓和字路偏"*愿μ、井偏邀、 路421所供應。 子、、且線路偏屋則是由穩定化電 弟一儲存單元302的宜人抒从a』 内之_存器中設定據控制單元1。。 換吕之，自RAM電力產生位準 輪出的參考資料是由參考電昼位準控二:二^ ，，然後再供應給第二儲存單⑽。此時在第= 存單元302操作所必要的電壓供應 = ^前，並不會執行第二館存單元3Q2的寫入=== 參考資料的操作）或抹除操作(抹除該參 亥 控制暫存器4 i 2即為控制第二儲元m)对 抹除操作的物項。當控制暫存器412操 寫入, 並開啟第-至第三切換器SW1至SW3日^ 穩定化電路421的井偏壓、位元線路 17 200905633 線路偏壓供應至第二儲存單元3〇2。 =字=路偏_計時和施用時間電 储存早凡302的寫入操作及抹除操作。 Μ弟- 化二以f:設定之控制值來控制穩定 計時與施用時間。 ”工刺值以凋整施用 裡If之更㈣料係進—步儲存在第二儲存單元302 ，，、係提供於根據本發明之第二具 父=動額電路，並且更新信號 v提供於該驅動積體電路。 ’二進 該更新資料係自RAM電力產生位 413所輸出。此更新資料係按 器 $而儲存在第二儲存單元内。 ^讀相问的方 實施例 第二圖係方塊圖，其顯示根據本發明之 施例用於顯示裝置之驅動積體電路的組態。，、體實 根據本發明之第三具體實施例用 二積體電路包含該等第一具體實施：=驅 例兩者的功能，如第三圖所示。 弟—具體實施 叙#!據本發明之第三具體實施例用於顯示妒晋“ -電路可藉由透過控制暫存器41:拖’區 至SW3之開啟咖，以令儲存^^器 内之參考資料不動作，並且藉由根據讓該^早者 =0定2 18 200905633 =11力「產生位準控制暫存器413之傳統程式，來替 该參考偏壓及字組線路偏壓的位準。 來凋整 在第三圖裡，編碼之參考資料 端501。該編碼參考資料由參考電壓位l t 加以解碼，^後供應至第二儲存單元3G2。糾碼裔424 在第一至第十切換器SW1至SW10中 切換器SW1至SW3與前述第—至第二 弟二 剛—者相同，而在此省略其:均料^至 制产器_係回應於來自控制暫存器412之控 自第一外雜端5G1 將錄考資料 -。第“器 :T;:r關閉’並且在當為開啟== 二弟六切換器，係回應於來自控制暫存器Tl2: :,β號而開啟/關閉，並且在當為開啟時，將誃 =充電偏壓自第三外部終端5〇3供應至參考 =解碼器424。第七切換器SW7係回應於來 勒 :ϋ控制信號而開啟/關閉，並且在當為開i i， 位轉路偏壓自第四外部終端5G4供應至灸考電壓 位準控制解碼器424。 。王 > 亏窀壓 制4= 器酬回應於來自控制暫存㈣之控 自τ^λΙγ植關’亚且在當為開啟時，將該來考資料 =電力產生位準控制暫存器413供應至來 器424。第九切換器輯回應於來= 時，將L解而自^關閉’並且在當為開啟 解碼參考讀自參考電壓位準控制解瑪器 19 200905633 424供應至參考偏置產生器215。第十切換器swi〇係回 器412之控制信號而開啟/關閉，並且 生料自第二錯存單™ ^九及第切換是按相反方式而運 = 當第九切換器請9為開啟時第十切換器 器啟而當第九切換器SW9她 第一至第十切換器SW1至swl〇的這此 地由=控制暫存器412的相對應控制信號所控制。 的切i = 切換器讓至，7為開啟並且其餘 資料及來自第：=第會將來自第-外部終端501的參考 供應終端502至5〇4的各種偏壓 至=寺=^?器議及第一至第三切換器讀 Ram電力產生位準控為將來自 心，_至第:儲自 I田弟八切換器SW8及第五？笛 ra心力為而其餘的切換器為關閉時:會 第二至第四外 暫存器413的“ 儲存單元3〇2。 至504的各種偏壓供應至第二 至SW3為^換器SW4及第一至第三切換器swi 外部終^!的為關閉時，會絲自第一 偏壓供應至第二儲存單^^自穩定化電路42i的各種 20 200905633 在將該參考資料儲存在第二 置產生器215所&+*> ^ 了貝村决疋自參考偏 數值。所輸出之參考驗的位準是否滿足-所欲 之2言ί第:匕第四切換器_及第八切換器挪 R施電力產生位準控制暫存器413 = ^出。該參考_，_供應轉考電壓㈣控制解碼器 接著，參考電壓位準控制解碼器424 予以解碼並將該解碼參考資科供應 第九切位準控制解碼器424透過= 以將該解碼參考資料供應至參考偏ΐ 第二由=動第二儲存單元302的偏壓未供應至 儲;ίίΤ二因而並未將該參考觸^ 後，準控制解碼器424收到該參考資料 壓，考偏置產生$215根據該參考資料輸出該參考偏 則’若鱗考偏壓的位準是在允許的範圍之内， 換:sCl五5至切換器SW5至請7或第-至第三切 3〇Γ n W3’猎以將該偏壓供應至第二儲存單元 地。因此，該參考資料儲存在第二儲存單元4存内早广 為門启t Γ?ΐ閉第九切換器SW9並且第十切換器swl〇 马開啟’因此將儲存在第-在 料供應至參考偏置產存早兀3°2之内的參考資 200905633 情況下，可藉由更^ l虔之位準超出該允許範圍的 的數值以改θ變爽白炎去^力產生位準控制暫存器413 資料的位H ,，考位準控制解碼器424之參考 為止。=參考顧的位準進入該允許範圍ί 圍内的4丄參考偏屋之位準在該允許範 —二考貝科儲存在第二儲存單元3〇2裡。 僅第32參考資料儲存在第二儲存單Μ⑽裡，則 可將來自：盗：匕開啟而其他的切換器為關閉，因此 置產生早 的參考資料供應至該參考偏 電路產出並上市時，僅第十切換器 搬，其mir係經進—步儲存在第二儲存單元 之，體電路所提:之示裝置 一步提供於該驅動積體電路中。…u 5係進 遠更新資料係透過第一外 應，或是自ram電力產生位準控帝由外部供 此更新資料係按前、+、々会I次制暫存益413所供應。 第二儲存單元、内34 #考 > 料相同的方式而儲存在 μ根據本發明之第一至第三星 =¾置示二r«述 例如’ S亥液晶孽示梦置句人 和複數個資料線路心複，個問極線路GL 個像素單元，其^ 彼此交錯；及複數 交會處所定義線路GL與資料線路DL 義的像素區域之内按個別方式所構成 22 200905633 該等像素單元各自 回應於來自該等閘桎線^ .溥胰電晶體TFT，其用以 脈衝，藉以切換來自誃 ^ ^中之一相對應者之掃描 應者的灰階電壓；像素貝；、、"路DL其中之一之相對 晶體TFT的灰階，極其用以接收來自該薄膜電 像；共用電極，其經排所收灰階電麗以顯示影 壓Vcom供應；# 電極且以共用電 極之間形成。 曰/、於邊像素電極與該共用電 根據本發明之第一 電路可用以驅動該等資料線二:、體實施例的驅動積體 根據第—至第三具體實施例，在第 儲存該更新資料可讓 在第二儲存單元302= The above information is re-introduced by the update signal to the drive integrated circuit of the memory J, usually using the younger-storage. In contrast, in the present invention, = the updated data is stored in the second storage unit 302, and the memory type (non-volatile memory or wave) of the ___________ II: The second embodiment is a block diagram showing the configuration of the driving integrated circuit of the display device for the root embodiment - now referring to the second figure, except for the configuration of the first figure According to the second embodiment of the present invention, the step for the display device includes a unit that is used to control the voltage of the control unit 2::; 15 200905633; and a stabilization circuit 421 for: the pump of 420 No voltage, thereby generating a drive for the drive = self-earthing 302, and crying through the first to third switching, respectively storing the partial inks to the second storage sheet ^3〇2 /W3 to "pressure" , bit line pre-charging bias and word c 昼). In addition to memory bribe (4) - 4U, = road bias (10) further steps include: control register 412, two 4-unit unit power and switchers SW1 to SW3 Operation, 俾 "A storage of 7L 302 erase operation and write operation of the first storage unit 3〇2 & SI: Inventive Temporary & 413 'which is used to generate the reference # material. According to the present invention: a specific embodiment for the display device driving unit ί way reference voltage level control decoder 424 And the source code control unit 413 receives the reference data, the solution data 'and supplies the decoded reference material to the second: the:= 421 and the second storage unit 3Q2 are transmitted through the first As far as SW3 is interconnected, the voltage is passed through the first thunder, and is supplied to the second storage unit 302. The bit line is precharged 302, and the second switch is supplied to the second storage unit. Through the third - the supply to the first state can be utilized as the stabilization circuit 42 pump unit 42. The production of the pump is required for the operation of the display device. The 420 and the stabilization circuit 421 are supplied to the drive product multi-test voltage level control decoder 424 and can also be used to reduce the first- and first-test voltage level control decoders under the RAM 16 200905633 ==:== system. Γ 各 各 „ 4 4 4 4 „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ ί, and the result is reduced.... According to the configuration of the second embodiment of the present invention, the reference 302 is from the relative of the driving integrated circuit: The low-cranial ί and the line bias of the group are formed. The position of the line 70 electric service partial housing and the word '= ie' is the self-control unit (10) power generation level control register 413, the ram position The pre-charging bias and the word bias of the meta-line are required to be supplied by the well, and the circuit is supplied by the road 421. The sub-house, and the line-biased house is stabilized by a stable unit of the storage unit 302. The control unit 1 is set in the register. . For the change of Lv, the reference data from the RAM power generation level is controlled by the reference electric power station two: two ^, and then supplied to the second storage list (10). At this time, before the voltage supply necessary for the operation of the storage unit 302 = ^, the writing of the second library unit 3Q2 is not performed === operation of the reference material) or the erase operation (erasing the control) The register 4 i 2 is an item for controlling the second storage unit m) for the erasing operation. When the control register 412 is written, and the first to third switches SW1 to SW3 are turned on, the well bias of the stabilization circuit 421, the bit line 17 200905633, the line bias is supplied to the second storage unit 3〇2 . = word = road bias _ timing and application time power Save the 302 write operation and erase operation. Μ弟-Chemical 2 controls the stable timing and application time with f: set control value. The spur value is stored in the second storage unit 302, and is provided in the second storage unit 302 according to the present invention, and the update signal v is provided in The driver integrated circuit. The binary update data is output from the RAM power generation bit 413. The update data is stored in the second storage unit by the device $. A block diagram showing a configuration of a driving integrated circuit for a display device according to an embodiment of the present invention. The first embodiment is embodied by a two-integrated circuit according to a third embodiment of the present invention: The function of both of the driving examples is as shown in the third figure. The third embodiment of the present invention is used to display the "" circuit can be controlled by the temporary register 41: dragging 'The opening of the area to the SW3, so that the reference data in the storage device does not operate, and the tradition of generating the level control register 413 is made by letting the early zero = 2 18 200905633 = 11 force Program to replace the reference bias and block line bias levels. In the third figure, the encoded reference end 501. The encoded reference data is decoded by the reference voltage bit lt, and then supplied to the second storage unit 3G2. The corrective code 424 is in the first to tenth switchers SW1 to SW10. The middle switches SW1 to SW3 are the same as the aforementioned first to second second, and are omitted here: the same is to the controller _ in response to the control from the control register 412 from the first foreign End 5G1 will record the data -. "Device: T;: r off" and when it is turned on == two brothers six switches, in response to the control register Tl2::, beta number on/off, And when it is turned on, the 誃=charge bias is supplied from the third external terminal 5〇3 to the reference=decoder 424. The seventh switch SW7 is turned on/off in response to the control signal: and when it is ON, the bit transition bias is supplied from the fourth external terminal 5G4 to the moxibustion voltage level control decoder 424. . Wang> The deficit is suppressed 4= The reward is in response to the control from the control temporary storage (4) from the τ^λΙγ 关 ' ' and when it is turned on, the reference data = power generation level control register 413 is supplied The originator 424. When the ninth switcher responds to YES, L is de-asserted from 'OFF' and is supplied to the reference bias generator 215 when it is turned on for the decoding reference read from the reference voltage level control numerator 19 200905633 424. The tenth switch swi〇 is returned to the control signal of the switch 412, and the raw material is switched from the second wrong deposit ticket TM ^ 9 and the second switch is performed in the opposite manner. The ten switcher is turned on and the ninth switch SW9 is controlled by the corresponding control signals of the control register 412 from the first to tenth switches SW1 to swl. Cut i = switch let, 7 is on and the rest of the data and from the :: will be the various biases from the reference supply terminals 502 to 5 〇 4 of the first external terminal 501 to = 寺 = ^? And the first to third switcher reads the Ram power generation level control for the heartbeat, _ to the first: from the I Tiandi eight switcher SW8 and the fifth? When the other switches are turned off: the storage units 3〇2 of the second to fourth outer registers 413 are supplied. The various bias voltages to 504 are supplied to the second to SW3 as the converter SW4 and When the first to third switches swi are externally turned off, the wires are supplied from the first bias voltage to the second storage unit ^i self-stabilizing circuit 42i. 20 200905633, the reference material is stored in the second The generator 215 &+*> ^ has a self-reference partial value. The level of the reference test output is satisfied - the desired 2 words ί: 匕 the fourth switch _ and the eighth The switcher R power generation level control register 413 = ^. The reference_,_ supply transfer voltage (four) control decoder, then the reference voltage level control decoder 424 decodes and decodes the reference information Supplying the ninth tangential level control decoder 424 through = to supply the decoded reference material to the reference yaw; the second by = the second storage unit 302 is not supplied to the storage; ίίΤ2 thus does not After ^, the quasi-control decoder 424 receives the reference data pressure, and the test offset generates $215 according to the reference. Material output the reference bias is 'if the scale of the scale is within the allowable range, change: sCl five 5 to switch SW5 to please 7 or the first to the third cut 3〇Γ n W3' hunting The bias voltage is supplied to the second storage unit. Therefore, the reference material is stored in the second storage unit 4, and the ninth switch SW9 is turned off and the tenth switch swl is turned on. 'Therefore, in the case of reference 200905633, which is stored within the first-to-be-stock supply to the reference offset, 3°2, the value can be changed by θ to the value of the allowable range. The white blood is turned to force the bit H of the level control register 413 data, and the reference level controls the reference of the decoder 424. = Refer to the level of the reference to enter the allowable range ί The position of the house is stored in the second storage unit 3〇2. The only 32th reference material is stored in the second storage unit (10), which can be from: thief: 匕 open and other The switch is off, so when the early reference data is supplied to the reference bias circuit and is listed, only the tenth The converter is moved, and the mir is stored in the second storage unit in advance, and the body circuit provides: the display device is provided in the driving integrated circuit in one step. ... u 5 is far from updating the data through the first Should, or from the ram power generation level control, the external supply of this update data is provided by the front, +, 々 I system temporary storage benefit 413. The second storage unit, the inner 34 #考> The mode is stored in μ according to the first to third stars of the present invention = 3⁄4 shows two r «represented, for example, 'S Hai liquid crystal 孽 梦 置 置 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 和 , , , , , , And ^ are interlaced with each other; and the pixel area defined by the plurality of intersections and the pixel area of the data line DL are formed in an individual manner. 22 200905633 The pixel units respectively respond to the TFTs from the gate lines , which is used for pulsing, thereby switching the gray scale voltage of the scanning person from one of the corresponding ones of the ;^^; pixel, quot; Receiving from the thin film electrical image; common electrode, its arrangement Li received gray-scale voltage Vcom supplied to the display image; # electrode and common electrode is formed in between.曰/, the edge pixel electrode and the common circuit according to the present invention may be used to drive the data lines 2: the driving body of the body embodiment according to the first to third embodiments, the update is stored Data can be made in the second storage unit 302

夠運用SRAM，藉以相】4的驅動程式能 的液晶顯示裝置裡。 心 用DRAM或PSRAM 地^'自則文明白’根據本發明，藉由利 己憶體而穩定化字組線路偏壓可提J用額外非揮發 的良率。 捉W驅動積體電路 首先》亥非揮發性記憶體係利用 J驅動積體電路内之泵汲 ：動電壓或自 以=以=路因_非4=:SRAM can be used in the liquid crystal display device with the driver of the phase 4. The use of DRAM or PSRAM is understood from the following description. According to the present invention, stabilizing the word line bias by resolving the body can provide additional non-volatile yield. Capture W drive integrated circuit Firstly, the non-volatile memory system uses J to drive the pump in the integrated circuit: dynamic voltage or self = = = wayin _ non 4 =:

其-人’在傳統的驅動積體電路裡 ，第-儲存單元。相對地， =利用SRAM 2儲存在第二錯存單元裡可供在相同二:將:亥更新 3積體電路的暫存ϋ設定，•該上執行該 憶體揮發&^兀的記 辦項技藝之人士將可瞭解可在本IS中進行 23 200905633 各式修改及變化，而不致悖離本發明之精神或範疇。如 此，所欲者係為本發明涵蓋本發明之各項修改及變化， 若該等歸屬於隨附之申請專利範圍及其等同項目的範 傳内。 24 200905633 - 【圖式簡單說明】 各附圖係包括以供進一步暸解本發明，並併入而組 成本申請案之一部分，該等說明本發明之（各）具體實施 例，且連同於該詳細說明以解釋本發明原理。在各圖式 中： 第一圖係一方塊圖，其顯示一根據本發明之一第一 具體實施例而用於一顯示裝置之驅動積體電路的組態； '第二圖係一方塊圖，其顯示一根據本發明之一第二 具體實施例而用於一顯示裝置之驅動積體電路的組 態；及 第三圖係一方塊圖，其顯示一根據本發明之一第三 具體實施例而用於一顯示裝置之驅動積體電路的組態。 【主要元件符號說明】 100 控制單元 101 電力產生單元 211 RAM電力產生控制器 212 增強時脈產生器 213 RAM電力產生器 214 開機重置電路 215 參考偏置產生器 301 第一儲存單元 302 第二儲存單元 411 記憶體操作模式控制暫存器 412 控制暫存器 413 RAM電力產生位準控制暫存器 420 泵没單元 25 200905633 421 424 501 502 503 504 555 SW1 SW2 SW3 穩定化電路 參考電壓位準控制解碼器 外部終端 外部終端 外部終端 外部終端 更新信號產生器 切換器 切換器 切換器 26Its - person's in the traditional drive integrated circuit, the first - storage unit. In contrast, the SRAM 2 is stored in the second memory unit for the same two: the setting of the temporary memory of the integrated circuit, and the recording of the memory of the memory is performed. Those skilled in the art will appreciate that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention covers the modifications and variations of the invention, and 24 200905633 - BRIEF DESCRIPTION OF THE DRAWINGS [0009] The accompanying drawings are included to provide a further understanding of the invention The description explains the principles of the invention. In the drawings: the first figure is a block diagram showing a configuration of a driving integrated circuit for a display device according to a first embodiment of the present invention; 'the second figure is a block diagram , which shows a configuration of a driving integrated circuit for a display device according to a second embodiment of the present invention; and a third block diagram showing a third embodiment of the present invention For example, the configuration of the driving integrated circuit of a display device is used. [Main component symbol description] 100 Control unit 101 Power generation unit 211 RAM power generation controller 212 Enhanced clock generator 213 RAM power generator 214 Power-on reset circuit 215 Reference bias generator 301 First storage unit 302 Second storage Unit 411 Memory Operation Mode Control Register 412 Control Register 413 RAM Power Generation Level Control Register 420 Pump Unit 25 200905633 421 424 501 502 503 504 555 SW1 SW2 SW3 Stabilization Circuit Reference Voltage Level Control Decoding External terminal external terminal external terminal external terminal update signal generator switcher switcher 26

Claims (1)

200905633 申請專利範固： l.—種】於顯示裝置之驅動積 元，其用以儲存影像 於筮 =存單70，其用以儲存參考資料 ，-儲存單元之操 貝=俾控制對 準； I的各式驅動信號之位 2. 内之Si以該===存在第二儲存單元 具”定位準號供二時將該等 控制單元’其用以控制 =早兀;及 動信號包含：項之轉積體魏，其中該等驅 線路Γ且線路偏屋，其用以驅動第一儲存單元的字組 位凡線路預充電偏壓，其 的位元線路；及 /、用㈣動第-儲存單元 之電偏壓，其用以驅動第-儲存單元 _ =請專利範圍第〗項 產生單元藉由根 ^體電路’其中該電力 料以設定—參 元内之參考資 4. 準。 +又控制该等驅動信號的位 如申請專利範圍第 存單元係—揮發性記忽藤動積體電路’其令第_ 如申請專利範園第4 存單元為-動態隨機存體電路’其中第-， 隨機存取記憶體(P 圮饺體(DRAM)或虛擬靜兔 27 5. 200905633 6. 如申請專利範圍第1項之驅動積體電路，其中第二儲 存單元係一非揮發性記憶體。 7. 如申請專利範圍第6項之驅動積體電路，其中第二儲 存單元為一電子可抹除及可程式化唯讀記憶體 (EEPROM)、單次可程式化(〇Tp) EpR〇M、鐵電RAM (FRAM)、磁性RAM (MRAM)及快閃記憶體之任一 者。 項之驅動積體電路，其中該 如甲請寻利範圍第 產生單元包括： ^考偏置產生H ’其用以根 設定一參考偏壓位準，並且輸出= 位準的參考偏壓；及 又疋 RAM電力產生器， 接收該參考_，參考偏置產生器 等驅動信號的位準據欠參考偏敎位準設定該 號。 輪出具5亥5又疋位準的驅動信 9. 項之驅動積體電路’其中該電力 以ί用以將時脈信號提供至該 大並輸出該等驅動信號的電力產生器能夠放 RAM電力產头伽Α 有， 單元提供之記憶體據來自該控制 控制該參考偏置產生哭彳二式抆制暫存器的控制值來 強時脈產生H的操作T '該RAM電力產生ϋ及該增 開機重置電^，复 單元之驅動電壓是盔用<以決定送至第一及第二儲存 為穩定，俾決定是否操作第一儲 28 200905633 元、第二儲存單元、 電力產生控制器。 号偏置產生器及該RAM 10.如申請專利範圍第 存單元可透過體電路，其中第二儲 數個外部終端而分別地以該之驅動積體電路的複 位元線路預充電 貝料、井偏置電堡、 η·如申請專利範園第l 線路偏迦應。 括： 項之驅動積體電路，進—步包 泵汲單元，苴用 没電壓·， 以在该控制單元的控制下輪出泵 穩定化電路，I用 電虔，俾透過第1第一=化來自泵沒單元的泵汲 動第m 弟—切換态而分別地產生對; Z弟^存早凡及將該所 =對於驅 早几所必要的偏壓，·及 场坚仏應至弟二儲存 多考電覆位準控制解 其令該控制單元包括. 第-ί:?存器’其用以控制該穩定化電路及第 弟二切換器的操作，藉此 匕罨路及弟—至 除操作及寫入摔作& 工子；弟―儲存單元之抹 的施用時間；及的㈣及該偏壓對第二儲存單元 參考^^電力產生位準控制暫存器，其用以產生該 力產位準控制解碼器可自該Ram電 資料加以t = 存f接收該參考資料，將所收參考 存單元。 且將该解碼參考資料供應至第二儲 12.如申請專利範圍第U項之驅動積體電路，其中該等 29 200905633 偏墨包含井偏麼、位“ 壓； 、、泉路預充電偏壓及字組線路偏 其中該驅動積體電路進 禝數個外部終端，苴(匕括. 井偏壓、位元線路:以力別地將該參考資料、 第二儲存單元；及電偏壓及字組線路偏壓供應至 複數個切換3|，女 13. 建:或斷開該等;部二在制下 -儲存單元之間的電子連接。 相對應者與第 ^請專利範圍第i項之驅動積體電路， 存早兀進一步儲存用於設定第— 二弟一儲 間的更新資料；及 碎仔早兀之更新時 進一步包括更新信號產生器，其用 二儲存單元的更新資料以產生—更新信、，“第 產生之更新資料供應至第一儲存單元。〜^且將所 30200905633 Patent application: l.—The driving element of the display device is used to store the image in 筮= deposit slip 70, which is used to store the reference data, and the storage unit is 俾== control alignment; The position of each type of driving signal 2. The inner Si has the second storage unit with the === "positioning number for the second time, the control unit" is used to control = early; and the dynamic signal contains: a turn-over body, wherein the drive lines are twisted and the line is partial, and the bit line for driving the first storage unit is the line pre-charge bias, and the bit line thereof; and/or (4) The electrical bias of the storage unit, which is used to drive the first storage unit _ = the scope of the patent range is generated by the root circuit 'where the power is set by reference - reference within the reference element. The bit that controls the driving signals is, for example, the first unit of the patent application scope--the volatile memory of the stagnation vine accretion circuit, which makes the _th, for example, the fourth storage unit of the patent application garden--dynamic random storage circuit' -, random access memory (P 圮 dumplings (DRAM) or virtual静兔27 5. 200905633 6. The driving integrated circuit of claim 1 wherein the second storage unit is a non-volatile memory. 7. The driving integrated circuit of claim 6 wherein The second storage unit is an electronic erasable and programmable read-only memory (EEPROM), single-programmable (〇Tp) EpR〇M, ferroelectric RAM (FRAM), magnetic RAM (MRAM) and flash Any one of the memory. The driving integrated circuit of the item, wherein the generating unit of the range is: ^ test bias generates H', which is used to set a reference bias level, and output = bit The reference voltage is biased; and the RAM power generator receives the reference _, and the reference signal of the reference offset generator and the like is set to the reference bias level to set the number. The driving circuit of the item 9. The driving integrated circuit of the item 'where the power is used to supply the clock signal to the large power generator that outputs the driving signal, and the power generating device can discharge the RAM power, the unit provides The memory is controlled from the control to control the reference offset The control value of the crying two-type buffer is generated to generate the H operation of the strong clock. The RAM power generation and the increase of the power-on reset power, the driving voltage of the complex unit is used by the helmet < Until the first and second storages are stable, determine whether to operate the first storage 28 200905633 yuan, the second storage unit, the power generation controller. The number offset generator and the RAM 10. The storage unit of the patent scope is permeable. a body circuit, wherein the second plurality of external terminals are respectively used to drive the reset circuit of the integrated circuit to pre-charge the material, the well biased electric bunker, and the η· . Including: the driving integrated circuit of the item, the step-by-step pumping unit, the use of no voltage, to turn the pump stabilization circuit under the control of the control unit, I use the electric 虔, 俾 through the first first = The pump from the pump unit is inciting the mth--switching state and generating the pair separately; Z-different and pre-existing the voltages necessary for driving the first few, and the field is firm and should be The second storage multi-test power level control solution is such that the control unit includes a first-order memory device for controlling the operation of the stabilization circuit and the second-party switcher, thereby using the circuit and the brother- To the operation and writing of the fall &work; the application time of the wiper of the storage unit; and (4) and the bias to the second storage unit reference ^^ power generation level control register, which is used The force production level control decoder can generate the reference data from the Ram electrical data and t = save f, and receive the reference storage unit. And supplying the decoding reference material to the second storage 12. The driving integrated circuit of the Uth article of the patent application scope, wherein the 29 200905633 partial ink includes the well deviation, the position "pressure; , , the spring road pre-charging bias And the word line line is biased by the driving integrated circuit into a plurality of external terminals, such as: well bias, bit line: force the reference material, the second storage unit; and the electrical bias and The word line line bias is supplied to a plurality of switching 3|, female 13. built: or disconnected; the second is in the system - the electronic connection between the storage units. The corresponding party and the second patent range i Driving the integrated circuit, storing the update data for setting the second-second storage room; and updating the signal generator further, using the update data of the two storage units to generate - update letter, "The generated updated data is supplied to the first storage unit. ~^ and will be 30
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