TW200904168A - Driving apparatus - Google Patents

Abstract

Disclosed herein is a driving apparatus for driving a pixel, including a first pMOS type transistor connected to a first potential a first nMOS type transistor connected in series to the first pMOS type transistor and connected to a second potential; and a control section configured to control the first pMOS type transistor and the first nMOS type transistor individually using a first on-signal for controlling the timing of turning on of one of the first pMOS type transistor and the first nMOS type transistor; a signal of a potential at a node between the first pMOS type transistor and the first nMOS type transistor being inputted as a driving signal for driving the pixel to the pixel.

Description

200904168 IX. Description of the Invention: [Technical Field] The present invention relates to a driving device for driving a pixel. The present invention is related to Japanese Patent Application No. JP 2007-206000, filed on Sep. 8, 2007, to Japan, and Japanese Patent Application No. JP-A No. The entire contents of these applications are incorporated herein by reference. [Prior Art] FIG. 1 shows an example of one of the configuration of one of the pixel driving circuit or the V driving circuit of the CMOS (Complementary Metal Oxide Semiconductor) image sensor, and the specific system is shown for convenience of explanation. A portion of the pixel drive circuit or the V drive circuit (where the pixels in an nth column are driven). In addition, although in FIG. J, an AND circuit, an R circuit, and a 电路 circuit are used for simplicity of explanation, an actual circuit is not used by using AND, OR, and NOT circuits by using NAND, NOR, and The NOT circuit is implemented. Referring to FIG. 1, the pixel driving circuit 1A includes a bit address decoder η, a timing adjustment section 12, a driver section 13, and a control section 14, and generates and outputs a transmission gate signal TR ( n), a reset signal RST(n) and a select signal SEL(n) to drive the pixels in the nth column. The address decoder 1 将 selects a pixel in the nth column as a one of the - drive target column selection signals at a predetermined timing to supply (4) to the timing adjustment section 12. The timing adjustment section 12 adjusts the timing of generation of the transmission gate signal TR(n), the reset signal RST(4), and the selection signal SEL(4). Specifically, the 128552.doc 200904168 timing adjustment section 12 includes AND circuits 21 and 22, an OR circuit 23, and a NOT circuit 24, which are used together to adjust the transmission gate signal TR(n). The logic gate circuit that produces the timing. The timing adjustment section 12 further includes an AND circuit 25 and a NOT circuit 26, the circuits being used as a logic gate circuit for adjusting the timing of the generation of the reset signal RST(n). The timing adjustment section 12 further includes an AND circuit 27 and a NOT circuit 28 that cooperate to function as a logic gate circuit for adjusting the timing of the generation of the selection signal SEL(n). The AND circuit 21 performs a logical AND operation on the column selection signal cpV_LINE(n) input from the address decoder 与 and a timing signal input from the control section M, and obtains the result by the logical AND operation. A signal is supplied to the OR circuit 23. The AND circuit 22 pairs the decoder from the address 丨! The input column selection signal (pV-LINE(n) is logically ANDed with another timing signal input from the control section 14 (pSTR and a signal obtained by the logical AND operation is supplied to the OR circuit 23. The OR OR OR circuit 23 performs a logical 〇R operation on the signal supplied from the AND circuit 21 and the signal supplied from the AND circuit 22, and supplies a signal obtained by the logic 〇r operation to the NOT circuit 24. The NOT circuit 24 operates a logical negation operation on the signal supplied by the OR circuit 23, and supplies a signal obtained by the logical negation to the driver section 13. Therefore, the driver section 13 is intended to be used hereinafter. The timing of the generation of the generated transmission gate signal TR(n) is controlled. The AND circuit 2 5 selects the column selection signal cpV_LINE(n) input from the address decoder 与 and inputs from the control section 14 - The timing signal is incremented by 128552.doc 200904168 The row logical AND operation and the signal obtained by the logical AND operation is supplied to the NOT circuit 26. The NOT circuit 26 operates a logical negation operation on the signal supplied from the AND circuit 25. And will use this logic Negatively obtained - the signal is supplied to the driver section 13. Therefore, the timing of the generation of the reset signal RST(n) to be generated by the driver section 13 is controlled. The AND circuit 27 decodes the address from the address. The column selection signal cpV_LINE(n) input to the unit u is logically ANDed with the anus input from one of the timing sections of the control section 14, and a signal obtained by the logical AND operation is supplied to the NOT circuit 28. The NOT circuit 28 negates the operation logic No. 6 supplied from the AND circuit 27, and supplies a signal obtained by the logic negation to the driver section 13. Therefore, it is intended to be generated by the driver section 13. The timing of selecting the generation of the 彳EL(n) is controlled. The driver section 13 generates and outputs the transmission gate signal TR(n) and the reset signal RST(n) according to the signal supplied from the timing adjustment section 12. And a selection signal SEL(n). Specifically, in the driver section 13, a pM〇s transistor 3i is connected in series with an nMOS transistor 32. A potential of ¥1)1:) is used as a High position

A quasi-potential is connected to the source of the pMOS transistor 31, and a potential vsS is connected to the source of the nM〇s transistor 32 as a low level potential. A signal supplied from the Ν〇τ circuit 24 of the timing adjustment section 12 is supplied to the PMOS transistor 31 and the gate of the nMOS transistor 32. If the signal is a low level signal, the PM 电 transistor 31 is placed in an on state, but the § § is a high level signal 'the nMOS transistor 32 is placed in an on state. 128552.doc 200904168 Therefore, if the signal input to the gate is a low level signal, the potential at the point where the PMOS transistor 31 and the drain of the nMOS transistor 32 are connected to each other becomes the potential VDD, but If the signal input to the gate is at position 5, the potential at that point becomes the potential vss. This point referred to below is referred to as a transmission gate junction. Next, a signal of the potential is applied as the transmission gate signal TR(n) to the transmission gate of the pixel in the nth column of one pixel segment formed by a plurality of pixels. In this manner, the driver section 13 generates and outputs the transmission gate signal TR(n) in accordance with the signal supplied from the timing adjustment section 12. In addition, in the driver section 丨3, similar to the pM〇s transistor 3 i and the nMOS transistor 32, a pm〇S transistor 33 and an nM〇s transistor 34 are connected in series, and the like The potentials VDD and vss are connected to the PMOS transistor 33 and the source of the nM〇S transistor 34, respectively. A signal supplied from the NOT circuit 26 of the timing adjustment area #1 1 is supplied to the gate of the pM〇s electric crystal 33 and the nMOS transistor 34. Next, a signal of a potential at a point at which the 1) centistoke 8 transistor 33 and the drain of the nMOS transistor 34 are mutually connected is input as the reset signal RST(n) to the pixel segment. The pixels in the η column. This point referred to below is referred to as a reset joint. Therefore, the potential VDD or the reset signal RST(n) of the potential vss is input to the pixel in the nth column of the pixel section in accordance with the signal supplied from the timing adjustment section 12. Further, in the driver section 丨3, similar to the pM〇s transistor 3 1 and the nMOS transistor 32, a pMOS transistor 35 is connected in series with an nMOS transistor 36, and the equipotential VDD and vss The source is connected to the source of the 128552.doc 200904168 pMOS transistor 35 and the nM0S transistor 36, respectively. A signal supplied from the NOT circuit 28 of the timing adjustment section 12 is supplied to the gates of the pM〇s electric crystal 35 and the nMOS transistor 36. Next, a signal of a potential at a point at which the 13-channel 8 transistor 35 and the drain of the nMOS transistor 36 are mutually connected is input as the selection signal SEL(n) to the nth column of the pixel section. The pixel in the middle. This point referred to below is referred to as a selection joint. Therefore, the potential vdd or the selection signal SEL(n) of the potential vss is input to the pixel in the nth column of the pixel section in accordance with the signal supplied from the timing adjustment section 12. The control section generates a #high level or a low level timing signal cpSEL, cpRST, and a 1/4 scale at a predetermined timing, and supplies the generated signal to the timing adjustment section 12. Next, the timing of the signal associated with the output of the transfer gate signal TR(n) in the pixel drive circuit 1A shown in Fig. 1 will be described with reference to Fig. 2 . If the level of the column selection signal cpV_LINE(n) changes from the low level to the high level at time q and then the timing signal φ8τκ or the timing signal (the level of pRTR changes from the low level to the time h from the low level to At the high level, the level of the signal generated by the AND circuits 21 and 22, the OR circuit 23, and the NOT circuit 24 becomes the low level. Therefore, the transistor 31 is placed in an on state. The 11 Helium 3 transistor 32 is placed in a closed state, and the transmission gate signal TR(4) of the potential VDD is output to the pixel section (as shown in FIG. 2). Then, if the timing signal or the timing is The signal φΐιτιι is changed from the high level to the low level at time t3 (as shown in FIG. 2), and the signals generated by the AND circuit 21 and the 22 'OR circuit 23 and the NOT circuit 24 of the 128552.doc 200904168 are used. The level becomes the high level. Therefore, the pMOS transistor 3 1 is placed in a closed state to place the nMOS transistor 32 in an on state, and the transmission gate signal 711 (11) of the potential vss is output. To the pixel segment (as shown in Figure 2). Thereafter, despite the column selection letter The level of φν_LINE(n) changes from the still level to the low level (as shown in Fig. 2) at the time, but by the AND circuits 21 and 22, the OR circuit 23 and the Ν〇τ circuit 24 The level of the generated signal is maintained at the high level. Therefore, the transmission gate signal TR(n) of the potential vss continues to be rotated to the pixel segment (as shown in Figure 2). It should be noted that although the above description The timing signal is in the scale or the timing signal (pRTR has @direction or the low level, but the content of the description means the following two conditions. In one case, the timing signals 9Str and the medium have the high level or the The lower level; the other case is where the timing signals are 1 and the cpRTR-signal has a high level or the low level and the other signal of the # generally has the low level. In addition, although not shown, In the pixel driving circuit 10 shown in FIG. 1, 'similar to the transmission signal signal TR (4), the potentials of the reset signal RST (8) and the (4) selection signal chaos (4) are also according to the column selection signal cpv LINE (4) and the timing signal _L or the The level of the timing signal changes to the potential VDD or the potential vss. It is mentioned that in the cardiac pixel driving circuit 所示 shown in FIG. 1, it is preferable that the same signal is propagated to the series connection at the timing of the complete phase π 卩 5 ^ ^ ^ 冋 冋 冋 冋 理想pM〇S transistor 3 j, μ th 33 or 35 with nM〇S transistor 32, I28552.doc 200904168 3 4 % gate. But hey, possible system, once the pM〇s transistor 31, 33 Or a transition occurs between the 35 and the on and off states of the nMOS transistor 32, 34 or 36, the operational timings of which may be displaced relative to one another such that the PMOS transistor 31, 33 or 35 and the nM〇s transistor 32 are present. , "or 36 are both placed in an open state. On the same day, as described above, the transmission gate signal TR(n) is determined by one of the pixels and outputs three values (for example, high, medium and low levels). It is known and disclosed in, for example, Japanese Patent Laid-Open Publication No. 2002-77730. In particular, in such a driving circuit of the type described above, the number of logic gates of one stage before the pM〇s transistor of one of the driver sections is before the nM〇s transistor of one of the driving sections The number of logic gates at one level is often different from each other. Therefore, there is a high possibility that a certain skew deviation may occur. In addition, the driver section 132pM〇s transistor 31, 33 or 35 and the nMOS transistor 32, 34 or 36 of the pixel driving circuit 10 are generally designed by using a transistor having a high capacity so as to be simultaneously turned on and off. A column of pixel gates S. Therefore, it is possible to operate the PMOS transistor 31, 33 or 35 and the nMOS transistor 32, 34 or 36 of the driver section Η

The timing sequences are relatively displaced from each other such that the {3]^(;^ transistor Η, D or 35 and the nMOS electrical body 32, 34 or 36 are both placed in an open state, Then, an excessively high feed-through current may flow from the potential side to the potential VSS. Next, if the feedthrough current flows to the low-level power supply of the potential vss, which causes the low-level fluctuation, it is pressed (for example) The low level of the gate of a pixel in a different column during a period of storage 128552.doc 200904168 may also fluctuate. In particular, it will be charged by incorporating a wafer in which the pixel driving circuit 1 is provided. The negative potential generated by Bangguang is determined as the potential of the low level. In the case of It, the possible system is determined by the capacity of the charging pump. It may be caused by the fluctuation of the negative potential caused by the feedthrough current. More time is required. Therefore, there is a detrimental effect on image quality and the image quality is degraded. [Invention] In this manner, in the above-described pixel driving circuit 10, there is a possibility that the feedthrough current can be derived from The potential VDD flows to the potential VSS to The power supply fluctuation causing the low level of the potential VSS has a detrimental effect on the image quality. Therefore, it is necessary to prevent fluctuations in the low-level power supply in the case where the pixel is driven to prevent degradation of the image quality. According to a specific embodiment of the present invention, a driving device for driving a pixel is provided, comprising: a first pM〇s transistor connected to a first potential; a first nM〇s transistor, Connected to the first pMOS type transistor in series and connected to a second potential; and a control section configured to control the first pMOS type transistor and the first nMOS by using one a first-on signal of the timing of the opening of one of the transistors to individually control the first pMOS type transistor and the first nMOS type transistor; between the first pM〇s type transistor and the first - one of the potentials at one of the nodes between the nMOS type transistors is input to the pixel as a drive signal for driving the pixel. 128552.doc • 14- 200904168 The control section can individually control the ! Nian- PMOS transistor and the first nMOS transistor to control a first Lei-like handle & / Gothic cycle (during the potential at the node is the first potential), a second potential period (during the node The potential at the potential is the second potential) and the length of the high-impedance period (the node is in a high-impedance state) and the start timing. The control section can control the first-potential period, the second potential period, and the high The length of the impedance period and the starting timing are such that from the first and second

The high-impedance period is provided by the period-cycle transition to the other period of the periods. The driving device may further include a second transistor, which is one of the following two transistors: a second pM〇s transistor connected in parallel with the first PMOS transistor and connected to a third And a second nMOS transistor connected in parallel with the first nM〇s transistor and connected to the third potential, wherein the control section uses the first turn-on signal and one to control the first a second turn-on signal of the timing of turning on the two transistors to individually control the first pMOS transistor, the first 11 pad 8 transistor, and the second transistor, in the first pMOS transistor 'first nM〇s A signal of a potential of a node 4 between the crystal and the second transistor is input to the pixel as the driving signal. The control section can individually control the first pM〇s transistor, the first nMOS transistor and the second transistor to control a first potential period (the potential at the node is the first potential), a second potential period (the potential at the node is the second potential), a third potential period (the period at which the potential is the third potential), and a high impedance period (the period is 128552. Doc -15- 200904168 The length and start timing of a high impedance state. The control section can control the lengths of the first, second, third, and third potential periods and the high-impedance period and the start timing to convert from one of the first, second, and third potential periods to a different one This high impedance period is provided by the cycle. In the driving device, the first PMOS transistor and the first nM〇s transistor are individually controlled by using the first turn-on signal, and the first turn-on signal is connected to the first potential by α control. a timing at which the first pM〇s transistor is connected to the first pMOS transistor connected in series to the first p-MOS transistor and connected to the second potential. Further, a signal of a potential at a junction between the first pM〇s transistor and the first nMOS transistor is input to the pixels as a driving signal for driving the pixels. By driving the driving means of the pixels therein, fluctuations in the low-level power supply can be prevented to prevent degradation of the image quality. [Embodiment] Before describing a preferred embodiment of the present invention, a correspondence between certain features described in the accompanying claims and specific features of the preferred embodiments described below will be described. However, the description is only for the purpose of clarifying the specific elements of the invention as described in the claims of the invention. Therefore, even if a particular element described in the description of the specific embodiments is not described as a feature of the features in the following description, this does not mean that the specific element does not correspond to the feature. Conversely, even if a particular element is expressed as an element corresponding to one of the features, this does not mean that the element 128552.doc • 16 - 200904168 does not correspond to any other feature than the element. According to a specific embodiment of the present invention, a device for driving a pixel (for example, the pixel (four) circuit 50 shown in FIG. 3) includes: - a: PMOS transistor (for example, FIG. 3) Illustrated - pM〇s transistor), connected to a first potential (eg, - potential chat); - nMOS transistor (for example, the _n Cong transistor cut shown in Figure 3, Connected in series to the pp-p-type transistor and connected to a second potential (eg, -potential VSS); and a control section (eg, one of the timing adjustment sections 51 shown in FIG. 3), the level set The state is used to individually control a first-on signal (for example, an on signal cpTR_PMOS) for controlling the timing of the opening of the first P-type transistor and the first die-type transistor. Controlling the first pMOS type transistor and the first nM〇s type transistor; one of potentials at a node between the first pMOS type transistor and the first nM〇s type transistor It is input to the pixel as a driving signal for driving the pixel (for example, a transmission gate signal TR(n)). The driving device may further include a second transistor (for example, one of the pMOS transistors 121 shown in FIG. 8), which is one of the following two transistors, a second pMOS transistor, and the first a pM〇s transistor connected in parallel and connected to a third potential; and a second nM〇s transistor connected in parallel with the first nMOS transistor and connected to the third potential, the control section The first pMOS transistor, the first nM〇S transistor, and the second transistor are individually controlled by using the first turn-on signal and a second turn-on signal for controlling a timing of turning on the second transistor. The signal of the potential at the node between the first 128552.doc •17·200904168 pMOS transistor, the _nth transistor and the second transistor is input to the pixel as the driving signal. DETAILED DESCRIPTION OF THE INVENTION A specific embodiment in accordance with the present invention will be described in detail with reference to the accompanying drawings in which: FIG. 3 shows an example of one of the configurations of one of the pixel drive circuits of a cm〇s image sensor according to one of the first embodiments of the present invention. Should be noted, for the sake of convenience, Figure 3 shows A portion of the pixel driving circuit including the driving pixels in the nth column. In addition, although an AND circuit, an R circuit, and a NOT circuit are used for simplification of description in FIG. 3, an actual circuit can be used. It is implemented by using a nand circuit, a NOR circuit and a NOT circuit. The same applies to one of the circuits described below with reference to Fig. 8. Referring to Fig. 3, the pixel drive circuit 5 shown includes a bit address decoder 11 a driver section 13, a timing adjustment section 5A and a control section 52, and generates and outputs a transmission gate signal TR(n) and a reset signal RST(n) - a selection signal SEL(n). It should be noted that the pixel drive circuit 5 includes several common components of the components described above with reference to Figure 1, and overlapping descriptions of such common components are omitted herein to avoid redundancy. The timing adjustment section 51 includes an AND circuit 2 1 , a NOT circuit 60 , an OR circuit 61 and another NOT circuit 66 , which are used together to adjust the generation of the transmission gate signal TR(n). The timing of the logic gate circuit. The timing adjustment section 51 further includes an AND circuit 25, a NOT circuit 26, an OR circuit 62, and another NOT circuit 65. The circuits are used together to adjust the generation of the reset signal RST(n). Timing logic gate 128552.doc •18- 200904168 pole circuit. The timing adjustment section 51 further includes an AND circuit 27, a NOT circuit 28, a 〇R circuit 63 and another not circuit 64. The circuits cooperate to adjust the generation of the selection signal SEL(n). Timing logic gate circuit. In the timing adjustment section 51, the 〇R circuits 61 to 63 and the 4 NOT circuits 64 to 66 are placed in a stage before the driver section 13. In addition, in the timing adjustment section 51, the same signal is not input to the pMOS transistor 31, 33 or 35 & nM〇s transistor 32, 34 or 36 of the driver section 13, but by logic The 0R operation (which uses one of the signals input to the nM〇s transistor 32, 34 or 36) is input to the pMOS transistor 31, 33 or 35. Further, in the timing adjustment section 5A, the AND circuit 22 and the 〇R circuit 23 provided in the pixel drive circuit 丨 shown in FIG. 不 are not provided, and one signal output from the AND circuit 21 is directly input to The Ν〇τ circuit is 6 〇. Therefore, it is not necessary to generate the timing signal by the control section 52 ((>8111. More specifically, the NOT circuit 60 of the 5th timing adjustment section 51 has a signal operation logic supplied from the AND circuit 21). Negative operation and outputting a signal obtained by the logic negation. The signal output from the circuit 6 is input to the nMOS transistor 32 of the driver section 13 and is also input to the 〇R circuit 61. An output signal for outputting a timing for controlling the turn-on of the pMOS transistor 31 from the control section 52 is input to the NOT circuit 66. Then, the circuit 66 is turned on by the cpTR_PMOS. The logic negation operation is operated and a signal obtained by the logic negation is input to the OR circuit 61. 128552.doc 19 200904168 The OR circuit 6 1 pairs the signal output from the NOT circuit 60 and the signal output from the NOT circuit 66. A logical OR operation is performed, and a signal obtained by the logical OR operation is supplied to the pMOS transistor 31. Specifically, by using a signal output from the NOT circuit 66, the OR circuit 61 generates an input to be input to The letter of the pMOS transistor 31 The signal output from the NOT circuit 60 for input to the nMOS transistor 32 is separated. Therefore, the timing adjustment section 51 can individually control the pMOS transistor 31 and the nMOS transistor 32. One of the output signals of the NOT circuit 26 of the timing adjustment section 51 is input to the nMOS transistor 34 of the driver section 13 and is also input to the OR circuit 62. In addition, one of the outputs from the control section 52 is used for An enable signal cpRST_PMOS that controls the timing of turning on the pMOS transistor 33 is input to the NOT circuit 65. The NOT circuit 65 operates a logic negative operation on the turn-on signal cpRST_PMOS and inputs a signal obtained by the logic negation to the OR circuit. 62. The OR circuit 62 performs a logical OR operation on the signal output from the NOT circuit 26 and the signal output from the NOT circuit 65, and supplies a signal obtained by the logical OR operation to the pMOS transistor 33. The timing adjustment section 51 can individually control the pMOS transistor 33 and the nMOS transistor 34.

Further, a signal output from the NOT circuit 28 of the timing adjustment section 51 is input to the nMOS transistor 36 of the driver section 13 and is also input to the OR circuit 63. In addition, an enable signal cpSEL_PMOS output from the control section 52 for turning on the pMOS transistor 35 is input to the NOT 128552.doc -20-200904168 circuit 64. Next, the NOT circuit 64 operates a logic negative operation on the turn-on signal q > SEL_PMOS and inputs a signal obtained by the logic negation to the OR circuit 63. The OR circuit 63 performs a logical 〇R operation on the signal output from the NOT circuit 28 and the signal output from the NOT circuit 64, and supplies a signal obtained by the logic operation to the pMOS transistor 35. Therefore, the timing adjustment section 51 can individually control the pMOS transistor 35 and the nMOS transistor 36. Γ

The control section 52 generates timing signals cpSEL, (pRST and (pRTR) and the turn-on signals cpTR_PMOS, (pRST_PMOS and (pSEL_PMOS) with the high level or the low level at a predetermined timing. The signal is supplied to the timing adjustment section 51. Next, an example of the timing of the signal related to the output of the transmission gate #TR(n) in the pixel driving circuit 5A shown in Fig. 3 will be described with reference to FIG. If the level of the column selection signal cpV_UNE(n) changes from the low level to the high level at time tn and then the level of the timing signal φΙιτκ is at time. From the low level to the high level, by the The circuit 2i and the NOT circuit 60 are generated so that the level of the signal input to the nM〇s transistor 32 becomes the low level. In addition, at this time, if the level of the on signal cpTR_PMOS is the low level (eg, As shown in FIG. 4, the signal generated by the AND circuit Μ, NOT circuit 60 or circuit 61 and Ν〇τ circuit % for input to the PMOS transistor 31 becomes the high level. 3! With the nMOS transistor 32 both placed _ close _, The transmission gate junction is placed in a high impedance (Hi_z) state, as shown in Figure 4. 128552.doc -21 - 200904168 In addition, if the level of the turn-on signal cpTR-PM〇s is from the low level at time ti3 Changing to the high level (as shown in FIG. 4), the level of the signal to be rotated into the PMOS transistor 3! is changed to the low level, and the signal to be input to the touch (10) transistor ^ remains at the low level. Therefore, when the state of the thorn S transistor 32 remains in the off state, the PMOS transistor 31 is placed in an open state and the lightning gate of the rms rm VDD is the same as that of the gate VDD. The pole signal TR(n) is output to the pixel segment. As described above, when the timing signal 9 level changes to a high level at time ^, the nMOS transistor 32 is placed in a closed state, and the potential VSS The output of the low-level transmission gate signal TR(n) ends. However, the time to the level of the turn-on signal ΦTM changes to the high level tu 'the pMOS transistor 31 is not turned on. Therefore, the transmission gate junction is placed in a high impedance state. The level of the turn-on signal cpTR_PM〇s changes from the high level to the low level (as shown in FIG. 4), and the level of the signal to be input to the PMOS transistor 返回 returns to the high level. Reading the person to the capsule (10) The level of the signal of the transistor 32 maintains the low level. Therefore, when the touch (10) transistor 32 remains in the off state, the state of the p-cut transistor 3 i returns to the state. The transfer idle junction is again placed in a high impedance state (as shown in Figure 4). Then, the level of the timing signal ton TM changes to the low level at time t15 (as shown in FIG. 4), and the level of the signal input to the nM 〇S transistor 32 becomes the high level. quasi. In addition, at this time, if the turn-on signal ― PMOS remains low (as shown in FIG. 4 ), the level of the signal to be input to the pM 〇 s 128552.doc -22- 200904168 transistor 3 1 becomes High level. Therefore, when the state of the pM〇s transistor 31 remains in the off state, the transistor 32 is placed in an on state and the low-level gate gate signal TR(n) of the potential vss is output to the Pixel section (as shown in Figure 4). Therefore, although the level of the column selection signal φΥUNE(n) is changed from the high level to the low level (as shown in FIG. 4), if the timing signal cPRRT and the enable signal ^tr_pmos The level of the signal is maintained at the low level and the level of the signal to be individually input to the PMOS transistor 31 and the nM 〇s transistor 32 is maintained at the high level. Therefore, the transmission gate signal TR(n) of the potential vss continues to be rotated to the pixel section (as shown in Fig. 4). As described above, when the level of the transmission gate signal TR(n) is desired to change from the high level to the low level or vice versa from the low level to the high level, the control section 52 turns the enable signal φΤΚ The level of PM〇s is changed such that the transmission gate junction is placed in a high impedance state during the level change described. Therefore, once the change described above occurs, both the pMOS transistor 3 1 and the nMOS transistor 32 are placed in an on state to prevent the feedthrough current from flowing from the potential VDE to the potential vss. Therefore, fluctuations in the low-level power supply are prevented. In addition, in particular, in the case where the negative potential generated by the charging pump inside the wafer (on which the pixel driving circuit 5 is provided) is determined to be the low level potential vss, the charging is eliminated. Puzhi load. Therefore, deterioration of image quality in the pixel section can be prevented. In addition, the control section 52 can change the timing of the timing signal (pRTR or the pulse length of the open signal cpTR_PMOS and its level to such that 128552.doc •23-200904168 can change the following periodic round-closed Wei TR(8) The snow timing and its period or length: during the transmission idle period 2: the potential VDD, during which the potential of the transmission () is the period of the potential VSS w#:::,, the period of the anti-state is long Production and it? Μ 或 or (4) 启 (4) φτκ·ρ_ pulse: the change of the two conversion timing can be in any way (for example, by using one US for the control section to implement. τ 07 supervised state (not shown No)) is:: bit 2, the level of the transmission inter-pole signal TR(n) is changed from the low level (as shown in FIG. 5), and the transmission can be closed during the change described. The junction is placed in a high-impedance state, and the "suppression of the feed-through current _ Dfn" is handled. And, in the transmission gate signal, the (4) high material is changed to the low material (= the control section 52 can place the object: the point into a high-impedance state during the change described) to suppress the feedthrough current. The flow of the gate signal TR(n) changes from the low level to the high level (as shown in Figure 5), and the brother § ^ § changes in the appropriate When the gate junction is to be transmitted during the high-impedance state, the control section 52 is not at time t14 before time t15 and at the time after time ti5, the level of cpTR_PM〇S is said to be from the high level. Change to the low level. Therefore, since the P s electric body 3 i is placed in a closed state while the nMOS transistor 32 is placed in the on state, the bit signal TM(4) is transmitted. In the case where the high level is changed to the low level, the transmission gate junction is not placed in a high impedance state. 128552.doc •24- 200904168 In addition, in the position of the transmission gate signal TR(n) In the case of changing from the high level to the low level of X (as shown in Figure 6), The change period: when the transmission closed-pole joint is to be placed in a high-impedance state, the control region ^52 is not at time t1 after k1, and at time t31 before time tI2, The level of pTR_PM〇s changes from the low level to the high level. Therefore, since the 11's transistor 32 is placed in the same state as the off state, the "Hi-PMOS transistor 3" is placed. An open state, therefore, the transmission gate junction does not enter a high impedance state in the case where the level of the transmission gate TR TR TR(n) changes from the low level to the high level. In addition to preventing the feedthrough current, it is necessary to pay more attention to shortening the high impedance period to shorten the time or clock cycle, in which the level of the transmission gate signal TR(n) is to be changed from the high level to the low level. In a case where the situation is to change the level of the transmission gate signal TR(n) from the low level to the high level (as shown in FIG. 7), the control section 52 can Preventing the transfer gate junction from being placed in a high impedance state during the change described In this example, the control section 52 changes the level of the turn-on signal (the level of pTR_PM0S from the low level to the high level at a time before time t1z, and the turn-on signal at time tzl after time tls. The 尺 尺 - pM 〇 s changed from the level of the word to the low level, as shown in Figure 7. The specific bamboo raft. < 'The control section 52 causes the turn-on signal (pTR-PMOS pulse length to be longer than the pulse of the timing wide number cpRTR. In addition, 'when the timing signal cPRRT is at the high level, the control Section 52 can change the state of the turn-on signal (pTR-PMOS bit into LV Λ 转换 转换 128 552 552 552 552 552 552 552 552 552 552 552 552 552 552 552 552 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 A high impedance period is provided. Thus, for example, when the timing signal cptTR is at a high level, it is provided to provide a plurality of high impedance periods or no high impedance period at all. Gate signal TR(n), but for the reset signal RST(4) and the select signal SEL(n), φ can also cause the control section 52 to level the turn-on signals ρΜΤ-ρΜ〇§ and cpSEL_PMOS. Changing to cause the reset junction and the selected junction to be placed in a high impedance state during a change in the level of the reset signal RST(n) and the select signal SEL(n) to prevent feedthrough current from The potential flows to the potential VSS. Figure 8 shows An example of one of the configuration of one of the pixel driving circuits of the cM〇s image sensor according to a second embodiment of the present invention. Referring to FIG. 8, the pixel driving circuit 1 includes a address decoder. u, a timing adjustment section 1〇1, a driver section 1〇2, and a control section 1〇3. The pixel driving circuit 1〇〇 generates and outputs: a transmission gate signal TR(n), a reset a signal RST(n) and a selection signal SEL(n) each having an intermediate level; and a transmission gate signal TR(n), a reset number RST(n), and a selection signal SEL(n) , which has the high level or the low level individually. It should be noted that although FIG. 8 shows a part of the pixel driving circuit 1 that generates the transmission gate signal TR(n) for convenience of explanation, it is similar. The reset signal RST(n) and the selection signal SEL(n) are generated and outputted by the transmission gate signal TR(n). It should be noted that the pixel driving circuit 1 includes 128552.doc •26·200904168 Reference is made to Figures 1 and 3 for several common components of the components, and the weight of such common components is omitted here. In order to adjust the timing of the generation of the transmission gate signal TR(n), in the timing adjustment section 101, two OR circuits 111 and i 1 2 and two NOT circuits 113 are 114 is placed in a stage before the driver section 102. In addition, the timing adjustment section 101 individually inputs an input signal to the two pMOS transistors 12 1 and 122 and an nMOS transistor 123 of the driver section 102 to generate The transmission gate signal TR(n). Specifically, one of the outputs 彳s遽 of the timing adjustment section 1〇1 is input to the nMOS transistor 123 of the driver section 1〇2 and is also input to the OR circuits 111. And 112. In addition, an enable signal cpTR_PMOS1 outputting a timing for controlling the turn-on of the pMOS transistor 121 from the control section 1 〇3 is input to the NOT circuit 113, and the NOT circuit 113 is turned on the cpTR- The PMOS1 operates a logical negation operation and inputs a signal obtained by the logic negation to the 〇R circuit 丨丨1. The 〇R circuit 111 performs a logical OR operation on the signal output from the NOT circuit 60 and the signal output from the not circuit 113, and inputs a signal obtained by the operation of the logic 〇11 to the pMOS transistor 121. In addition, an on signal φτκ__pm〇S2 outputting from the control section 103 to control the timing of turning on the pM〇s transistor 122 is input to the NOT circuit 114, and the NOT circuit 114 is turned on. (pTR__PM〇S2 operates a logical negation operation and inputs a signal obtained by the logical negation to the OR circuit 112. The OR circuit 112 performs a signal that is rotated from the NOT circuit 60 and a signal output from the NOT circuit 114. Logic R operation, and 128552.doc -27- 200904168 will obtain a signal input to the pM〇s transistor 122 by the logical OR operation. As described above, the OR circuit 1 Π uses the circuit from the Ν〇τ The signal output from 丨3 is used to generate a signal to be input to the pMOS transistor 121 to be separated from a signal output from the Ν〇τ circuit 60 for input to the nMOS transistor 123. In addition, the OR circuit 112 uses the NOT from the NOT. The signal output by the circuit 114 generates a signal to be input to the pMOS transistor 122 to be separated from the signal to be input to the transistor 123. Therefore, the timing adjustment section 101 can individually control the signal. Equal pMOS transistors 121 and 122 and the nM 〇S transistor 123. The driver section 102 generates the transmission gate signal TR(n) or the like according to a signal supplied thereto from the timing adjustment section! 。. Specifically, in the driver section 102 The pMOS transistors 121 and 122 are connected in parallel, and the pMOS transistors 121 and 122 are connected in series with the nMOS transistor 123. A potential VDD 1 is connected to the pM〇s transistor as a high level potential. The source of 121 is connected to the source of the pMOS transistor 122 as a medium level potential. In addition, the potential vSS is connected to the source of the nMOS transistor 1 23 as a low level potential. The 〇R circuits u 丨 and 丨丨 2 of the timing adjustment section 1 与 and the 彳 § of the N 〇 T circuit 60 are respectively input to the pM 〇 s transistors 121 and 122 and the nMOS The gate of the crystal 1 23 is placed in an on or off state in response to the level of the signal supplied to the pMOS transistors 121 and 122 and the individual gates of the nMOS transistor 1 23 Interconnecting the pMOS transistors 121 and 122 with the drain of the nMOS transistor 123 The potential at one point (hereinafter referred to as 128552.doc -28-200904168 three connection points) is changed to the potential VDD1, the potential VDD2, or the potential VSS. Then, the signal whose potential is changed as described is used as the transmission gate signal. TR(n) is applied to the transmission gate of the pixel in the nth column of the pixel segment. In this manner, in the driver section 丨〇2, the transmission gate signal TR(n) is generated and output in response to the signal supplied from the timing adjustment section 101. The shai control section 103 generates the timing signal at a predetermined timing, the turn-on signal cpTR-PMOS1, the turn-on signal individually has the direction or the low level, and supplies the signals to the timing adjustment section 10 1. It should be noted that although the potential VDD2 is connected to the pM 〇s transistor 122 in Fig. 8, the potential VDD2 may be connected to an nM 〇s electric crystal. In this example, the potential VDD2 is connected to the 2nM〇s electro-crystalline system and, if connected to the nMOS transistor 123, one of the signal system inputs is obtained by inverting the k-number output from the OR circuit 丨丨2. To the pole between the nM〇s transistors. Now, an example of the timing of signals related to the output of the transmission gate #TR(n) in the pixel driving circuit 1A shown in Fig. 8 will be described with reference to Fig. 9. If the level of the column selection signal cpV_LINE(n) changes from time to time from the low level to the high level, then the level of the timing signal ^RTR changes from the low level to the high level at time t52 (eg, As shown in FIG. 9, the level of the signal to be input to the nMOS transistor 123 becomes the low level. In addition, at this time, if the turn-on signal φΤ1ι_ΡΜ〇δ1Λ (the level of ρΤΙι-pM〇s2 is low level (as shown in FIG. 9), it is to be input to the pM〇s transistors 128552.doc -29 · 200904168 1 2 1 and 1 2 2 both of the levels of the § § are changed to the high level. Therefore, the pMOS transistors 121 and 122 and the nM 〇S transistor 123 are placed in a closed state, The three connection points are placed in a high impedance 丨)) state. Therefore, if the level of the turn-on signal cpTR_PMOS 1 changes from the low level to the high level at time t53 (as shown in FIG. 9), the level of the signal to be input to the pMOS transistor 122 remains. When the level of the signal to be input to the nMOS transistor 123 is maintained at the low level, the level of the signal to be input to the pMOS transistor 121 is changed to the low level. Therefore, when the state of the pMOS transistor 122 and the nMOS transistor 123 is maintained in the off state, the pMOS transistor 12 1 is placed in an on state. Therefore, the high-level transmission gate signal TR(n) of the potential VDD1 is output to the pixel section (as shown in Fig. 9). Although 'when the timing signal cpRTR level changes to the high level at time t52', the nMOS transistor 123 is placed in an off state and the output of the low level of the potential gate VSS of the transmission gate signal TR(n) ends ( As described above, 'but as of the turn-on signal tpTR_PMOS1 or the turn-on signal (the level at which the level of pTR_PMOS2 becomes the high level... the pM〇s transistor 121 or the pMOS transistor 122 is not placed in an on state. Therefore, the two connection points are placed in a south impedance state. Therefore, if the on signal (the level of pTR_PMOS 1 returns from the high level to the low level at time t54 (as shown in FIG. 9), then When the level of the signal input from the pM〇s transistor 122 and the nMOS transistor 123 is not changed, the level of the signal to be input to the pMOS transistor 121 is returned to the high level. Therefore, g § hai pMOS transistor 1 22 and the nMOS transistor 123 protects J28552.doc -30- 200904168 When the off state is maintained, the pMOS transistor 121 returns to the off state and the three connection points are placed into a high impedance (Hi_z(2)) The status is as shown in Figure 9. As mentioned above, the control The segment 103 can place the pM〇s transistor i2i into a factory-on state to change the level of the turn-on signal CpTR-PMQS丨 to the high level by maintaining the level of the RTR at the high level. The level of the transmission gate signal D(4) is changed. Therefore, the control section 1〇3 can control the level of the ON_CpTR_PM〇S1 during the control period to maintain the high level and the level of the timing signal cPRRT maintains the high level. The quasi-period, thereby controlling the turn-on period of the pMOS transistor 121 to control the level of the inter-transmission signal TR(n) during the control period is the supply/omission, length, and start timing of the high-level period of the high level. The turn-on signal (the level of pTR_PMOS2 is returned from the low level to the still level at the time... as shown in FIG. 9), and the signal is to be input to the transistor 121 and the nM〇S transistor 123. When it is not changed, the level of the signal to be input to the pMOS transistor 122 is returned to the low level. Therefore, when the pMOS transistor 121 and the nMOS transistor 123 remain in the off state, the pM〇s The transistor 122 is placed in an open state, and the electricity is The output gate signal TR(n) in the bit VDD is output to the pixel segment (as shown in Figure 9). Then 'If the turn-on signal (the level of pTR_PMOS2 returns from the high level to the time at time t56) The low level (as shown in FIG. 9) is the level of the signal to be input to the pMOS transistor 121 when the level of the signal to be input to the pM〇s transistor 121 and the nMOS transistor 123 is not changed. Return to the high 128552.doc 200904168 level. So when should that? When the transistor 121 and the nMOS transistor 123 remain in the off state, the pMOS transistor 122 returns to the off state and the three connection points are placed in a high impedance (Hi_z(3)) state (eg, Figure 9)). In this way, the control section 1〇3 can change the level of the turn-on signal (()111_1>] 82 to the high level while the level of the timing signal cPRRT maintains the high level, thereby The pMOS transistor 122 is placed in an on state to change the level of the transmission gate signal TR(n) to the intermediate level. Since the "Hai control area ^1 〇3 can be controlled during the period of the on signal The level of the ruler-pm〇s2 maintains the high level and the level of the ruler in the timing signal maintains the period of the high level, thereby controlling the turn-on period of the pM〇s transistor 122 to control the transfer gate during the control period. The level of the signal 711 (11) is the supply/omission, length and start timing of the medium level intermediate level. Then, if the level of the timing signal CpRTR returns from the high level to the low level at time h (As shown in Fig. 9), the level of the signal to be input to the nM〇s transistor 123 is changed to the high level. In addition, at this time, if the opening nickname...the 卩一卩河(10)丨 and less D, pM〇s22 level will remain at the s low level (as shown in Figure 9), then you want to enter these The level of the signals of the crystals 12 1 and 122 are changed to the high level. Therefore, when the states of the PMOS electric cells a and 121 are kept in the off state, the nMOS electric day and the sun body are set. The human-on state turns the low-level transmission signal of the potential vss to the pixel segment (8) to the pixel segment (as shown in Fig. 9). Next, the right at time in the column select signal 9V-LINE(n The position of the position k is changed to the low level, but the timing signal and the level of the opening signals cpTR_PM〇S丨 and cpTR_PM〇S2 of the 128552.doc -32-200904168 signal are kept at the low level (Fig. 9). As shown, the level of all signals to be output to the pMOS transistors i2i and 122 and the nMOS transistor 123 is maintained at the high level. Therefore, the low level of the transmission gate signal TR(4) of the potential vss continues to be output to The pixel segment (as shown in Figure 9). In this manner, 'in Figure 9', the level of the transmission gate signal TR(4) changes from the low level to the high level, from the high level to the medium level. In the case of a level change or a change from the medium level to the low level, the transmission pole The level of the signal TR(n) is changed to have a high impedance state midway during the above change period. In this manner, during the above change, the three connection points can be provided with a period of -high impedance state to prevent During the change period, the feedthrough current flows from the potential VDD to the potential vss. In addition, during the period, the levels of the turn-on signals 9TR-PM(10) and φΤΙ^ρΜϋδ2 are placed in the low level and the timing signal (4) is The level is the high level (as shown in Figure 9) - the three connection points should have a period of 1 high impedance state during the period. Therefore, the conversion timings and pulse periods of the ON signals cpTR_PMQS and 9TR_P can be changed so that the three connection points have a high-impedance arbitrarily long length during an arbitrary timing supply period. cycle. For example, a separate high-impedance period Hiz(1), a separate period Ηί_Ζ(2), a separate period Hi_Z(3), separate periods Hi-Z(1) and Hi_Z(2), separate periods H^1), and Hi_Z can be provided ( 3) or separate periods m_z(7) and m-zp). In addition, the control section (8) I28552.doc • 33- 200904168 may not provide any high-impedance period at all, in addition to preventing the feed-through current from being more important to attenuate the still-impedance period to shorten the time. It should be noted that although the AND circuit 22 and the OR circuit 23 shown in FIG. 1 are not provided in any of the above-described pixel driving circuits 50 and 1 , it may be similar to the pixel driving circuit shown in FIG. 1 . And in other ways. The following describes the configuration of one of the pixel drive circuits in one of the ways described, for example. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a diagram showing an example of one of the configuration of one of the pixel driving circuits of a CMOS image sensor according to a third embodiment of the present invention. It should be noted that for convenience of explanation, FIG. 1A shows a portion of a pixel driving circuit for driving pixels in the nth column. In addition, although in FIG. 1 'an AND circuit, an OR circuit, and a NOT circuit are used for simplicity, an actual circuit can be implemented by using a nand circuit, a NOR circuit, and a τ circuit. . The same also applies to one of the circuits described below with reference to FIG. The pixel driving circuit 丨50 shown in FIG. 1 includes a bit address decoder ii, a driving 1 § section 13, a timing adjustment section 15 5 and a control section 丨 52, and generates and outputs a transmission gate. The pole signal TR(n), a reset signal RST(n) - selects the signal SEL(n). It should be noted that the pixel drive circuit 丨5〇 includes several common components of the components described above with reference to Figures 1 and 3, and overlapping descriptions of such common components are omitted herein to avoid redundancy. The timing adjustment section 151 includes an AND circuit 2 1 , another AND circuit 22 , an OR circuit 23 , a NOT circuit 24 , another OR circuit 61 , and a NOT circuit 66 . A logic gate circuit for adjusting the timing of the generation of the transmission gate signal TR(n). The timing adjustment section 128552.doc -34 - 200904168 15 1 further includes an AND circuit 25, a NOT circuit 26, an OR circuit 62 and another NOT circuit 65, which are used together to adjust the reset A logic gate circuit for the timing of the generation of the signal RST(n). The timing adjustment section 151 further includes an AND circuit 27, a NOT circuit 28, an OR circuit 63, and another NOT circuit 64'. The circuits cooperate to serve as a timing for adjusting the generation of the selection signal SEL(n). Logic gate circuit. Specifically, in the timing adjustment section 151, the OR circuits 6 1 to 63 and the NOT circuits 64 to 66 are placed in a stage before the driver section 13. In addition, in the timing adjustment section 151, the same signal is not input to the pMOS transistor 31, 33 or 35 and the nMOS transistor 32, 34 or 36 of the driver section 13, but by logic A 〇R operation (which uses one of the signals to be input to the nMOS transistor 32, 34 or 36) is input to the pMOS transistor 31, 33 or 35. Specifically, a signal from the NOT circuit 24 output of the timing adjustment section 151 is input to the nMOS transistor 3 2 of the driver section 13 and is also input to the OR circuit 61. Further, an on signal cpTR_PMOS outputted from the control section 152 for controlling the timing of turning on the pMOS transistor 31 is input to the 玄NOT circuit 66. The NOT circuit 66 operates a logical negation operation on the turn-on signal cpTR_PMOS and inputs a signal obtained by the logic negation to the OR circuit 61. The OR circuit 61 performs a logical OR operation on the signal output from the NOT circuit 24 and the signal output from the N〇T circuit 66, and inputs a signal obtained by the logic 〇R operation to the pMOS transistor 3 1 . . Specifically, the OR circuit 61 uses the signal output from the NOT circuit 66 to generate a signal to input 128552.doc -35 - 200904168 to the pMOS transistor 31 and output from the NOT circuit 24 for input to the nMOS The signal of crystal 32 is separated. Therefore, the timing adjustment section 151 can individually control the pMOS transistor 3 1 and the nMOS transistor 32 °, and input a signal from the NOT circuit 26 output of the timing adjustment section 151 to the The nMOS transistor 34 of the driver section 13 is also input to the OR circuit 62. Further, an ON signal cpRST_PMOS outputting a timing for controlling the turn-on of the pMOS transistor 33 from the control section 152 is input to the NOT circuit 65. Next, the NOT circuit 65 operates a logical negation operation on the turn-on signal cpRST_PMOS and inputs a signal obtained by the logic negation to the OR circuit 62. The OR circuit 62 performs a logical OR operation on the signal output from the NOT circuit 26 and the signal output from the NOT circuit 65, and inputs a signal obtained by the logical OR operation to the pMOS transistor 33. Therefore, the timing adjustment section 151 can individually control the pMOS transistor 33 and the nMOS transistor 34. Further, a signal output from the NOT circuit 28 of the timing adjustment section 151 is input to the nMOS transistor 36 of the driver section 13 and is also input to the OR circuit 63. Further, an on signal cpSEL_PMOS outputting a timing for controlling the turn-on of the pMOS transistor 35 from the control section 152 is input to the NOT circuit 64. Next, the NOT circuit 64 operates a logical negative operation on the turn-on signal cpSEL_PMOS and inputs a signal obtained by the logic negation to the OR circuit 63. The OR circuit 63 performs a logical OR operation on the signal output from the NOT circuit 28 and the signal output from the NOT power 128552.doc -36 - 200904168 path 64 and inputs a signal obtained by the logic operation to The pMOS transistor 35. Therefore, the timing adjustment section 151 can individually control the pMOS transistor 35 and the nM〇s transistor 36. The control section 152 generates timing signals cpSEL, (pRST, (pSTR, and (pRTR) and the enable signals q>TR_PMOS, (pRST_PMOS and cpSEL_PMOS, respectively) having the high level or the low level, and the predetermined timings Signal is supplied to the timing adjustment section 151. Now, an example of the timing of the signal related to the output of the transmission gate signal TR(n) in the pixel driving circuit 15A shown in FIG. 1A will be described with reference to FIG. The level of the column selection signal φV_LINE(n) changes from the low level to the high level at time ti and then the timing signal φ8τκ or the timing signal (the level of prtr changes from the low level to the high level at time tu (as shown in FIG. 7) 'The level of the signal generated by the AND circuits 21 and 22, the OR circuit 23, and the NOT circuit 24 so as to be output to the nM〇s transistor 32 is changed to the low level. At this time, if the level of the turn-on signal φ ΤΚ - pM 〇 s is the low level (as shown in FIG. 11 ), the AND circuits 2 ι and 22, the OR circuit 23, the NMOS circuit 24, and the 〇R circuit 61 are provided. And the _ circuit is "generated for input to the ρ Μ OS transistor The signal of 3丨 is changed to the high level (as shown in FIG. 1). Therefore, both the 5 PMOS PMOS transistor 3 1 and the nM 〇S transistor 32 are placed in a closed state, and the transmission gate is bonded. The point is placed in a high-impedance (Hi-Z) state, as shown in Figure 1. Therefore, if the level of the turn-on signal CpTR_PM〇S changes from the low level to the high level at time h (as shown in Figure U) ), the level of the signal of the body 32 to be input to the transistor 31 is changed to the low level, and the level of the signal to be input to the transistor 31 is changed to the low level. Therefore, when the nMOS transistor 32 is kept in the off state, the pM〇s transistor 3 1 is placed in an on state to output the high-level transmission gate signal TR(n) of the potential VDD to In this manner, if the timing signal or the timing signal φΚΤΙι level changes to the high level at time tz, the nM〇s transistor u is placed The output of the low-level transmission gate signal TR(n) of the potential vss is ended, but up to the turn-on signal (pTR) The time tn at which the PMOS level is at the level of the level does not place the pM〇s transistor 31 into an on state. Therefore, the transmission gate junction is placed in a high impedance state. The level of the turn-on signal CpTR_PM〇S changes from the low level to the high level (as shown in FIG. U), and the level of the signal to be input to the transistor (10) transistor 32 maintains the low level, but The level of the signal input to the transistor 31 is returned to the high level. Therefore, when the nM〇S transistor 32 remains in the off state, the state of the pMOS transistor 31 returns to the off state and the transmission gate junction is again placed in a high impedance state (as shown in FIG. 11). ). Therefore, if the timing signal CpSTR or the timing of the timing signal changes to the low level at time t5 (as shown in FIG. u), the level of the signal to be input to the nMOS transistor 32 is used. Become the high level. In addition, at this time, if the level of the turn-on signal cpTR_PM0S is kept low (as shown in Fig. u), the level of the signal to be rotated into the pM0S transistor 31 is changed to the high level. Therefore, when the pM〇s transistor 31 remains in the closed state 128552.doc •38·200904168 2 'the nM〇s transistor 32 is set to the on state and the low level of the potential is transmitted to the gate signal TR(n) is output to Figure 11).斤' 匕f again, because, although the column selection signal φν LINE(n) is at the level ti6 攸. The position of the hainan is changed to the low level (as shown in FIG. 11), but if the timing signal or the timing signal and the low level of the ping signal cpTR_PMOS are low, the PMOS transistor 31 and the PMOS transistor 31 are to be input. The level of the signal of the nM〇S transistor 32 maintains this high level. Therefore, the transmission gate signal TR(4) of the potential VSS is output to the pixel section (as shown in Fig. 2). In this way, when the level of the transmission gate signal TR(4) changes from the high level to the low level and from the low level to the high level, the control section 152 turns the on signal ^R_pM〇s The level is changed such that the transfer gate junction is placed in a high impedance state during the & Therefore, once the change described above occurs, the PMOS transistor 31 and the s-transistor are immediately turned "on" to prevent the feedthrough current from flowing from the potential VDD to the potential vss. Therefore, the prevention is prevented. The low level of power supply fluctuations. In addition, in particular, the negative potential generated by the charging pump inside the wafer (on which the pixel driving circuit 15 is provided) is set to the low level potential state In this case, the load on the charging pump is eliminated. Therefore, the deterioration of the image quality of the pixel section can be prevented. In addition, the control section 152 can set the timing signal, the timing signal cPRRT or the turn-on signal center. The switching timing and pulse of the level of the touch 8 is changed to 128552.doc •39- 200904168 It is changed so that the transmission gate sequence and W or length·· bits can be changed during the following periods. The potential of 唬TR(n) is During the potential vdd, the potential of the transmission gate is deficient, and the potential of the R(n) is the period of the potential VSS and the period where the x & gate junction is in the -high impedance state (referred to as the period of the impedance) ). Poor skin > spit / ( Surface 'Μ T sequence number k φδΤΚ, timing signal (PRTR or Η start " is number (pTR + &, Α stay open - <Level conversion timing and pulse length change can be in any way (for example, the borrower in the borrower (not shown (10) implementation ^ (four) (four) section 152 = 'in the transmission gate money TR (8) level (four) In the case where the low level changes to the level of δ hai (such as ^ 2), the change period 152 can be placed in the high-impedance state and the feedback is suppressed. The flow of the current is passed. In addition, the control section is changed during the change of the position of the transmission gate signal, (4) from the high level to the low level (as shown in FIG. 13). 152 can connect the transmission to the "Wh λ ' ν impedance state, thereby suppressing the flow of the feedthrough current. As shown in Fig. 12, the position of the transmission gate signal TR(n) is From the low 'quasi-change to 3 hainan level', if the transmission gate junction is to be placed in the _high-impedance state during the change described, then the control section 152 is not in time before time t5 Ttl4 and changing the level of the on signal q>TR_PMOS from the high level to the time after time ti5 Therefore, since the γ 曰 电 电 电 电 置 置 置 置 置 置 置 置 置 置 置 HC HC HC HC HC HC HC HC HC HC HC HC HC HC HC HC HC HC HC HC HC HC HC HC HC HC HC HC HC HC HC In the case where the high level is changed to the low level, the transmission gate junction is not placed in the high impedance state by 128552.doc -40·200904168. In addition, the position of the transmission gate signal (8) is changed.兮 隹, 隹 γ ^ This position is changed to k and low # (as shown in Figure 13) in the case of a change in the time to change the transmission gate, the control section kisses in time two silly time t丨3 and at the time f =: this: the level of the start signal ~ from this:: This, because the PMOS transistor 32 is placed in the -on state while the PMOS transistor 31 is placed in a close State, the position of the p-transmission idle signal TR(8) is changed from the low level to the high level, and the transmission gate junction is not placed in a high-impedance state. In addition, in addition to preventing the feedthrough current, more attention needs to be paid to shortening the high resistance = cycle to shorten the time or the clock cycle. 'In the case where the level of the transmission closed-loop signal TR(8) is changed from the high level to the low level, and the condition in which the transmission gate signal TR(4) is to be changed from the low level to the side position In the other case (as shown in Figure 14), the control section 152 prevents the transmission gate from being engaged in this example during the change described, which is in time. Time t3 before t, 2! The on signal (the level of pTR_PM〇S is changed from the low level to the high level) and the time tzl after time h is the on signal (pTR_PMOS level from the The high level changes to the low level, as shown in FIG. Specifically, the control section 丨52 sets the length of the pulse of the turn-on signal tpTR-PMOS to be longer than the length of the pulse of the timing signal cpSTR or the timing signal cpRTR. 128552.doc -41 - 200904168 In addition, when the timing signal cpSTR or the timing (4) of the timing (4) maintains the high level, the control section 152 can change the level of the opening signal CPTR-touch S to be at the same level. Turning between the on and off states (4) The state of the PMOS transistor 31 to provide or not provide - a high impedance period. So, for example, when the timing letter? “The STR or the position of the (10) in the ordinal signal of the day is as high as: punctuality can provide multiple high impedance periods or no south impedance period at all.

It should be noted that although the transmission gate signal (3) (4) is described above, for the reset signal RST (4) and the selection signal SEL (n), the control section 152 can also be caused to cause the on signals cpRST_PM0S and cpSEL to be - The level of PM0S is changed such that the reset junction and the selected junction are placed in a high-impedance state during the change of the reset signal hunger (4) and the level of the selection signal SEL (η) to prevent the feedthrough current This potential VDD flows to the potential vss. Figure 15 shows an example of one configuration of one of the pixel drive circuits of a cM〇s image sensor in accordance with a fourth embodiment of the present invention. Referring to FIG. 5, the pixel driving circuit 200 includes a bit address decoder, a timing adjustment section 201, a driver section 102, and a control section 2〇2. The pixel driving circuit 200 generates and outputs: individually Having a medium-level transmission gate signal TR(n), a reset signal RsT(n), and a selection k-number SEL(n); and individually having a high level or a low level - a transmission gate Signal TR(n), _ reset signal RST(n), and a select signal SEL(n). It should be noted that the portion of the pixel driving circuit 200 that generates the transmission gate 328552.doc -42-200904168 pole signal TR(n) is shown for convenience, but is similar to the transmission gate. The reset signal RST(n) and the selection signal SEL(n) are generated and output by the signal TR(n). It should be noted that the pixel drive circuit 2 includes several common components of the components described above with reference to Figures 1 and 8, and overlapping descriptions of such common components are omitted herein to avoid redundancy. In the timing adjustment section 201, in order to adjust the timing of the generation of the transmission gate signal TR(n), two NR circuits U1 and 112 and two 〇 电路 circuits 113 and 114 are placed in the driver area. Stage 1〇2 before the level. The timing adjustment section 20 1 individually inputs the input signals to the two pMOS transistors 121 and 122 of the driver section 丨〇2 and an nMOS transistor 123 to generate the transmission gate signal TR(n). Specifically, the k number output from the Ν〇τ circuit 24 of the timing adjustment section 2〇丨 is input to the nM〇s transistor i 23 of the driver section 1 〇2 and is also input to the OR circuits 1U. And 112. Further, an ON signal tpTR_PMOS1 outputting one of the timings for controlling the turn-on of the pMOS transistor 121 from the control section 2〇2 is input to the NOT circuit 113. The NOT circuit 113 operates a logical negation operation on the ON signal q > TR_PMOS1 and inputs a signal obtained by the logic negation to the scale circuit U1. The 〇R circuit m performs a logical OR operation on the signal output from the NOT circuit 24 and the h number output from the Ν〇τ circuit 113, and inputs a signal obtained by the logic 〇R operation to the pMOS transistor. 12 1. In addition, one of the outputs from the control section 2〇2 is used to control this? The turn-on signal φΤΓι_ρΜ〇82 of the timing at which the crystal 122 is turned on is input to the NOT circuit 丨丨4. The NOT circuit 丨 14 performs a logical negation operation on the turn-on signal φ ΤΙ 一 〇 〇 128 552 552 552 552 552 552 552 552 552 552 552 552 552 552 552 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The OR circuit 112 performs a logical OR operation on the signal output from the NOT circuit 24 and the signal output from the NOT circuit 114, and inputs a signal obtained by the logic 〇R operation to the pMOS transistor 122°. In this manner, the OR circuit U1 uses a signal output from the NOT circuit 113 to generate a signal to be input to the pMOS transistor 121 to be separated from a signal output from the NOT circuit 24 for input to the nMOS transistor 123. At the same time, the OR circuit 112 uses the signal output from the NOT circuit 114 to generate a signal to be input to the pMOS transistor 122 to be separated from the signal to be input to the nMOS transistor 123. Therefore, the timing adjustment section 2〇1 can individually control the pMOS transistors 121 and 122 and the nMOS transistor 123. The driver section 1 〇 2 generates a 5 Hz transmission gate signal TR(n) in response to a signal supplied from the timing adjustment section 2 。. Specifically, in the driver section 102, the pMOS transistors 121 and 122 are connected in parallel, and the pMOS transistors 121 and 122 are connected in series with the nMOS transistor 123. The potential VDD1 is connected to the source of the 13-well transistor 121 as a high level potential, and the potential VDD2 is connected to the source of the pMOS transistor 122 as a medium level potential and the potential VSS is It is connected to the source of the nMOS transistor 123 as a low level potential. The signals supplied from the OR circuits U1 & 112 of the timing adjustment section 201 and the Ν〇τ circuit 24 are input to the gates of the pM 〇 s transistors and 122 and the gates of the nMOS transistors 123, respectively. In response to the level of the signals supplied to the respective gates of the pMOS transistors 121 and 122 and the nMOS transistors 128552.doc -44 - 200904168 1 2 3, the transistors are placed in an on or off state, The potential at the point where the pMOS transistors i 2 1 and 122 and the gate of the β-n nMOS bb body 123 are connected to each other (hereinafter referred to as = connection point) is changed to the potential VDD1, the potential VDD2, or the potential VSS. . A signal whose potential is changed as described above is applied as the transmission gate signal TR(n) to the transmission gate of the pixel in the nth column of the pixel section. In this manner, the drive benefit section 1 〇 2 generates and outputs the transmission gate signal TR(n) in response to the 彳§ number supplied from the timing adjustment section 201. The control section 202 generates the timing signals and the pRTR, the turn-on signals (pTR_PMOS1 and q>TR_PM0S2, etc. (which individually have the high level or the low level) at a predetermined timing and supply the generated signals Up to the timing adjustment section 201. It should be noted that although the potential VDD2 is connected to the pM〇s transistor 1 22 in FIG. 15, it may alternatively be connected to an nMOS transistor. In this example An nMOS transistor system to which the potential VDD2 is connected is connected in parallel to the nMOS transistor 123, and a signal signal is input to the gate of the nMOS transistor by inverting a signal output from the 〇R circuit 112. 'An example of the timing of the signal associated with the output of the transmission gate signal TR(n) in the pixel driving circuit 2A shown in Fig. 15 is explained with reference to Fig. 16. If the column selection signal cpV_LINE(n) is at the level The time t5i is changed from the low level to the high level, and then the timing signal or the level of the timing signal cpRTR is changed from the low level to the high level at time h (not shown in FIG. 6). The level of the signal of the nMOS transistor 123 becomes In this case, if the turn-on signals 128552.doc •45-200904168 PMOS1 and (pTR-PMOS2 are low level (as shown in Figure 16), then the pMOS is to be input. The level of the signals of both the crystals 121 and 122 becomes the same level. Therefore, the pM〇s transistor 121 and the iiMOS transistor 123 are placed in a closed state, and the three connection points are placed. Enter a high-impedance (Hi-Z(l)) state, as shown in Figure 16. Therefore, if the turn-on signal (pTR-PMOS1 level changes from the low level to the high level at time t53 (as shown in Figure 16) In the case where the level of the signal to be input to the pMOS transistor 122 is maintained at the high level and the level of the signal to be input to the nMOS transistor 123 is maintained at the low level, the pMOS transistor 121 is to be rotated. The level of the signal is changed to the low level. Therefore, when the pMOS transistor 122 and the nMOS transistor 123 remain in the off state, the pMOS transistor 121 is placed in an on state, and the potential VDD1 is The high level transmission gate signal TR(n) is output to the pixel section (as shown in FIG. 16). In this manner, when the timing signal φ8τκ or the level of the scale in the timing signal changes to the local level at time t; 52, although the transistor 123 is placed in a closed state and the potential VSS is low. The output of the transmission gate signal TR(n) ends, but the time t53 until the level of the turn-on signal "pM〇s" or the turn-on signal q>TR_PMOS2 becomes the high level does not cause the ^pMOS The crystal 121 or the pM〇s transistor 122 is placed in an open state. Therefore, the three connection points are placed in a high impedance state. Therefore, if the level of the turn-on signal cpTR_PM〇sl returns to the low level from the level at time h (as shown in FIG. 16), the transistor 122 and the nM〇s are intended to be directed to the pM〇S. The level of the signal input by the transistor 123 is not changed. 128552.doc 46- 200904168 Change '= The level of the signal to be turned to the PMQS transistor 121 will also return to the level. Therefore, when the pM〇s transistor (1) and the side (10) transistor 123 remain in the off state, the state of the (4) (10) transistor (2) returns to the off state and the three connection points are placed in a high impedance (HU ( 2)) Status (as shown in Figure 16). In this way, the control section 2〇2 can change the level of pM〇si in the turn-on signal to the_South level while the timing signal ΜΗ or the timing L number (the level of the pRTR maintains the high level, Therefore, the pM〇s transistor 121 is placed in an on state to change the level of the transmission gate signal TR(n) to the high level. Therefore, the control section 202 can control the on signal cpTR_PMOS during the control period. The level of 1 maintains the high level and the timing signal...the level of the squaring or cpRTR maintains the period of the high level, thereby controlling the turn-on period of the pM〇s transistor 121 to control the transmission gate signal TR(n) during control. The level of the high level is the supply/omission, length and start timing of the high level. Therefore, if the turn-on signal (pTR_PMOS2 level changes from the low level to the high level at time t55 (Figure 6) As shown, although the level of the signal to be input to the pMOS transistor 121 and the nMOS transistor 123 does not change, the level of the signal to be input to the pMOS transistor 122 also changes to the low level. When the pMOS transistor 121 and the nMOS transistor 1 23 remain In the off state, the pMOS transistor 122 is placed in an on state, and the equal-level transmission gate signal TR(n) in the potential VDD2 is output to the pixel segment (as shown in FIG. 16). If the level of the turn-on signal cpTR_PMOS2 returns from the high level of 128552.doc -47 - 200904168 to the low level at time t56 (as shown in FIG. 6), the pixel is intended to be electrically connected to the pMOS transistor 121 and the nMOS. The level of the signal input by the crystal 123 does not change, but the level of the signal to be input to the pMOS transistor 122 also returns to the high level. Therefore, when the pM〇s transistor 1 2 1 and the nMOS transistor When the 123 is kept in the off state, the pM〇s transistor 122 returns to the off state and the three connection points are placed into a high impedance (Hi_Z(3)) shape (as shown in Fig. 16. In this way, the control section 2〇2 can change the level of the turn-on signal φΤΚ_ΡΜ〇82 to the high level while the level of the timing signal 9STR or the timing k number tpRTR is the high level, thereby Putting the pM〇s transistor into an on state to place the transmission gate signal TR(n) Changing to a moderate level. Therefore, the control section 2〇2 can control the turn-on signal (the level of pTR_PMOS2 maintains the high level and the timing signal or the level of the cpRTR maintains the high level period, thereby controlling the The turn-on period of the pM〇s transistor 122 is such that the level of the transfer gate signal tr(4) during the control period is the supply/omitation of the length and the order of the high level of the high level. If the timing signal cpSTR or the timing The level of the leg in the signal returns from the high level to the low level at time t57 (as shown in FIG. ,), and enters the nMOS transistor 1 91 smear station Λ, the 曰曰 别 123 123 The level changes to the high level, and the turn-on signals cpTR_PMOS1 and sigma-supplement (4) hold the low material (the signals to be input to the dedicated PMOS transistors 121 and 122 as shown in FIG. 16). The standard. Therefore, when the state of the transistor - hold = two 128552.doc -48 - 200904168 state, the nMOS transistor 123 is placed in an on state and the low level of the potential vs. the gate signal TR(n) ) Output to the pixel segment (as shown in Figure 16).

Therefore, although the level of the column selection signal φν_LINE(n) changes from the high level to the low level at time t58 (as shown in FIG. 16), if the timing signal φδΤΚ or the timing signal and the turn-on are turned on The signals (pTR-PMOS 1 and cpTR- PMOS 2 are maintained at the low level |, and the level of the signal to be applied to the pM 〇 s transistors 121 and 122 and the nMOS transistor 123 is maintained at the high level. The low-level transmission gate signal TR(n) of the potential vss continues to be output to the pixel segment (as shown in FIG. 16). As described above, in FIG. 6, the transmission gate signal TR(n) The transmission idle signal TR(n) is changed from the low level to the high level, from the high level to the medium level, or from the t level to the low level. The level change is changed to have a high impedance state midway during the above change period. In this manner, the period in which the three connection points remain in the -high impedance state during the change period can be provided, thereby preventing the change during the change period. The feedthrough current flows from the potential VDD to the potential vss. In addition, as shown in FIG. During the period, the on-signal (pTR-PMOS1 and cpTR_PMOS2 are both at the low level and the timing signal 咐r or cpim^ is at the high level - Zhou Qingcheng) during the three connection points (9) The period of the impedance-like evil. Therefore, the switching timing and the pulse period of the levels of the turn-on signals cpTR_PM〇S丨 and 9TR_PM〇S2 can be changed so that the three-connected point is at the time of the arbitrary timing supply. A period of any length of a high-impedance state. 128552.doc -49- 200904168 The case can be & for a separate high-impedance period Hi-Z (1), a separate period Hl_Z (2), a separate period Hi_Z (3 ), separate periods Hi-Z(l) and Hi-Z(2), early periods m_z(1) and Hiz(3) or separate periods ζ(2) and Η〗-Ζ(3) In addition, in addition to preventing the feedthrough current from being more important to shorten the high impedance period to shorten the time T, the control section 202 may not provide any high impedance period at all. It should be intentional, for the position of the signals. By default, the scratchpad (not shown) provided in the control area #52 1 03, 152 or 202 can be used. The setting is applicable to any value of the pixel boat circuit 5〇, 100, 150 or 200. It should be noted that although the timing (4) or the timing signal cPRTR is described in the foregoing description with reference to the drawings and the description thereof. The level is the high level or the low level, but the description includes _ wherein the timing signals cpSTR and (pRTR are both the high level or the low level and one of the timing signals 咐r "Rtr The -signal level is the high level or a low level and the timing signals (10)(7) and ? The other of rtr - the level of the signal - keeps the low level. In the latter case, which of the timing signals cpSTR^RTR (4) has the high level, the high impedance control can be implemented by using the turn (4). In the present specification, the description of the program recorded in a recording medium may be, but does not necessarily have to be, processed in a time series in the illustrated order, and π includes parallel or individual execution instead of one time. The series to handle the program. Although specific terms have been used to describe the preferred embodiments of the present invention, such description is only for the purpose of the explanation, but it should be understood that the changes and changes are made by some of the 128552.doc -50-200904168 instead of Deviate from the spirit or scope of the following patent application. Those skilled in the art should understand that various modifications, combinations, sub-combinations and alterations may be made depending on the design requirements and other factors, as long as they fall within the scope of the appended claims or their equivalents. FIG. 1 is a circuit diagram showing a conventional pixel driving circuit; FIG. 2 is an example of a driving electric diagram shown in FIG. 1; one of the timings of the Τ and 諕 timings is shown in FIG. FIG. 4 to FIG. 7 are diagrams showing a timing diagram of the pixel driving timing relationship shown in FIG. 3 according to one embodiment of the present invention and the configuration of the dynamic circuit. Different FIG. 8 shows a four-body embodiment of a configuration of one of the ___ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 1 is a timing diagram showing a sequential relationship of a pixel drive in an embodiment of a second dynamic circuit according to one embodiment of the present invention; FIG. 1 is a diagram showing the invention according to the present invention. Dynamic circuit - configuration - example "body embodiment - pixel ^ phantom circuit diagram; Figure 11 to U system diagram shown in Figure 10 like symplectic: dynamic timing relationship date #床暗. ", in the dynamic circuit The signal is not driven. Figure 6 shows the signal in the pixel-driven Ray % + circuit shown in Figure 15. Time series 128552.doc -51 . 200904168 A timing chart. [Main component symbol description] 10 pixel drive circuit 11 address decoder 12 timing adjustment section 13 drive benefit section 14 control section 21 AND circuit 22 AND circuit 23 OR circuit 24 NOT circuit 25 AND circuit 26 NOT circuit 27 AND circuit 28 NOT circuit 31 pMOS transistor 32 nMOS transistor 33 pMOS transistor 34 nMOS transistor 35 pMOS transistor 36 nMOS transistor 50 pixel drive circuit 51 timing adjustment section 52 control section 128552.doc - 52- 200904168 60 NOT circuit 61 OR circuit 62 OR circuit 63 OR circuit 64 NOT circuit 65 NOT circuit 66 NOT circuit 100 pixel drive circuit 101 Timing adjustment section 102 Drive as section 103 Control section 111 OR circuit 112 OR circuit 113 NOT circuit 114 NOT circuit 121 pMOS transistor 122 pMOS transistor 123 nMOS transistor 150 pixel drive circuit 151 timing adjustment section 152 control section 200 pixel drive circuit 201 timing adjustment section 202 control section 128552.doc -53- 200904168 RST(n) reset signal SEL(n) select signal TR(n) Transmit gate signals cpSEL, cpRST, (pSTR and (pRTR timing signals cpTRPMOS, cpRSTPMOS, and (pSEL_PMOS turn-on signal cpTRPMOSl turn-on signal q> TR_PMOS2 turn-on signal cpV_LINE(n) column select signal -54- 128552.doc

Claims (1)

200904168 X. Patent application scope: 1. A driving device for driving a pixel, comprising: a first pMOS type transistor connected to a first potential; - an -nMOS type transistor, which is connected in series Connected to the first pM〇s-type transistor and connected to a second potential; and a control section configured to control the first PMOS transistor and the first nM by using one The first-on signal of the f-timed period of the 〇s-type transistor is used to individually control the first-pM〇s-type transistor and the first nMOS-type transistor, and the first pMOS-type transistor and the first- The signal at the -node between the nM〇s type transistors is used to drive the driving signal of the pixel and input to the pixel. 2. The driving device of claim 1, wherein the control section individually controls the first: PMOS type transistor and the first nM 〇s type transistor to control the potential at the node during the control period to be the first potential The _th potential period, the potential at the node is the second potential - the second potential period and the period is the length of the high impedance period and the start timing of one of the high impedance states. X. The squib of claim 2, wherein the control section controls the length of the first potential period, the second potential period, and the high impedance period and the start timing such that the first and second The period of the potential period - the period into which the other period of the period is provided provides the high impedance period. 4) The driving device of claim 1, further comprising: a second transistor 'connected to the second pM of the first pM〇s type 128552.doc 200904168 crystal and connected to a third potential a 〇s-type transistor and a second nMOS-type transistor connected in parallel to the first nMOS-type transistor and connected to the third potential; the control section is used by using the first turn-on signal and Controlling, by the second turn-on signal of the timing of turning on the second transistor, the first PM〇S-type transistor, the first nM〇s-type transistor, and the second transistor; and the first PM〇 A signal of the potential at a node between the S-type transistor, the first nM〇s-type transistor, and the second transistor is rotated into the pixel as the driving signal. 5. The drive device of claim 4, wherein the control section individually controls the first PM〇S transistor, the first nM〇st crystal, and the second transistor to control the node at the node The potential is the first potential period of the first potential, the potential at the node is the second potential - the second potential period, the potential at the period is the third potential of the 帛2 potential: The length of the high-impedance period and the turn-on timing of the node in a high impedance state during the period and period. The driving device of claim 5, wherein the control section controls the length of the ::, the third potential period and the high impedance period, and the opening, the first, second, and third potentials The high-impedance period is provided by the cycle-'conversion of different cycles. 128552.doc