TW200904011A - Improvements relating to analogue to digital converters - Google Patents

Abstract

An analogue to digital converter (ADC) (1) is provided which comprises an signal sampling device (5), a signal comparison device (3), and a digital signal generator (7, 9, 11). An analogue signal to be converted to a digital signal is input into the ADC, the signal sampling device produces samples of the analogue signal, the signal comparison device receives the analogue signal and the analogue signal samples, performs a comparison between them and outputs comparison signals, and the digital signal generator receives the comparison signals and uses them to generate a digital signal. The signal sampling device may produce voltage samples or current samples of the analogue signal.

Description

200904011 IX. INSTRUCTIONS: TECHNICAL FIELD OF THE INVENTION The present invention relates to an analog-to-digital converter (ADC) improvement. [Prior Art] A common component of a sub-device. Conventional ADCs are based on analog input. Time sampling of the signal, which depends on the analog signal value at each instant of the analog input signal sampling. This can cause many of the shortcomings of conventional ADCs. When analog to digital conversion occurs at many discrete, spaced transients It is not possible to determine the analog input signal between the two sampling instants. For time-varying analog input signals, when the analog input signal is temporarily close to constant, there is no need to perform digital signal conversion. At each = time The 'digital signal is generated by the transfer of the analog input value at the instant: the yield is not able to predict the resulting digital signal. The signal, regardless of the first two complex operations to convert the analog input. This needs to make: What operation? Performs an analog input signal conversion. This tears and has a structure to perform complex analog/digital whip operation characteristics (power consumption, ruler , and inch. Therefore, 'transformation and cost are very important. & speed, etc.) is the best (for example - in the portable device, the typical life of the limited power supply = electric thin and heart), which The power of the nest phone pad? | Pool) is very important. The voltage of the battery in the bee is preferably maintained in a continuous supervision mode with a standby mode 128675.doc 200904011

During the two periods. This is what many functions of the device's power management integrated circuit (pMIC) are required. Supervising the battery voltage requires quickly tracking the rapid change in voltage and avoiding voltage spikes. This functionality is provided by high resolution: software conversion (a general purpose ADC found on the device's PMIC). However, this ADC uses a battery voltage analog signal = conventional time sample that requires a clock. This ADC system will cause the ADC function to be unreasonable: power consumption. In addition, during the device standby mode, the only available clock is provided by the low frequency crystal oscillator. This low frequency clock cannot be used in the ADC function, so monitoring the battery voltage will be interrupted. The whip of these problems is W

In a heart appliance, the power source (battery) is not easily rechargeable or more. Because of &, it is absolutely important to limit battery power consumption as much as possible. This is not completely achieved by using a conventional ADC and associated clock. D [ SUMMARY OF THE INVENTION] The present invention provides an analog to digital converter and a method of converting an analog signal into a digital signal as described in the following application. [Embodiment] Referring to Figure 1, a first embodiment of the present invention includes an analog to digital converter (ADC). This includes an amplifier/subtractor 3, a signal sampling and holding system 5, a first comparator 7, a second comparator 9, and a tensor 11. A type of ratio signal (which translates into a digital signal) is a rounder/subtraction benefit of 3. The analog signal is also periodically input to the signal sample and ', , system, first 5. This includes a switch 丨3 and _ signal storage device 1% in the form of a 128675.doc 200904011 container. The switch 13 is closed and the signal sampling and holding system 5 samples the analog k number and stores the signal sample in the capacitor 15. The amplifier/subtracter 3 receives a first signal on the input labeled + and receives the second signal on the input labeled #. Amplifier/Subtractor:: Subtracts the second signal from the first signal, amplifies the resulting signal, and outputs the signal to each of the comparators 7, 9. The first comparator 7 receives the signal from the amplifier/subtracter 3 at the input labeled + and receives a signal w at the input of the flag. The first comparator 7 compares the two signals 'and outputs a digital signal containing i to the earner counter 11 if the input signal of the input + is greater than the signal of the input of the indication. The second comparator 9 receives the signal from the amplifier/subtracter 3 at the input of the flag - and receives a signal at the input labeled +. The second comparator 9 compares the two signals ' and outputs a digital signal containing 丨 to the n-bit counter 11 if the signal at the input indicating + is greater than the signal at the input. A signal from the first comparator 7 or from the second comparator 9

A signal of V will be output to the N-bit +古+叙·1 1 „ n ^ , i J Λ王IN诅70彳 number i, that is, the signals from the two comparators 7, 9 will not be simultaneously output to the N-bit The counter is completed. The N-bit counter U includes a counter portion which receives the output signals from the first and first ratios 7, 9. Upon receiving a signal from the first comparator 7, the counter portion is caused. Incremented by the value 。. On the - signal received from the first comparator 9, 'causes the counter portion to be a value (subtracted by 1. The value of the counter profit portion forms a digital signal D, which is equivalent to the analog input signal, And the N-bit counter 11 outputs the signal of |ADC 1. The N-bit counter 11 further includes an OR gate 17. This receives the 俨 from both the comparator 7 and the second comparator 9 of the 128675.doc 200904011. ..... 叫 有 有 。 。 。 。 。 。 。 。 接收 接收 接收 接收 接收 接收 接收 接收 OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR a sampling control ## causes the switch 13 of the signal sampling and holding system 5 to be temporarily turned off, and A sample of the analog signal is used and stored to capacitor 15. The time at which the sample of the analog signal is used is indicated as 丨, tn+2 " The whip configuration of this embodiment of the invention is based on the analog input signal voltage Sampling, as shown below, will be initialized before starting to use ADC 1. For example, N-bit counter 11 is reset to the initial condition 'to ensure that switch 13 of signal sampling and holding system 5 is off' and capacitor 丨5 Will discharge. An analog signal with a time varying voltage v(t) (which will be converted to a digit 1 er) is applied to the amplifier/subtractor 3. The voltage of the analog signal will initially be zero. When the switch 13 fe/f is on This voltage signal is also not applied to capacitor 15. Amplifier/subtractor 3 therefore receives a zero voltage nick on the labeled + input and a zero voltage signal at the labeled - input. Amplifier / Subtractor 3 subtracting the two signals, amplifying the resulting signal, and outputting a zero voltage signal to each of the comparators 7, 9. The first comparator 7 is received on the input labeled + from the amplifier/subtractor 3 Zero a voltage signal; and receiving a signal Vref at its input labeled _ where Vref = LSBxG, (LSB = least significant bit). The first comparator 7 compares the two signals 'and when the zero voltage signal is not greater than Vref , does not output a digital signal to the N-bit counter 11. The second comparator 9 receives the zero-power signal from the amplifier/subtraction 128675.doc 200904011 on its input of the flag - and is marked with + The input receives a signal -Wef 'where ef=-LSBxG. The second comparator 9 compares the two signals, and when the signal -Vref is not greater than the zero voltage signal, the 16^ digit signal is not output to the N-bit counter. 11. The counter portion of the N-bit s ten-state 11 therefore does not receive signals from the first comparator 7 or the second comparator 9. The uncorrected value of the counter portion (i.e., zero) is output from the ADC 1 as a digital signal D which is equivalent to the zero voltage analog signal input to the amplifier/subtractor 3. An analog signal having a time varying voltage v(t), which is converted to a digital signal, is continuously applied to the amplifier/subtractor 3, and the voltage of this signal will rise from its initial zero value. This voltage signal is also not applied to the capacitor 15 when the switch 13 is still open. The amplifier/subtracter 3 therefore receives the voltage signal v(t) at the input marked + and receives a signal equal to zero at the input of the flag. The amplifier/subtracter 3 subtracts the zero signal from the voltage signal, amplifies the resultant signal by gain G, and outputs the signal to each of the comparators 7, 9. The output signal is therefore (v(t)-0)xG. The first comparator 7 receives the signal (v(t)-0)xG from the amplifier/subtractor 3 at its input labeled + and receives a signal Vref at its input of the flag -, where Vref = LSBxG, (LSB = least significant bit). The first comparator 7 compares the two signals, and if the signal (v(1)_0) XG is greater than Vref, it is a digital signal of the output packet if it is (1)-0)xG>LSBxG or (v(t)-0)>LSB Up to the N-bit counter 11. The first comparison benefit 9 is to receive the k number (v(t)-0)xG from the amplifier/subtraction state 3 on its input of the flag-; and receive a number 128675.doc 200904011 on its wheeling marked + Vref, where -Vref=-LSBxG. The second comparator 9 compares the two signals 'and if the signal -Vref is a large signal (v(1)_〇) xG, that is, if _LSBxG >(v(t)-0)xG, or -LSB>(v( t)-0) 'Output a digital signal containing 1 to the n-bit counter 11. If the voltage of the analog input signal is considered to change from _v to +V, and ADC 1 provides N+1 bit resolution, then i lsb=v/2n. The voltage amplitude of the analog input signal will therefore be greater than! LSB, which is greater than the signal Vref

The amplitude. Therefore, the first comparator 7 (instead of the second comparator 9) will output a signal to the N-bit counter 11. Upon receiving the signal from the first comparator 7, the counter portion of the N-bit counter n is incremented by the value 丨. The value of the counter portion is output from the ADC 1 as a digital signal D(n) which is equivalent to the analog voltage signal input to the amplifier/subtractor 3. The 闸R gate i 7 of the bit counter Π also receives the signal from the first comparator 7. Upon receiving this signal, the OR gate 17 outputs a sample control signal to the signal sample and (4) system 5. This causes the signal sampling and holding system to be temporarily closed by the switch 13 and uses a sample of the voltage signal v(tn) (where 峨 is taken, time) and stored in the capacitor 15. It should be understood that the above procedure may not be faster than the time variation of the analog input signal voltage. Therefore, the amplitude of the signal sampling voltage received by the two capacitors 15 will be equal to the amplitude of the voltage signal input to the amplifier/subtractor 3. Content: 15 The stored voltage signal is input to the rod of the amplifier/subtractor 3. The amplifier/subtracter 3 is marked with the + change voltage analog signal ν(1). Amplifier/Subtractor 3 slave = 128675.doc 10 200904011 The voltage signal is subtracted from the voltage signal received from the capacitor 15, the obtained signal is amplified by the gain G, and this signal is output to each of the comparators 7, 9. The output signal is therefore (v(t)-v( Tn)) xG. The amplifier/subtracter 3 can therefore determine the difference between the voltage of the analog signal at the time of the reception and a previous electrical value of the analog signal. As described above, the first comparator 7 is at the mark + Its input receives the signal from amplifier/subtractor 3 (now (v(t)-v(tn))xG); and receives a signal Vref on its input labeled -, where Vref = LSBxG. Comparator 7 compares the two signals and if The number (yt)_v(tn))xG is greater than Vref, that is, if (v(1)-v(tn))xG>LSBxG or (v(1)-v(tn))>LSB, output a digital signal containing i to N bits Meta-Counter 11. At the same time, as described above, the second comparator 9 receives the signal from the amplifier/subtractor 3 on its input (now (v(t)-v(tn)))); A signal _Vref is received on its input labeled +, where _Vref = _LSBxG. The second comparator 9 compares the two signals, and if the signal _Vref is greater than the signal (v(1)-v(tn)) xG, -LSBxG>(V(t)-v(tn))xG, or -LSB>(v(t)_v(tn))' outputs a digital signal containing 1 to the n-bit counter 11. Therefore, if received The voltage v(t) of the time-varying analog signal is different from the previous voltage value of the analog signal V(tn)+M LSB 'The first or second comparator | 曰 outputs a signal. The ADC 1 can thus detect the analog signal voltage. +Λι LSB change. If the voltage v(t) of the received time-varying analog signal is different from the previous voltage value LS]B of the analog signal, the first or second comparator does not output a signal. If the N-bit counter U receives the a signal of the first comparator 7 , causing the 128675.doc 200904011 counter portion to be a semaphore of the second comparator 9 with a value of 1. As described above, the value of the counter portion is increased from Adc. If the N-bit counter 11 receives the counter, it becomes a counter. The part is decremented by a value of 1 as a digital signal' which is equivalent to the analog voltage signal V(1) input to the amplification 2 a king hole state / subtraction method 3 . r

The 011 gate 17 of the N-bit counter 11 also receives any signal from either the first comparator or the second comparator 9. Upon receiving this signal, the 〇R gate" outputs a sample control signal to the signal sample and hold system 5. This causes the switch 13 of the signal sample and hold system 5 to be temporarily closed and uses a sample of the voltage signal v(tn + 1) And store it in the capacitor Μ. When the conversion time changes the analog signal, its voltage value is completely known. By using D(n)-D(nl)=+/-i LSB, each equivalent digit can be expected. Signal D. The resolution of ADC 1 is given by N = l 〇 g2 (V / LSB) + l = l 〇 g2 (GxV / Vref) + 1. Referring to Figure 2, a second embodiment of the present invention A analog to digital converter (ADC) 20 is included. This is similar to the ADC of Figure i, and the same reference numerals are used to indicate similar components. However, in this embodiment of the present invention, the phantom sample and hold system 2 5 contains a bitwise bit-to-analog conversion is (DAC), where Μ>Ν. This replaces the switches and capacitors of the signal sampling and holding system 5. This benefit is not required to provide a switch in the signal sampling and holding system. Capacitor; therefore, there will be no leakage of the capacitor. Disadvantages 疋 increase the power of the ADC 20 The consumption (Dac stabilization time must be as short as the sampling time of the capacitor) 'and increase the size of the ADC 20. I28675.doc 12- 200904011 Referring to Figure 3, a third embodiment of the present invention includes an analog to digital converter ( ADC) 30. This is similar to ADC 1 of Figure 1 and the same reference numerals are used to indicate similar components. In this embodiment, signal sampling and holding system 35 includes a switch and a signal that can store a current signal. The storage device. The ADC 30 architecture of this embodiment of the invention is based on current sampling of an analog input signal, as shown below. It is initialized before the ADC 30 is used. For example, the N-bit count thief 11 is reset to The initial condition 'to ensure that the signal sampling and holding system 3 5 switch is off' and the current signal storage device is discharged. An analog signal having a time varying current i(t) (which is converted to a digit k) is applied to Amplifier/Subtractor 3. The current of the analog signal will be initialized to zero. When the switch is turned off, this current signal will not be applied to the current signal storage device. Amplified/Subtractor 3 Therefore, a zero current signal is received at the input labeled +; and a zero current signal is received at the input of the flag - the amplifier/subtractor 3 subtracts the two signals, amplifies the resulting signal, and outputs a zero current. Up to each of the comparisons 7, 9. The first comparator 7 receives the zero current 彳§ number from the amplifier "Salt to benefit 3" on its input labeled + and receives a signal on its input labeled _

Iref, which +Iref=LSBxG. The first comparator 7 has two two signals, and does not output a digital signal to the track counter 11 when the zero current signal is not greater than Iref. The second comparator 9 receives the zero current signal from the amplifier/subtractor 3 at its input - and receives it on its input labeled + signal 128675.doc -13 - 200904011 -Iref, where _Iref =_LSB><G. When a brother compares the two signals and compares the two signals and when the signal -1 ref is not greater than Mengdang, * corpse., + current #唬, the digital signal containing 1 is not output to the N-bit counter 1 i. The counter portion of the N-bit counter 11 therefore does not receive a number 5 from the first comparator 7 or the second vehicle. The uncorrected value of the counter portion (i.e., zero) is output from the ADC 30 as a digital signal D which is equivalent to the zero current analog signal input to the amplifier/subtractor 3.

An analog signal having a time varying current i(t), which is converted to a digital signal, is continuously applied to the amplifier/subtractor 3, and the current of this signal will rise from its initial zero value. This current signal is also not applied to the current signal storage device when the switch is still open. The amplifier/subtracter 3 thus receives the current # number i(t) on the input labeled + and receives a signal equal to zero on the input of the flag. The amplifier/subtracter 3 subtracts the zero signal from the current signal, amplifies the resulting signal with gain G, and outputs the signal to each of the comparators 7, 9. The output signal is therefore (i(t) - 〇) xG. The comparator 7 接收 receives the signal (i(t)-0) xG from the amplifier/subtracter 3 at its input labeled + and receives a signal Iref at its input of the flag - Iref = LSBxG. The first comparator 7 compares the two signals, and if the signal (i(t) - 〇) xG is greater than Iref, that is, if (i(1)_0)xG>LSBxG or (i(t)-0)>LSB, the output A digital signal containing 1 is sent to the n-bit counter u. The second comparator 9 receives the signal (i(t)-0)xG from the amplifier/subtractor 3 at its input of the flag - and receives a signal -Iref at its input labeled + - where -Iref= -LSBxG. The second comparator 9 compares the two signals, and if the signal -Iref is greater than the signal (i(1)-0)xG 'is if _LSBxG>(i(1)-0)xG, 128675.doc • 14-200904011 or -LSB> (i(tH)), outputting the digital signal containing 丄 to the n-bit counter. If the current of the analog input signal is considered to vary from q to +1, and adc 3〇 provides N+1 bit resolution, then i LSB =I/2N. The current amplitude of the analog input signal is therefore greater than the W LSB, which is greater than the signal, amplitude. Thus the 'first comparator 7 (instead of the second comparator 9) outputs a _ signal to the Ν bit counter 丨i.

Upon receiving the signal from the first comparator 7, the counter portion of the N-bit counter ^ is incremented by a value}. The value of the count portion is output from 継30 as a digital signal which is equivalent to the analog current signal input to the amplifier/subtracter 3. The 〇R gate N of the N-bit counter 11 also receives the apostrophe from the first comparator 7. Upon receiving this signal, 〇R gate i 7 outputs a sampling control signal to signal sampling and holding system 35. This results in a signal sampling and (iv) system Μ switch temporarily closed, and the current signal is used to receive the sample (where η represents the sampling time), and stored in the current signal storage device ^ should be able to understand that the program is very fast happening' The current time variation faster than the analog input signal The amplitude of the signal sampling current received by the current signal storage device will be equal to the amplitude of the current signal input to the amplifier/subtractor 3. The current signal stored by the current signal storage means is input to the input of the amplifier/subtracter 3. The indication + input of the amplifier/subtracter 3 continues to receive the time varying current analog signal i(1). The amplifier/subtractor 3 subtracts the current signal received from the current signal storage device from the time varying current signal, amplifies the resultant signal with the gain G, and outputs the signal to the comparators 7, 9 of I28675.doc -15-200904011 By. The output apostrophe is therefore (i(t)-i(tn))xG. The amplifier/subtracter 3 thus determines the difference between the current i(t) of the analog signal of the reception time variation and the previous current value of the analog signal. As before, the first comparator 7 receives the signal from the amplifier/subtractor 3 on its input labeled + (now ^(1) - ^^广(7); and receives a signal lref on its input labeled "," Iref=LSBxG. The first comparator 7 compares the two signals, and if the signal (Kt)_i(tn))xG is greater than Iref, it is right Ο(1)-i(tn))xG>LSBxG or (i (1) _i (tn)) > LSB , outputting a digital signal containing ! to the N-bit counter 11. Meanwhile, as previously described, the second comparator 9 receives the signal from the amplification/subtractor 3 on its input of the indication ( It is now (丨(1)_i(tn))xG); and receives a signal ef on its input labeled +, where _Iref=_LSBxG. The first comparator 9 compares the two signals and if the signal _Iref is greater than The signal (Kt)-i(tn))xG, that is, if -LSBxG>(i(t)-i(tn))xG, or -LSB>(i(t)-i(tn)), the output contains 1 The digital signal is sent to the N-bit counter 11. Therefore, if the current i(t) of the received time-varying analog signal is different from the previous current value i(tn)+/] LSB of the analog signal, the first or second comparator will output One #唬. ADC 30 will detect the connection The LSB change of the analog signal current. If the current i(t) of the analog time change analog signal is different from the previous current value i(tn) +/-: i LSB of the analog signal, the first or second comparator does not output a signal. If the N-bit counter 11 receives a signal from the first comparator 7, causing the counter portion to increment by a value of 1. If the N-bit counter 丨丨 receives a signal from the second comparator 9, the counter portion is caused. The value is decremented by the value 128 128,675.doc 200904011 As the foregoing, the value of the counter section is output from the ADC 3〇 as a digital signal, and (4) is the Bobe-like current signal i(1) input to the amplifier/subtractor 3. N-bit counter The OR gate i 7 of 11 also receives any signal from the first comparator 7 or the second comparator 9. Upon receiving this signal, the 〇R gate singly outputs a sample control signal to the signal sample and hold system 35. This causes the switch of the signal sampling and holding system 35 to be temporarily closed, and the sample of the current signal Ktn+1) is used and stored in the current signal storage device.

When the conversion time changes the analog signal, its current value is completely known. By using D(n) - D(n - 1) = +/- 1 LSB, each equivalent digit signal D can be expected. The resolution of the ADC 30 is given by N = l 〇 g2 (I / LSB) + l = l 〇 g2 (GxI / Iref) + l. Referring to Figure 4, a fourth embodiment of the present invention includes an analog to digital converter (ADC) 40. This is similar to ADC 30 of Figure 3, and like reference numerals are used to indicate like components. However, in this embodiment of the invention, the 5-sample and hold system 45 includes a bit-to-bit analog to analog converter (DAC), where > This replaces the switch and current signal storage of the signal sampling and holding system 35. This benefit is that there is no need to provide a switch and current signal storage device in the signal sampling and holding system so that the current signal storage device does not leak. The disadvantage is to increase the power consumption of the ADC 40 and increase the size of the ADC 40. The ADC embodiment of the present invention converts time varying analog input signals. A constant analog input signal can be achieved by converting these signals into a time varying input signal. 128675.doc 17 200904011 The operation of each embodiment of the ADC of the present invention is quite different from the conventional adc. Of these, time sampling is used to sample analog input signals, and this requires the use of a clock. In an embodiment of the ADC of the present invention, voltage or current sampling is used to sample the analog signal of the input ADC, and this does not require the use of a clock. This provides the desired power consumption improvement. The ADC embodiment of the present invention provides many advantages over the conventional adc. The specific embodiment of the ADC has reduced power consumption compared to the power consumption of conventional ADCs. This is due to the fact that the ADC has no clock and subsequently reduces power consumption. The ADC of the present invention achieves increased resolution by digital post-processing of the conversion signal achievable by the voltage or current sampling structure of the ADC. The ADC of the present invention further provides for reducing the conversion time of the input signal. Any voltage or current change that does not have a clock system and automatically monitors the input signal will reduce the on-wafer design of the ADC of the present invention, optimize the ADC size, and reduce design cycle time. This reduces the cost of the ADC. The ADC further provides flexibility' in that each ADC can be easily extended to medium/high resolution and/or high speed. The ADC embodiment of the present invention is suitable for use in any application requiring signal conversion, particularly with respect to π low resource environments, ie, for example, power and allowed ADC regions are lower resource availability, and need to increase conversion speed and reduce Application of resolution. The ADC of the present invention can be implemented, for example, in a portable device, such as a cellular phone, a laptop and heart device, an instrument/measurement application, an audio and video application such as an audio data converter, a car Applications, medical applications, etc.

Referring to the portable device application discussed in the introduction, the ADC 128675.doc 200904011 of the present invention is particularly useful in monitoring the application of the battery voltage of a device. The unused clock of the ADC reduces the power consumption of the ADC; therefore, monitoring the battery voltage can be achieved during the mode of operation of the device with reduced power consumption. Monitoring the battery voltage can also be achieved during the device's standby mode, without the need for a clock, while also reducing power consumption. These help to optimize the power supply of the device. However, if the voltage of the device's power source (e.g., battery) remains odd for a long time, an erroneous analog to digital conversion may occur if any particular embodiment of the ADc detects an i LSB analog signal drop. This may result in an error that causes a 1 LSB signal offset due to the signal sampling of the ADC of Figure 3 or 3 and the house/current leakage of the signal storage device of the system (4). This may result in a continuous increase in the output digital signal. Using a low frequency clock that is always available, this problem can be solved by periodically reinitializing the ADC. Adc will use ^ up to approximately 1 〇叩 time to output the correct digital signal, and the free running period of the ADC should be the worst, for example. Because the original low-frequency clock system /, with a new purpose, its use does not significantly increase AD. Power consumption or size. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic representation of an analog-to-digital converter according to a first embodiment of the present invention provided by way of example; FIG. 2 is provided by way of example A schematic representation of an analog-to-digital conversion H according to a second embodiment of the present invention; FIG. 3 is a comparison of a third embodiment 128678.doc _ 19· 200904011 according to the present invention provided by way of example to A schematic representation of a digital converter; FIG. 4 is a schematic representation of an analog to digital converter in accordance with a fourth embodiment of the present invention provided by way of example. [Main component symbol description] 1 analog to digital converter 3 amplifier/subtractor 5 signal sampling and holding system 7 f 9 first comparator second comparator 11 N bit counter 13 switch 15 signal storage device 17 0 R gate 20, 30, .40 analog to digital converter 25, 35, 45 signal sampling and holding system 128675.doc 20-

Claims (1)

200904011 X. Patent application scope: 1.—Type to digital converter (ADC) (1, 20 ' 30, 40) It is characterized in that the analog to digital converter includes a sampling device (5, 25, 35, 45) a signal comparison device (3) and a digital signal generator (7, 9, 11), wherein an analog signal to be converted into a digital signal is input to the ADC, and the signal sampling device generates a sample of the analog signal, The signal comparison device receives the analog signal and the analog signal samples, performs a comparison therebetween and outputs a comparison signal, and the digital signal generator receives a comparison signal such as shai and uses it to generate a digital signal. 2. The ADC of claim 1, wherein the signal comparison means (3) compares the difference between the analog signal and the previously used sample of the analog signal to compare the analog signal with the analog signal. sample. 3. The ADC of claim 2, wherein the digital signal generator (7, 9, u) receives a comparison signal comprising a difference between the analog signal and the prior employed sample of the analog signal' and if The comparison signal exceeds a predetermined threshold to generate a digital signal. 4. The ADC of claim 1 wherein the digital signal generator comprises a first comparator (7), a second comparator (9) and an N-bit counter (11), first and second comparators The comparison signals are received to determine whether the comparison signal exceeds the predetermined threshold 'and if so, a signal is output to the N-bit counter of the generation-digit signal, and the signal sampling means produces an analog signal sample. 5. The ADC of any of the preceding claims wherein the signal sampling means (5, 25) produces a voltage sample of the analog signal. 128675.doc 200904011 6. The ADC of claim 5, wherein the signal sampling device (5) includes a switch that is periodically disconnected to receive the analog signal and to generate a voltage analog signal sample. 7. The ADC of claim 6, wherein the signal sampling device (5) further comprises a k唬 storage device that stores the voltage analog signal samples and outputs the same to the signal comparison device (3). 8. The ADC of claim 5, wherein the signal sampling means comprises a digital to analog converter that receives a digital signal equivalent to the analog signal and converts the digital signal into a voltage analog signal sample. 9. The ADC of any of claims 1 to 4, wherein the signal sampling means (35, 45) is a current sample that produces the analog signal. 10. The ADC of claim 9, wherein the signal sampling device (35) includes a switch that is periodically disconnected to receive the analog signal and to generate a current analog signal sample. U. The ADC of claim 10, wherein the signal sampling means (35) further comprises a storage device for storing the current analog signal samples and outputting the signals to the signal comparison means (3). 12. The ADC of claim 9, wherein the signal sampling means comprises a digital pair analog converter 'which receives a digital signal equivalent to the analog signal' and converts the digital signal into a current analog signal sample. 13. If you ask for it! The operation of the signal sampling means (5, 25, 35, 45) for generating an analog signal sample is controlled by the digital signal generator, any of 2, 3 and 4. A method of converting an analog signal into a digital signal, characterized by 128675.doc 200904011, which includes generating a sample of the analog signal, performing a comparison between the analog signal and the analog signal samples to generate a comparison signal, and using The comparison signals are used to generate a digital signal. / 128675.doc