JP6677563B2 - ΔΣ A / D converter, A / D converter integrated circuit - Google Patents

Description

  The present invention relates to a ΔΣ A / D converter.

A ΔΣ A / D converter is used for measuring a small signal requiring a high resolution or for audio applications. FIG. 1 is a block diagram showing a basic configuration of a primary ΔΣ A / D converter. Delta-Sigma A / D converter 100r converts an analog input signal _{V IN} to a digital output signal _{D OUT.} The ΔΣ A / D converter 100r includes a subtractor 102, an integrator 104, a quantizer 106, and a D / A converter 108. The D / A converter 108 delays the digital output signal D _OUT by one sample and converts the digital output signal D _OUT into an analog feedback signal V _FB . The subtractor 102 generates a difference between the analog input signal _VIN and the feedback signal _VFB . The integrator 104 integrates the difference output from the subtractor 102. The quantizer 106 quantizes the output of the integrator 104 and generates a digital output signal D _OUT .

  By using the ΔΣ A / D converter, the noise spectrum caused by the quantization error can be moved out of the band of the input signal. This is called noise shaping.

JP 2011-150561 A JP 2014-171035 A

  The present inventors have studied the ΔΣ A / D converter, and have come to recognize the following problem. In a first-order, particularly second-order or higher ΔΣ A / D converter, the integrator 104 is often formed of a switched capacitor circuit.

If the ΔΣ A / D converter is completely broken and becomes inoperable, the digital output signal D _OUT has no correlation with the analog input signal _VIN . In this case, it is possible to recognize an abnormality in a subsequent processor or circuit using the output signal D _OUT of the ΔΣ A / D converter.

However, an incomplete failure may occur in the ΔΣ A / D converter. Incomplete failure refers to a failure mode in which some abnormality has occurred, but the ΔΣ A / D converter is operating at first glance, and some inaccurate output signal D _OUT is generated. If incomplete failure occurs, subsequent processor or circuit, since the operate based on erroneous output signal D _OUT, causes the system to malfunction.

  The present inventor has been made in view of such a problem, and one of exemplary purposes of an embodiment thereof is to provide a ΔA / D converter with improved reliability.

  One embodiment of the present invention relates to a ΔΣ A / D converter that converts an analog input signal into a digital output signal. The ΔΣ A / D converter includes at least one integration circuit configured by a switched capacitor circuit, and a leak detection circuit that detects leakage of at least one capacitor of the integration circuit.

  The inventor has recognized that capacitor leakage in a switched capacitor circuit is one cause of the incomplete failure mode of a ΔΣ A / D converter. According to this aspect, the ΔΣ A / D converter can detect an incomplete failure that cannot be detected in a subsequent processor or circuit by performing self-diagnosis of a capacitor leak, thereby improving reliability.

The leak detection circuit may open the capacitor after charging the capacitor to be leak-detected, and measure the voltage of the capacitor.
If the leak is not present or is small enough, the voltage on the capacitor will continue to maintain the original voltage level after the capacitor is opened. On the other hand, if there is a leak, the charge of the capacitor is discharged by the leak current, and the voltage is reduced. Therefore, by measuring the voltage of the capacitor, the presence or absence of the leak or the degree of the leak can be measured.

  The leak detection circuit may measure a relaxation time until the voltage of the capacitor crosses a predetermined threshold voltage after the capacitor to be leak-detected is opened. By measuring the relaxation time, the presence or absence of the leak or the degree of the leak can be measured.

  Alternatively, the leak detection circuit may measure the voltage of the capacitor after a predetermined time has elapsed after the capacitor to be leak-detected has been opened. The amount of change in the voltage of the capacitor occurring during the predetermined time indicates the presence or absence of the leak or the degree of the leak.

  At least one capacitor may include a capacitor having the largest capacitance value among a plurality of capacitors forming the integration circuit. The larger the capacitance value, that is, the larger the area, the easier it is to detect a leak.

  The ΔΣ A / D converter may be of secondary or higher order. The at least one capacitor may include a capacitor of a first stage integrator. Since the capacitance value of the capacitor of the first-stage integrator is often the largest, leak detection is easy.

  The leak detection circuit includes a first switch provided between one end of a capacitor to be detected and a first fixed voltage line, and a second switch provided between the other end of the capacitor and a second fixed voltage line. And a comparator for comparing the voltage of the capacitor with a threshold voltage.

  The comparator of the leak detection circuit may be shared with the comparator of the quantizer of the ΔΣ A / D converter. Thereby, an increase in the circuit area can be suppressed.

  The ΔΣ A / D converter may be a differential type. The leak detection circuit may detect the leak of each of the capacitor provided on the positive phase side and the capacitor provided on the negative phase side of the differential.

  The ΔΣ A / D converter may be integrated on one semiconductor substrate.

  Another embodiment of the present invention relates to an A / D converter integrated circuit. The A / D converter integrated circuit includes a plurality of input terminals to each of which an analog input signal can be input, a multiplexer for selecting one of the plurality of input terminals, an amplifier for amplifying an output signal of the multiplexer, and an output of the amplifier. A filter for filtering a signal and any one of the above-mentioned ΔΣ A / D converters for converting an output signal of the filter into a digital signal may be provided.

  It is to be noted that any combination of the above-described components and any conversion of the expression of the present invention between a method, an apparatus, and the like are also effective as embodiments of the present invention.

  According to the ΔΣ A / D converter according to the present invention, the reliability can be improved.

FIG. 2 is a block diagram illustrating a basic configuration of a first-order ΔΣ A / D converter. FIG. 2 is a circuit diagram of a ΔΣ A / D converter according to the embodiment. FIG. 3 is a circuit diagram illustrating a configuration example of a leak detection circuit. FIGS. 4A and 4B are operation waveform diagrams of the leak detection circuit of FIG. FIG. 3 is a circuit diagram illustrating a specific configuration example of a ΔΣ A / D converter. It is a circuit diagram which shows a part of integration unit of a differential type. FIG. 2 is a block diagram of an A / D converter IC including a ΔΣ A / D converter.

  Hereinafter, the present invention will be described based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in each drawing are denoted by the same reference numerals, and the repeated description will be omitted as appropriate. In addition, the embodiments do not limit the invention, but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  FIG. 2 is a circuit diagram of the ΔΣ A / D converter 200 according to the embodiment. The ΔΣ A / D converter 200 includes a subtractor 202, an integration circuit (integration filter) 204, a quantizer 206, a D / A converter 208, and a leak detection circuit 230. The ΔΣ A / D converter 200 is integrated on one semiconductor substrate.

The D / A converter 208 delays the digital output signal D _OUT by one sample and converts the digital output signal D _OUT into an analog feedback signal V _FB . The subtracter 202 generates a difference between the analog input signal _VIN and the feedback signal _VFB . The integration circuit 204 integrates the difference output from the subtractor 102. The quantizer 206 quantizes the output of the integration circuit 204 and generates a digital output signal D _OUT .

  The ΔΣ A / D converter 200 of FIG. 2 is a third-order ΔΣ A / D converter, and the integration circuit 204 includes three-stage integration units 210, 212, and 214. Each integration unit multiplies the signal from the preceding stage by a predetermined coefficient and integrates the signal. In the present invention, the topology of the integration circuit 204 and the value of the coefficient are not limited, and may be designed so as to obtain desired filter characteristics.

  The configuration of the quantizer 206 is not particularly limited. For example, multipliers 240, 242, 244 for multiplying the outputs of the integration units 210, 212, 214 by predetermined coefficients a1, a2, a3, and multipliers 240, 242, An adder 246 for adding the output of the adder 244 and a comparator (comparing circuit) 250 for quantizing the output of the adder 246 are included.

  The integration circuit 204 is configured by a switched capacitor circuit. The leak detection circuit 230 detects a leak of at least one of a plurality of capacitors included in the integration circuit 204.

  The method and circuit configuration of the leak detection are not particularly limited, but may be detected as follows. After charging the capacitor to be leak-detected, the leak detection circuit 230 opens the capacitor and measures the voltage of the capacitor.

  The above is the configuration of the ΔΣ A / D converter 200. According to the ΔΣ A / D converter 200, a self-diagnosis of the leakage of the capacitor of the switched capacitor circuit can be performed, whereby an incomplete failure that cannot be detected in a subsequent processor or circuit can be detected. Therefore, the reliability and safety of the ΔΣ A / D converter 200 itself or a system using the same can be improved.

  For example, ΔΣ A / D converter 200 may notify an external circuit when leak detection circuit 230 detects a leak. Alternatively, the ΔΣ A / D converter 200 may transmit a signal indicating the degree of leakage to an external circuit. Alternatively, data indicating the degree of leakage may be accessible from an external circuit.

  The present invention covers various devices and circuits that can be grasped as the block diagram or circuit diagram of FIG. 2 or derived from the above description, and is not limited to a specific configuration. Hereinafter, more specific configuration examples and embodiments will be described, not to narrow the scope of the present invention, but to help understand the essence and circuit operation of the invention and to clarify them.

FIG. 3 is a circuit diagram showing a configuration example of the leak detection circuit 230. The first switch SW11 is provided between one end of the capacitor Cx whose leakage is to be detected and a first fixed voltage line (for example, a power supply line or a reference voltage line) 260. The second switch SW12 is provided between the other end of the capacitor Cx and a second fixed voltage line (for example, a ground line or a common voltage line) 262. Comparator 232 compares voltage V _{CX of} capacitor Cx with threshold voltage V _TH . A third switch SW13 is provided between the comparator 232 and the other end of the capacitor Cx. The threshold voltage V _TH may be generated by the voltage division of the resistors R11 and R12, and a fourth switch SW14 is provided between the output of the resistor voltage dividing circuit and the comparator 232.

  Note that the comparator 232 may be shared with a part of the comparator 248 of the quantizer 206 of the ΔΣ A / D converter 200. Thereby, an increase in the circuit area can be suppressed. Some of the switches of the leak detection circuit 230 may be shared with the switches of the integration circuit 204.

4A and 4B are operation waveform diagrams of the leak detection circuit 230 in FIG. The leak detection circuit 230 turns on the first switch SW11 and the second switch SW12, and charges the both ends of the capacitor Cx with the voltage _VDD . Subsequently, the second switch SW12 is turned off, and the third switch SW13 and the fourth switch SW14 are turned on. When the second switch SW12 is turned off, the capacitor Cx is opened. Comparator 232 compares voltage V _{CX of} capacitor Cx with threshold voltage V _TH . If no leakage occurs, as shown by the solid line (i), the voltage ΔV between both ends of the capacitor Cx maintains the initial power supply voltage V _DD , so that the voltage V _CX of the capacitor becomes the initial ground voltage 0V. To maintain.

On the other hand, when a leak occurs, the capacitor Cx is discharged as shown by the broken line (ii), so that the voltage ΔV between both ends of the capacitor Cx decreases, and the voltage V _CX of the capacitor becomes the initial ground. It rises with time from the voltage 0V.

As shown in FIG. 4B, the leak detection circuit 230 measures the relaxation time τ until the voltage V _{CX of the} capacitor Cx crosses the predetermined threshold voltage V _TH after the capacitor Cx is opened. Good. If there is no leak, the relaxation time τ is sufficiently long, and if there is a leak, the relaxation time τ becomes short. Therefore, by measuring the relaxation time τ, the presence or absence of the leak or the degree of the leak can be measured.

  The leak detection circuit 230 may include a counter (timer) 234 that measures a time τ from when the second switch SW12 is turned off to when the output of the comparator 232 changes. The leak detection circuit 230 may store data indicating the measured relaxation time τ in a register as data indicating the degree of leak. Alternatively, the leak detection circuit 230 may set a flag indicating the occurrence of a leak failure when the measured relaxation time τ is shorter than a predetermined threshold.

Alternatively leak detection circuit 230, after the lapse of a predetermined time after the opening of the capacitor Cx of the leak detection target may be measured voltage V _CX of the capacitor Cx. The fluctuation amount of the voltage _VCX occurring during the predetermined time indicates the presence or absence of the leak or the degree of the leak.

In FIG. 2, the leakage is measured based on the power supply voltage V _DD , but may be measured based on the ground voltage. That is, after charging the capacitor Cx, the first switch SW11 may be turned off, and the voltage at the upper end of the capacitor Cx may be monitored.

  FIG. 5 is a circuit diagram showing a specific configuration example of the ΔΣ A / D converter 200. Although shown here as a single-ended type, the ΔΣ A / D converter 200 may be a differential type.

  It is desirable that the leak detection circuit 230 monitors a capacitor having the largest capacitance value among a plurality of capacitors included in the integration circuit 204. This is because the larger the capacitance value, that is, the larger the area, the easier the leak detection becomes. Further, the larger the capacitance value, the greater the influence on the performance of the ΔΣ A / D converter 200 when a leak occurs.

  In the configuration of FIG. 5, the feedback capacitor 272 of the integrator 270 of the first-stage integration unit 210 is suitable as a leak detection target. This is because in order to suppress the noise of the ΔΣ A / D converter 200, it is effective to increase the feedback capacitor 272 of the integrator 270 in the first stage. Also, the voltage applied during the operation is the largest in the feedback capacitor 272 in the first stage, so that it is easily affected by the leak.

  This is because the capacitance of the feedback capacitor 272 is the largest as compared with other capacitors. Note that, in addition to the feedback capacitor 272, the feedback capacitors 276 of the integrators 274 in the second and subsequent stages may be subjected to leak detection. Alternatively, the capacitor 280 forming the equivalent resistance (or the sample-and-hold circuit) 278 may be a leak detection target.

  FIG. 6 is a circuit diagram showing a part of the integration unit 210 of the differential type. It is desirable that the leak detection circuit 230 detects leaks of the feedback capacitor CP provided on the positive phase side of the differential and the feedback capacitor CN provided on the negative phase side.

  FIG. 7 is a block diagram of an A / D converter IC (integrated circuit) 300 including the ΔΣ A / D converter 200. Each of the plurality of input terminals IN1 to INM (M is an integer) can receive an analog input signal from the outside. For example, a temperature detection signal from a temperature sensor such as a thermistor or a thermocouple, a current detection signal corresponding to a voltage drop of a sense resistor for current detection, a signal indicating a battery voltage, and the like are input to the input terminal IN.

The multiplexer 302 selects one of the plurality of input terminals. The amplifier 304 is a programmable gain amplifier (PGA) that amplifies the output signal of the multiplexer 302. The filter 306 filters the output signal of the amplifier 304. Delta-Sigma A / D converter 308 converts the output signal _{V IN} of the filter 306 into a digital signal _{D OUT.} The ΔΣ A / D converter 308 is configured using the architecture of the ΔΣ A / D converter 200 described above. Logic circuit 310 performs a predetermined signal processing on digital signal DOUT from ΔΣ A / D converter 308. The interface circuit 312 is an SPI (Serial Peripheral Interface) or I ² C (Inter IC) interface, and is connected to an external processor or microcontroller. An output signal D _OUT of the ΔΣ A / D converter 308 and a signal obtained by processing the output signal D _OUT can be read from an external circuit via the interface circuit 312. Further, the presence or absence of the leak detected by the leak detection circuit 230 of the ΔΣ A / D converter 308 (200) or the degree of the leak can be read from the outside via the interface circuit 312.

  Although the present invention has been described based on the embodiment, the embodiment merely shows the principle and application of the present invention, and the embodiment includes the idea of the present invention defined in the claims. Many modifications and changes in arrangement are possible without departing from the scope of the invention.

100: ΔΣ A / D converter, 102: subtractor, 104: integrator, 106: quantizer, 108: D / A converter, 200: ΔΣ A / D converter, 202: subtractor, 204: integrating circuit, 206: quantum 208, a D / A converter, 210, an integration unit, 230, a leak detection circuit, 232, a comparator, SW11, a first switch, SW12, a second switch, SW13, a third switch, SW14, a fourth switch, and R11. .., First resistor, R12, second resistor, 300, A / D converter IC, 302, multiplexer, 304, amplifier, 306, filter, 308, ΔΣ A / D converter, 310, logic circuit, 312, interface circuit.

Claims (9)

A ΔΣ A / D converter for converting an analog input signal into a digital output signal,
An integration circuit composed of a switched capacitor circuit;
A leak detection circuit for detecting a leak of at least one capacitor of the integration circuit;
Equipped with a,
The leakage detection circuit, the capacitor opening after charging the leak detection target of the capacitor, voltage of the capacitor and measuring the relaxation time to cross a predetermined threshold voltage delta .SIGMA.A / D converter. 2. The ΔΣ A / D converter according to claim 1 , wherein the at least one capacitor includes a capacitor having a largest capacitance value among a plurality of capacitors forming the integration circuit. 3. The ΔΣ A / D converter is of second order or higher;
It said at least one capacitor, Delta-Sigma A / D converter according to claim 1 or 2, characterized in that it comprises a first stage integrator capacitor. The leak detection circuit includes:
A first switch provided between one end of the capacitor to be leak-detected and the first fixed voltage line;
A second switch provided between the other end of the capacitor and a second fixed voltage line;
A comparator for comparing the voltage of the capacitor with the threshold voltage;
The ΔΣ A / D converter according to claim 1 , further comprising: The ΔΣ A / D converter according to claim 4 , wherein a comparator of the leak detection circuit is shared with a comparator of a quantizer of the ΔΣ A / D converter. The ΔΣ A / D converter according to any one of claims 1 to 4 , wherein the ΔΣ A / D converter is a differential type. The ΔΣA according to any one of claims 1 to 5 , wherein the leak detection circuit detects a leak of each of a capacitor provided on a positive phase side and a capacitor provided on a negative phase side of the differential. / D converter. Delta-Sigma A / D converter according to any one of claims 1 to 6 in which a single semiconductor substrate characterized in that it is monolithically integrated. A plurality of input terminals to each of which an analog input signal can be input,
A multiplexer for selecting one of the plurality of input terminals;
An amplifier for amplifying an output signal of the multiplexer;
A filter for filtering an output signal of the amplifier,
A ΔΣ A / D converter according to any one of claims 1 to 7 , which converts an output signal of the filter into a digital signal.
An A / D converter integrated circuit, comprising:

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