JP2014119273A - Abnormality sign determination circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an abnormality sign determination circuit that can monitor a sign of a leakage current abnormality of a capacity element in a more appropriate period during an actual use in a market.SOLUTION: While a user is actually using a semiconductor integrated circuit device 100, a resistor Ra within the semiconductor integrated circuit device 100 always detects leakage current of capacitors C1 to C3. If a short-circuit abnormality, for example, occurs in at least one of the capacitors C1 to C3, the leakage current of the capacitor causing the abnormality increases and therefore current flowing through the resistor Ra also increases. Then, the terminal voltage of the resistor Ra increases and therefore a comparator 8 outputs an abnormality detection signal.

Description

  The present invention relates to an abnormality sign determination circuit for determining an abnormality sign of a capacitive element.

  This type of technology is disclosed in Patent Document 1. According to the technique described in Patent Document 1, a plurality of capacitors are connected in parallel to one power source, a voltage is applied to each capacitor, and a leakage current after a predetermined time is measured. At this time, the variable input resistance circuit is connected in series to each capacitor, and the resistance value of the resistance of the variable input resistance circuit is increased after a certain time shorter than a predetermined time after the voltage is applied.

Japanese Patent Laid-Open No. 09-243893

  However, the technique described in Patent Document 1 shows a technique for monitoring a leak state after a predetermined time, and the presence or absence of abnormality can be detected only by a leak current after a predetermined time. In addition, since the technique described in Patent Document 1 is a technique for inspecting a leakage current, it is not a technique for measuring the leakage current when a user such as a user actually uses a circuit. No consideration has been given to this point.

  An object of the present invention is to provide an abnormality symptom determination circuit capable of monitoring a sign of leakage current abnormality of a capacitive element during a more appropriate period during actual use in the market.

  According to the first aspect of the present invention, the current detection circuit detects the leakage current of the node where the steady target value of the energization current flowing to the constant potential node (GND) through the capacitive element provided in the abnormality detection target circuit is zero. For this reason, if an abnormality occurs in the capacitive element, the leakage current increases, so that the current detection circuit can detect the leakage current. Since the determination circuit determines a sign of abnormality of the capacitive element according to the detection result of the current detection circuit, the sign of leakage current abnormality can be monitored.

  Note that “the steady target value of the energization current is zero” means that a current value on the order of zero that is so small that it can be ignored compared to the leak current value that the steady value of the energization current is assumed to flow in an abnormal state is steady. Note that it means flowing in a state, not strictly “0A”.

  According to the invention described in claim 2, the invalidation circuit invalidates the operation of the current detection circuit by short-circuiting the resistor after the first predetermined time has elapsed after the power is turned on, and the determination circuit is invalidated by the invalidation circuit. Whether or not there is a sign of an abnormality of the capacitance element is determined according to the detection result of the current detection circuit before the detection. Therefore, a sign of leakage current abnormality can be monitored during a more appropriate period, and the abnormality detection target circuit can operate without being affected by the resistance of the current detection circuit after the first predetermined time has elapsed.

  According to the third aspect of the present invention, the validation circuit opens the current detection circuit by opening between the terminals of the resistor before the first predetermined time after the second predetermined time excluding the power supply transient fluctuation period after the power is turned on. The determination circuit determines whether or not there is a sign of abnormality of the capacitance element according to the detection result of the current detection circuit after being enabled by the enabling circuit. Then, the signs of leakage current abnormality can be monitored during the period excluding the power supply transient fluctuation period after the power is turned on, can be detected more accurately, and the signs of leakage current abnormality can be monitored during a more appropriate period. .

  According to the fourth aspect of the present invention, when the determination circuit determines that there is a sign of abnormality during actual use of the abnormality detection target circuit, the switching circuit operates the abnormality countermeasure circuit. Even if this sign is generated, the function of the abnormality detection target circuit can be maintained by the abnormality handling circuit, and the circuit can continue to operate normally.

1 is a circuit configuration diagram schematically showing a first embodiment of the present invention. A diagram showing the current when the capacitor is short-circuited and the output of the judgment circuit FIG. 1 equivalent view showing a second embodiment of the present invention Timing chart showing the operation when there is no abnormality Timing chart showing operation when there is an abnormality Timing chart showing the operation of the third embodiment of the present invention FIG. 1 equivalent view showing a fourth embodiment of the present invention FIG. 1 equivalent view showing a fifth embodiment of the present invention Timing chart showing operation FIG. 1 equivalent view showing a sixth embodiment of the present invention FIG. 1 equivalent view showing a seventh embodiment of the present invention Timing chart showing operation of triangular wave generator FIG. 1 equivalent view showing an eighth embodiment of the present invention

  Hereinafter, some embodiments according to the present invention will be described. Components that are the same or similar in the embodiments are denoted by the same or similar reference numerals, description thereof will be omitted as necessary, and description will be made focusing on the characteristic portions of the embodiments.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 shows details of a detection circuit for detecting a leakage current of n capacitors (n is a natural number).

  In the semiconductor integrated circuit device 100, two ground electrode pads G1, G2 are provided apart from each other. The ground electrode pads G1 and G2 are bonded to the ground inner leads LG by wires W1 and W2, respectively. In the semiconductor integrated circuit device 100, an abnormality detection electrode pad O1 is provided separately from the ground electrode pads G1 and G2. The abnormality detection electrode pad O1 and the abnormality detection inner lead LH are bonded by a wire W3.

  An abnormality sign determination circuit 1 is configured in the chip of the semiconductor integrated circuit device 100. The abnormality sign determination circuit 1 is a circuit for determining an abnormality sign of each of the capacitors C1 to C3 (corresponding to an abnormality detection target circuit) connected to the power supply circuit 2, the reference voltage generation circuit 3, and the like. . The abnormality sign determination circuit 1, the power supply circuit 2, the reference voltage generation circuit 3, and the capacitors C1 to C3 are all configured in the semiconductor integrated circuit device 100.

  The power supply circuit 2 inputs the power supply voltage Vdd, for example, via a backflow prevention diode (not shown) or the like, and supplies power to the power supply target circuit 4. The power supply circuit 2 includes a bias generation circuit 5, a capacitor C1, and a power supply NPN transistor Tr1, and supplies power to the power supply target circuit 4 through the transistor Tr1.

  The bias generation circuit 5 is configured by connecting a current source 6 and one or a plurality of diodes D1 in series between a supply terminal of a power supply voltage Vdd and a ground electrode pad G2. Normally, when the power supply voltage Vdd is supplied, the bias generation circuit 5 applies a constant bias generated by the diode D1 to the base of the transistor Tr1. The transistor Tr1 supplies power corresponding to the bias to the power supply target circuit 4.

  The power supply target circuit 4 is connected between the emitter of the transistor Tr1 and the ground electrode pad G2. When power is input from the power supply voltage Vdd through the transistor Tr1 in accordance with a constant bias generated by the bias generation circuit 5, a predetermined operation is performed. I do. The detailed description of the power supply target circuit 4 is omitted because it is not related to the characteristics of the present embodiment.

  A capacitor C1 is connected between the base of the transistor Tr1 and the intermediate node N1. The capacitor C1 is provided to remove noise generated at the base of the transistor Tr1. The capacitor C1 is configured using a capacitor incorporated in the semiconductor integrated circuit device 100, and is set to about several [pF] to several tens [pF].

  On the other hand, the reference voltage generation circuit 3 receives the power supply voltage Vdd and generates a plurality of (for example, two) DC reference voltages. A plurality (three or more) of resistors R1 to R3 are connected in series between the supply terminal of the power supply voltage Vdd and the ground electrode pad G2, and analog switches SW1 and SW2 are connected to the common connection nodes N2 and N3 adjacent to each other. Are connected to each other. These analog switches SW1 and SW2 output voltages at nodes N2 and N3, respectively, when an output on control signal is given from the control circuit 7.

  Capacitors C2 and C3 are connected between the nodes N2 and N3 and the intermediate node N1, respectively. These capacitors C2 and C3 constitute a filter circuit for suppressing transient voltage fluctuation noise generated when the analog switches SW1 and SW2 are switched.

  A resistor Ra is connected between the intermediate node N1 and the ground electrode pad G1. The resistor Ra is a resistor electrically connected between the intermediate node N1 where the steady target potential becomes the ground potential and the ground electrode pad G1, and is set to about several [kΩ]. The resistor Ra is connected between nodes (between the intermediate node N1 and the ground electrode pad G1) where the energization current becomes zero during the steady operation.

  In the present embodiment, the intermediate node N1 serves as a potential reference node for the voltage stabilizing capacitor C1 of the bias generation circuit 5 and also serves as a potential reference node for the capacitors C2 and C3. The same potential as G1 (≈0). Therefore, almost no current flows through the resistor Ra during steady operation.

  The reason why the resistor Ra is provided is to detect the leakage currents of the capacitors C1 to C3. A comparator 8 is connected between the terminals of the resistor Ra. The comparator 8 is, for example, a comparator having a DC offset characteristic. When a current exceeding a predetermined value (for example, about several [μA]) flows through the resistor Ra, the abnormality detection electrode pad O1 corresponds to an increase in the terminal voltage of the resistor Ra. Is configured to output an abnormality detection signal “H”.

  A method of using the above circuit will be described. The manufacturer (inspector) detects the current flowing in the resistor Ra with respect to the leakage current of the capacitors C1 to C3 connected to the power supply circuit 2 and the reference voltage generation circuit 3, so that the capacitors C1 to C3 have predetermined insulation. The semiconductor integrated circuit device 100 is shipped to the market after checking whether or not the performance is exhibited and confirming that the leakage current is below the allowable amount.

  After the semiconductor integrated circuit device 100 is sold from the manufacturer to the user, the user uses the semiconductor integrated circuit device 100. When the user uses the semiconductor integrated circuit device 100, while the capacitors C1 to C3 are functioning normally, each of the capacitors C1 to C3 cuts a direct current, so that the current passes through the capacitors C1 to C3 and the ground electrode pad G1. Does not flow to the side. Therefore, the terminal voltage of the resistor Ra does not increase, and the abnormality detection signal “H” is not output to the inner lead LH for abnormality detection.

  When a short circuit abnormality occurs in any of the capacitors C1 to C3 and the leakage current increases, the leakage current of the capacitor (= the current flowing through the resistor Ra) increases as shown in FIG. 2, and when the threshold current value It is exceeded, the abnormality detection electrode An abnormality detection signal “H” is output to the pad O1. As a result, an external device (not shown) of the semiconductor integrated circuit device 100 can receive the abnormality detection signal “H” to identify the presence of an abnormality sign.

  According to this embodiment, while the user actually uses the semiconductor integrated circuit device 100, the resistor Ra constantly detects the leakage currents of the capacitors C1 to C3 in the semiconductor integrated circuit device 100. For example, if a short circuit abnormality occurs in at least one of the capacitors C1 to C3, the leakage current of the capacitor in which the abnormality has occurred increases, so the current flowing through the resistor Ra also increases. Then, since the terminal voltage of the resistor Ra increases, the comparator 8 outputs the abnormality detection signal “H”. Thereby, it is possible to constantly monitor for signs of leakage current abnormality.

(Second Embodiment)
3 to 5 show a second embodiment of the present invention. The difference from the previous embodiment is that the invalidation circuit invalidates the operation of the current detection circuit after a first predetermined time has elapsed after power-on. And determining whether or not there is a sign of abnormality of the capacitance element according to the detection result of the current detection circuit before being invalidated by the invalidation circuit.

  As shown in FIG. 3, the control switch 11 is connected between the terminals of the resistor Ra. The control switch 11 has a control terminal connected to the timer circuit 12. As shown in FIGS. 4 and 5, the timer circuit 12 counts the time immediately after the semiconductor integrated circuit device 100 is turned on and outputs an off control signal to the control switch 11 until the first predetermined time T1 elapses. When a predetermined time T1 has elapsed, an ON control signal is output to the control switch 11.

  When an ON control signal is given, the control switch 11 short-circuits between the terminals of the resistor Ra and invalidates the function of the resistor Ra as a current detection circuit. Since the comparator 8 can detect the terminal voltage of the resistor Ra before the first predetermined time T1 has elapsed, it can determine the presence or absence of an abnormality sign.

  However, when the first predetermined time T1 elapses, the voltage between the input terminals of the comparator 8 becomes 0 [V]. Therefore, the comparator 8 does not output the abnormality detection signal “H”, and the function of the comparator 8 as a determination circuit also functions. It is invalidated.

  That is, while the timer circuit 12 is controlling the control switch 11 to be off, the comparator 8 can be used to determine whether or not there is an abnormality, but if the timer circuit 12 controls the control switch 11 to be on, The presence or absence of signs cannot be determined.

  During such an indeterminable period, it is not necessary to operate the comparator 8, and it is not necessary to energize the comparator 8. Therefore, in the present embodiment, it is preferable to connect the control switch 13 to the power supply line of the comparator 8 and simultaneously control the control switch 13 to be turned off when the timer circuit 12 controls the control switch 11 to be turned on. By controlling in this way, the power supply voltage Vdd is not energized to the comparator 8 and current consumption of the comparator 8 can be suppressed.

  According to the present embodiment, since the timer circuit 12 invalidates the function of the resistor Ra as a current detection circuit, it is possible to determine whether or not there is a sign of abnormality only during an appropriate predetermined period. Further, since the power supply of the comparator 8 is also cut off when the function of the current detection circuit by the resistor Ra is invalidated, the current consumption of the comparator 8 can be suppressed.

(Modification)
In the above-described embodiment, the resistor Ra constituting the current detection circuit is set to a value of about 1 [kΩ]. In the above-described embodiment, the resistor Ra is disposed at the intermediate node N1 that is small enough to ignore the steady current in the circuit configuration. However, the resistor Ra may be disposed at a node where the alternating current steadily flows, for example. .

  In such a case, as shown in the second embodiment, the timer circuit 12 controls the control switch 11 so as to open the terminals of the resistor Ra only during an initial predetermined period and detect a leakage current. Thereafter, after the inspection is completed, the terminals of the resistor Ra may be short-circuited to invalidate the function as the current detection circuit. Then, even if a current flows constantly to the node, it is possible to avoid as much as possible the possibility that the circuit operation becomes unstable due to the presence of the resistor Ra in the circuit.

(Third embodiment)
FIG. 6 shows a third embodiment of the present invention. The difference from the previous embodiment is that the operation of the current detection circuit is validated after a second predetermined time period excluding the power supply transient fluctuation period after the power is turned on. An enabling circuit is provided, and the presence or absence of a sign of abnormality of the capacitive element is determined according to the detection result of the current detecting circuit after being enabled by the enabling circuit.

  Immediately after the power is turned on, the power supply voltage Vdd is likely to fluctuate transiently, and it takes time until the power supply voltage Vdd is stabilized. Therefore, the current detection function of the resistor Ra is invalidated by turning on the control switch 11 immediately after the power supply voltage is turned on and before the second predetermined time T2 has elapsed using the timer circuit 12 described in the above embodiment. Then, when the power supply voltage Vdd is in an unstable state, both the current detection function of the resistor Ra and the determination function of the comparator 8 are invalidated.

  That is, as shown in the second embodiment, from the second predetermined time T2 shown in FIG. 6, if the timer circuit 12 is valid until the first predetermined time T1 and can determine whether or not there is an abnormality sign. The abnormality sign determination function can be validated only during the first predetermined time T1.

  According to the present embodiment, since the current detection function of the resistor Ra and the determination function of the comparator 8 are validated except for the power supply transient fluctuation period, the leakage current abnormality of the capacitors C1 to C3 during the period excluding the power supply excessive fluctuation period. And the leakage current can be detected during a more appropriate period.

(Fourth embodiment)
FIG. 7 shows a fourth embodiment of the present invention. The difference from the previous embodiment is that a circuit in which a capacitor is not directly connected to a ground electrode pad through a current detection circuit is applied as an abnormality detection target circuit. It is in.

  The power supply circuit 2a is configured based on the power supply voltage Vdd with respect to the power supply circuit 2 described in the above embodiment. The capacitor C1 is connected between the supply terminal of the power supply voltage Vdd and the base of the transistor Tr1a, and removes noise generated at the base of the transistor Tr1a.

  The reference voltage generation circuit 3a is a circuit similar to the reference voltage generation circuit 3 described in the above embodiment, and the capacitors C2 and C3 are respectively connected between the node N2 and the supply terminal of the power supply voltage Vdd, and the node N3 and the power supply. It is connected between the supply terminals of the voltage Vdd.

  When such a circuit configuration is adopted, for example, the capacitor C2 is connected between the terminal of the resistor R3 and the supply terminal of the power supply voltage Vdd. However, when the leakage current of the capacitor C2 increases, the energization current of the resistor R3 also increases. Although it increases, the energization current of the resistor Ra also increases, and the comparator 8 can determine the sign of abnormality of the capacitor C2.

(Fifth embodiment)
8 and 9 show a fifth embodiment of the present invention. The difference from the previous embodiment is that an abnormality connected to the abnormality detection target circuit in order to realize the same function as the abnormality detection target circuit. A switching circuit that operates the emergency response circuit to maintain the function of the abnormality detection target circuit is provided when the determination circuit determines that there is an abnormality sign during actual use of the abnormality detection target circuit. By the way.

  When the abnormality sign determination circuit 1 determines that any of the capacitors C1 to C3 (for example, the capacitor C1) connected to the power supply circuit 2 and the reference voltage generation circuit 3 has an abnormality sign, for example, the capacitor may be a discrete component. If C1 is configured, it can be replaced. However, particularly when the capacitor C1 is configured in the semiconductor integrated circuit device 100, it is impossible to replace the capacitor C1. In such a case, it is desirable to deal with it immediately in the case where a serious abnormality may occur and other circuit operations may be adversely affected.

  Therefore, in this embodiment, an abnormality handling circuit 14 is provided as shown in FIG. This abnormality handling circuit 14 is provided in preparation for an abnormality in the leakage current of the capacitor C1. The abnormality handling circuit 14 includes a capacitor C4, MOS transistors Tr3 and Tr4, a latch circuit 15, and a NOT gate 16.

  A MOS transistor Tr3 is interposed between the capacitor C1 and the base of the transistor Tr1. The capacitor C4 has one end connected to the intermediate node N1 and the other end connected to the base of the transistor Tr1 via the drain / source of the MOS transistor Tr4. The capacitors C1 and C4 have the same characteristics and the same characteristics, and the MOS transistors Tr3 and Tr4 also have the same characteristics.

  A latch circuit 15 is connected to the output of the comparator 8. The latch circuit 15 is configured using, for example, an SR flip-flop, and changes and holds the output level of the latch circuit 15 when the output of the comparator 8 changes. The output signal of the latch circuit 15 is given to the abnormality detection electrode pad O1. Therefore, once the comparator 8 outputs the abnormality detection signal (“H”), the abnormality detection signal “H” continues to be output to the abnormality detection electrode pad O1 even if the abnormality detection signal “H” is subsequently released. .

  The latch circuit 15 complementarily applies an output signal to each gate of the MOS transistors Tr3 and Tr4 using a NOT gate 16. Accordingly, one of the MOS transistors Tr3 and Tr4 is turned on and the other is turned off according to the output level of the latch circuit 15. In this embodiment, the MOS transistors Tr3 and Tr4 are N-channel transistors.

  As shown in FIG. 9, since the comparator 8 does not output an abnormality detection signal “H” when it is not determined that there is an abnormality sign according to the detection voltage of the resistor Ra, the transistor Tr3 is turned on and the transistor Tr4 is turned off. To do. Therefore, although the capacitor C1 functions, the capacitor C4 does not function.

  When it is determined that there is an abnormality sign due to some influence, the comparator 8 outputs an abnormality detection signal “H” (see CMP_OUT in FIG. 9). For this reason, the output of the latch circuit 15 also changes from “L” to “H” and continues to output this “H” level.

  When the latch circuit 15 outputs “H” level, the transistor Tr3 is turned off and the transistor Tr4 is turned on. Therefore, the capacitor C4 functions instead of the capacitor C1. That is, according to this operation, the capacitor C1 in which the abnormality sign is detected can be automatically switched to the capacitor C4. Thereby, normal operation can be maintained.

  According to the present embodiment, since the abnormality handling circuit 14 is provided, even if it is determined that there is an abnormality sign, the capacitor C1 determined to have an abnormality sign can be switched to a capacitor C4 that can operate normally. The normal operation of the circuit can be maintained.

(Sixth embodiment)
FIG. 10 shows a sixth embodiment of the present invention, which is different from the previous embodiment in that a plurality of determination circuits and abnormality handling circuits are provided.

  The circuit configuration illustrated in FIG. 10 mainly includes a resistor Rb serving as a second current detection circuit, a comparator 17 serving as a second determination circuit, and a latch circuit 18 in addition to the circuit configuration illustrated in FIG. The resistor Rb is connected in parallel with the resistor Ra.

  The comparator 8 serving as the first determination circuit outputs a digital level to the latch circuit 15 according to the magnitude of the terminal voltage of the resistor Ra, and the latch circuit 18 latches this digital level, and the first switching circuit through the NOT gate 16a. Is output to the gate of the MOS transistor Tr3.

  The comparator 17 outputs a digital level to the latch circuit 18 in accordance with the magnitude of the terminal voltage of the resistor Rb. The latch circuit 18 latches this digital level and passes through the NOT gate 16b to the gate of the MOS transistor Tr4 serving as the second switching circuit. Output. The outputs of the latch circuits 15 and 18 are both supplied to an OR gate 19.

  At normal times, the MOS transistors Tr3 and Tr4 are both turned on. Therefore, both the capacitors C1 and C4 are connected between the base of the transistor Tr1 and the intermediate node N1, and both function. That is, in the present embodiment, the power supply circuit 2 serving as the abnormality detection target circuit is a circuit including capacitors C1 and C4.

  In this embodiment, the abnormality handling circuit 14a is configured by combining the latch circuit 15, the NOT gate 16a, and the MOS transistor Tr3, and the abnormality handling circuit 14b is configured by combining the latch circuit 18, the NOT gate 16b, and the MOS transistor Tr4. Composed.

  When the leakage current of the capacitor C1 or C4 increases to indicate an abnormality, and any one of the comparators 8 or 17 outputs the abnormality detection signal “H”, the abnormality detection signal is transmitted through the OR gate 19 to the abnormality detection electrode pad O1. It is possible to detect signs of abnormality from the outside.

  When the capacitor C1 shows an abnormality sign, the latch circuit 15 applies an off control signal to the transistor Tr3 through the NOT gate 16a. On the other hand, when the capacitor C4 indicates an abnormality, the latch circuit 18 applies an off control signal to the transistor Tr4 through the NOT gate 16b. Then, the transistor Tr3 or Tr4 corresponding to the capacitor C1 or C4 causing the abnormality sign is switched off, and the capacitor C1 or C4 showing the abnormality sign is not used. Thereby, the capacitor C1 or C4 showing the sign of abnormality can be disconnected from the operating circuit.

  According to the present embodiment, a circuit is operated using a plurality of capacitors C1 and C4, and a circuit in which the capacitor C1 or C4 in which the abnormality sign is generated is detected when an abnormality sign is detected in any one of the circuits. Can be separated from. Thereby, normal operation can be maintained.

(Seventh embodiment)
11 and 12 show a seventh embodiment of the present invention. The difference from the previous embodiment is that the abnormality detection target circuit is applied to a triangular wave generation circuit and the capacitor is applied to charge / discharge applications. is there.

  A triangular wave generation circuit 20 shown in FIG. 11 is a circuit that generates and outputs a triangular wave according to charging / discharging of the capacitor C1 or C4, and includes a comparator 21, a NOT gate 22, analog switches SW1, SW2, an NMOS transistor Tr5, a current source I2, The capacitor C1 or C4 is combined. When the capacitor C1 operates normally, the transistors Tr3 and Tr4 are turned on and off, respectively, and the capacitor C1 is used for circuit operation.

  FIG. 12 is a timing chart showing the operation in the steady state. Assume that the analog switch SW1 in the initial state is on, the analog switch SW2 is off, the output of the comparator 21 is at "L" level, and the NMOS transistor Tr5 is off. Since the analog switch SW1 is on, the high threshold VTH is given as the comparison target voltage of the comparator 21. As shown in FIG. 11, the input voltage of the comparator 21 is set as the output voltage Vout of the circuit.

  In the steady state, when the current source I2 charges the capacitor C1, the input voltage of the comparator 21 gradually increases almost linearly. When the input voltage of the comparator 21 exceeds the high threshold value VTH, the output of the comparator 21 changes to “H” level.

  Then, the analog switch SW1 changes from the on state to the off state, and the analog switch SW2 changes from the off state to the on state, and the low threshold VTL is given as the comparison target voltage of the comparator 21.

  At the same time, the “H” level is applied to the gate of the NMOS transistor Tr5, and the NMOS transistor Tr5 is turned on. Then, the charge of the capacitor C1 is discharged through the NMOS transistor Tr5, and the constant current of the current source I2 also flows through the NMOS transistor Tr5, so that the input voltage of the comparator 21 gradually decreases almost linearly.

  When this terminal voltage reaches the low threshold VTL, the output of the comparator 21 changes to the “L” level, the high threshold VTH is applied as the comparison target voltage of the comparator 21, and the NMOS transistor Tr5 is turned off. Then, the current of the current source I2 charges the capacitor C1 again, and the input voltage of the comparator 21 gradually increases almost linearly. Such a circuit operation is repeated at a frequency of about 1 [kHz], for example.

  When the capacitor C1 is configured in the semiconductor integrated circuit device 100, the capacitance value can be configured with about several [pF], and therefore the current value at the operating frequency of about 1 [kHz] is about several [nA].

  As shown in the above-described embodiment, the current detection circuit using the resistor Ra and the determination circuit using the comparator 8 are configured to detect abnormal signs when the energization current of the resistor Ra becomes about several [μA] or more. Therefore, the current value flowing through the resistor Ra during steady operation is small enough to be ignored compared to the current value flowing through the resistor Ra during abnormality detection.

  Therefore, if the leakage current of the capacitor C1 increases due to some influence and the energization current of the resistor Ra increases on the order of several [μA], the comparator 8 can detect an abnormality sign by detecting this increase in current. The latch circuit 15 can switch the capacitor C1 to the capacitor C4 by switching the output.

  In the present embodiment, even when the abnormality detection target circuit is applied to the triangular wave generation circuit 20 and the capacitor C1 is applied to charge / discharge applications, the same operational effects as those of the above-described embodiment are obtained. In the present embodiment, the configuration applied to the triangular wave generation circuit 20 is shown. However, the circuit is not steadily operated by changing the current (current operation) but operated by changing the voltage (voltage operation). With such a circuit, it is possible to detect signs of abnormality of capacitors connected to various circuits.

(Eighth embodiment)
FIG. 13 shows an eighth embodiment of the present invention. The difference from the previous embodiment is that a leak current generated in the element isolation portion is detected using the element isolation portion for trench isolation between semiconductor elements as a capacitive element. There is.

  As shown in FIG. 13, a plurality of semiconductor elements 32 such as transistors are formed on a support substrate 31 on which the semiconductor integrated circuit device 100 is formed, and a trench 33 is formed between the plurality of semiconductor elements 32. In addition, an insulating film 34 is embedded in the trench 33, thereby providing an element isolation portion.

  The insulating film 34 constitutes a capacitive element for element insulation in the support substrate 31. Therefore, by connecting the element isolation portion by the insulating film 34 to the intermediate node N1, the capacity performance through the insulating film 34 can be sequentially detected.

  Therefore, if the leakage current increases in the insulating film 34, the leakage current flows through the resistor Ra, and the comparator 8 can detect the increase in the leakage current and the presence of an abnormality sign. As shown in FIG. 13, you may connect in parallel with each capacitor | condenser C1-C3 mentioned above. According to the present embodiment, it is possible to detect an abnormality sign generated in the insulating film 34.

(Other embodiments)
The present invention is not limited to the above-described embodiment, and for example, the following modifications or expansions are possible.
Although the configuration in which the ground node of the ground electrode pads G1 and G2 is applied as the constant potential node has been shown, the current detection is not limited to this configuration, and other constant potential nodes (for example, nodes to which a constant bias voltage is applied) are detected. The present invention can be applied to a form in which a circuit is provided.

  In the drawings, Ra and Rb are resistors (current detection circuits), 2 is a power supply circuit (abnormality detection target circuit), 3 is a reference voltage generation circuit (abnormality detection target circuit), 14, 14a and 14b are circuits for dealing with abnormalities, 8 and 17 are comparators (determination circuits), 12 is a timer circuit (invalidation circuit, validation circuit), 20 is a triangular wave generation circuit (abnormality detection target circuit), 32 to 35 are abnormality detection target circuits, and 34 is an insulating film ( Capacitance elements), C1 to C3 indicate capacitors (capacitance elements), and Tr3 and Tr4 indicate MOS transistors (switching circuits).

Claims (6)

Leakage at a node where the steady target value of the energization current flowing to the constant potential node (GND) through the capacitance elements (C1 to C3, 34) provided in the abnormality detection target circuit (2, 3, 20, 32 to 35) becomes zero Current detection circuits (Ra, Rb) for detecting current;
A determination circuit (8, 17) for determining a sign of abnormality of the capacitance element according to a detection result of the current detection circuit during actual use of the abnormality detection target circuit;
An abnormal sign determination circuit comprising: In the abnormality sign determination circuit according to claim 1,
The current detection circuit includes a resistor (Ra) connected to a node where the steady target value of the energization current is zero,
An invalidation circuit (12) for invalidating the operation of the current detection circuit by short-circuiting the resistor (Ra) after the elapse of a first predetermined time (T1) after power-on. The determination circuit (8) includes: The presence or absence of a sign of abnormality of the capacitance elements (C1 to C3, 34) is determined according to the detection result of the current detection circuit (Ra) before being invalidated by the invalidation circuit (12). An abnormal sign determination circuit. In the abnormal sign determination circuit according to claim 1 or 2,
The current detection circuit includes a resistor (Ra) connected to a node where the steady target value of the energization current is zero,
An enabling circuit that validates the operation of the current detection circuit (Ra) by opening the terminals of the resistor (Ra) after the elapse of a second predetermined time (T2) excluding the power supply transient fluctuation period after power-on. 12)
The determination circuit (8) indicates an indication of an abnormality of the capacitance elements (C1 to C3, 34) according to a detection result of the current detection circuit (Ra) after being enabled by the enabling circuit (12). An abnormality sign determination circuit, characterized by determining presence or absence. In the abnormality symptom determination circuit according to any one of claims 1 to 3,
A circuit for realizing a function similar to that of the abnormality detection target circuit (2), and including an abnormality handling circuit (14) connected to the abnormality detection target circuit (2),
When the determination circuit (8) determines that there is a sign of abnormality during the actual use of the abnormality detection target circuit (2), the abnormality handling circuit (14) activates the function of the abnormality detection target circuit (2). An abnormality sign determination circuit comprising a switching circuit (Tr4) that operates so as to maintain. In the abnormality symptom determination circuit according to any one of claims 1 to 3,
A plurality of the determination circuits (8, 17) are provided,
A circuit for realizing a function similar to that of the abnormality detection target circuit (2), including first and second abnormality coping circuits (14a, 14b) connected to the abnormality detection target circuit (2);
When the first determination circuit (8) determines that there is a sign of abnormality during the actual use of the abnormality detection target circuit (2), the first abnormality handling circuit (14a) A first switching circuit (Tr3) that operates to maintain the function of (2);
When the second determination circuit (17) determines that there is a sign of abnormality during actual use of the abnormality detection target circuit (2), the second abnormality handling circuit (14b) An abnormal sign determination circuit comprising a second switching circuit (Tr4) that operates to maintain the function of (2). In the abnormality symptom determination circuit according to any one of claims 1 to 5,
The current detection circuit (Ra) includes the insulating film (34) embedded in the trench (33) between the semiconductor elements (32) constituting the abnormality detection target circuit (32 to 35) as the capacitive element. An abnormality sign determination circuit characterized by detecting a leakage current generated in (34).

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