200903800 九、發明說明： 【發明所屬之技術領域】 本發明揭示一種具有砷化銦鎵/砷化鎵（InGaAs/GaAs) 超晶格基極（superlattice base)之磷化銦鎵/神化鎵 (InGaP/GaAs)異質結構射極雙極性電晶體。本發明之電晶 體元件具有高電流增益、相當低的基_射（B_E)極導通電壓 (tUrn-on v〇ltage)及集-射極（C_E)補償電壓（〇ffset voltage) ’極適於低功率消耗之電路應用。 【先前技術】 以石申化紅為基礎的異質接面雙極性電晶體（HBT)具有 高電流增益、高輸出電流及高頻微波特性，已成為主要的 高速半導體元件之一。通常，異質接面雙極性電晶體之基 -射極導通電壓很大，此將使最低操作電壓受限制。此外， 異質接面雙極性電晶體由於基_射極異質接面與基-集極同 質接面不對稱，其基-射極異質接面之導通電壓較基-集極 同質接面為大，此二接面的導通電壓差將造成大的集-射極 補償電壓，這在電路應用上將增加功率消耗。若能降低基 -射極導通電壓即可減小集_射極的極補償電壓。 過去，已有一些習知技術被提出用以降低基-射極的導 、電壓^知方法之一為使用異質射極結構，亦即異質結 構射極雙極性電晶冑（脑T)。此結構在大能隙_射^ 偈限層與小能隙P型基極層之間加入-層小能隙的n型射 極層，使該射極成為η型的異f結構，用以消除基_射接面 的位IV i峰（potential spike)，進而降低基-射極的導通電壓 200903800 與集-射極補償電壓。然而，若該小能隙的η型射極層太 厚’其對電洞的侷限效應降低，此將在射極中性區 (neutral-emitter region)内造成過大的復合電流，而增加了 基極電流且使電流增益降低。反之，若該小能隙的η型射 極層太薄’基-射接面的位障尖峰（potential spike)仍然存 在’如同傳統的HBT般，其過大的基-射極導通電壓仍未 改善。 另一個習知方法為使用小能隙的基極層。過去，已有 砷化銦鎵（InGaAs)材質與lnxGai_xAsi_yNy材質分別被使用 做為基極層。因該基極層的能隙小，本質濃度高，可改善 基-射極的導通電壓。然而，砷化銦鎵（InGaAs)與砷化鎵 (GaAs)晶格常數並非匹配，這將導致應力產生，且該坤化 細鎵（InGaAs)的厚度亦受限制。雖然以inxGahAsbyNy為 材質的基極層具有小能隙及改善應力的優點，但是其基_ 集極（B-C)異質接面的導電帶不連續值（ΔΕ(：)將導致大的曲 膝效應（knee effect) ’使部分電子在此基-集極（B-C)異質接 面受阻擋’而使集極電流與電流增益降低。 【發明内容】 本發明揭示一種具有砷化銦鎵/珅化鎵（InGaAs/GaAs) 超晶格基極之磷化銦鎵/砷化鎵（InGaP/GaAs)異質結構射 極雙極性電晶體。本發明之元件具有高電流增益、相當低 的基-射極導通電壓及集-射極補償電壓，極適於低功率消 耗之電路應用。 本發明的較佳具體實施例包括（但不限於）下列項目： 200903800 .一種超晶格基極異質結構雙極性電晶體，包含：一半導 體基板；一位於該半導體基板上之n+型摻雜次集極層； 一位於該n+型摻雜次集極層上之n.型摻雜集極層；一位 於該η型摻雜集極層上之p+型超晶格基極層丨一位於該 P型超晶格基極層上之n型摻雜射極層；一位於該η型 摻雜射極層上之η型摻雜侷限層；一位於該11型摻雜侷 限層上之η+型摻雜半導體蓋層。 士廂述項目第1項之超晶格基極異質結構雙極性電晶 體其中該半導體基板為半絕緣型之GaAs。 於 如則述項目第1項之超晶格基極異質結構雙極性電晶 體，其中該n+型摻雜次集極層為GaAs，且該n+型摻雜 次集極層具有一範圍介於0.2〜i μπι的厚度及一範圍介 1 X 1018 〜3 X 1019 cm-3 之濃度。。 .如則述項目第1項之超晶格基極異質結構雙極性 1〇 声其中該η·型摻雜集極層為GaAs，且該n-型推雜集極 a具有一範圍介於0.2〜1 μηι的厚度及一範圍介於η=ι 1 X 1〇17 cm·3 之濃度 “項目第1項之超晶格基極異質結構雙極性電晶 :其中該p+型超晶格基極層為InxGaixAs/GaAs超晶 ’其中X為0.05〜0.25。 體⑴述項目第1項之超晶格基極異質結構雙極性電晶 Z其中該η型摻雜射極層為GaAs，且該n型摻雜射極 η具有-範圍介於15〇〜議埃的厚度，及一濃度範圍為 1 χ 1017 〜5 X 1018 cm — 3 的摻雜。 200903800 7.如前述項目帛丨項之超晶格基極異質結構雙極性電晶 體，其中該η型摻雜侷限層為In〇49Ga〇5iP，且該η型: 雜侷限層具有一範圍介於5〇〇〜2〇〇〇埃的厚度及一濃 度範圍為η= 1 X 1〇17〜5 x 1〇ucm.3的推雜。/辰 8.如前述項目第i項之超晶格基極異質結構雙極性電晶 體，其中該n+型摻雜半導體蓋層為GaAs，其具有一範圍 介於0.1〜0·5 μιη的厚度及一範圍介於n+ = ! X i〇i8〜3 X 1019 cm_3的摻雜。 目第5項之超晶格基極異質結構雙極性電晶 體，其中該InxGai_xAS/GaAS超晶格中之InxGa] xAs為井 層且該GaAs為能障層。 1〇_如前述項目第9項之超晶格基極異質結構雙極性電晶 體、，其中該井層為N週期且該能障層為週期，其曰中曰 N為5〜20。。 11:前述項目第9項之超晶格基極異質結構雙 體，其中該井層具有一範圍介於30〜70埃的厚度及一範 圍介於p+=lx1018〜“ww的摻雜。 12::=目第9項之超晶格基極異質結構雙 ^其中該能障層具有—範圍介於3q〜7q埃的厚度及一 範圍介於p+ = 1 X 1〇18〜 19 4χΐο cm3的摻雜。 13.如前述項目第丨項之超晶格 質 共貨結構雙極性電晶 體、中該1摻雜侷限層為AlxGalxAS，其中 〜〇·5,且該n型摻雜侷限層 ，，-' ’ 圍介於500〜2000 埃的厚度，及-濃度範圍為n= 〜 5 χ 10 cm 200903800 的摻雜。 以本發明之超晶格基極元件而言，因載子穿透行為而 使δ亥超晶格基極區域内有較多的少數載子（亦即電子）儲 存，其電流增益高達246且集-射極補償電壓僅為16 mV。 且萬基-射極電流為1 μΑ時，基_射（b_e)極導通電壓僅為 〇·966 V，此導通電壓較習知傳統的異質結構射極雙極性電 晶體降低了 40 mV。 【實施方式】 依本發明的一較佳具體實施例所完成的具砷化銦鎵/ 砷化鎵（InGaAs/GaAs)超晶格基極之磷化銦鎵/砷化鎵 (InGaP/GaAs)異質結構射極雙極性電晶體，其結構如圖一 所不。本發明超晶格基極元件丨〇〇在未摻雜半導體料材基 1 02、一 rT型摻雜 一 η型摻雜射極 板101上依序形成一 n+型掺雜次集極層 集極層103、一 P+型超晶格基極層104、 層105 11型摻雜侷限層106及一 η+型摻雜半導體蓋層 107其中，該ρ型超晶格基極層包含一 ν週期之井 (well)層ι〇8及一（Ν_υ週期之能障（barder^ 1〇9,其中ν 可為5至20。本發明元件之製作步驟依序如下：（丨）蒸鍍 射極金屬於該n+型摻雜半導體蓋層1〇7上，再以高溫短 時間燒結（sintering)，使射極金屬浸入，以完成射極之歐 姆接觸；（2)以該射極金屬為硬遮罩（hard mask)，化學蝕 刻去除該型摻雜半導體蓋層1G7、該n型摻雜偈:層 1〇8及該n型摻雜射極層1〇5，以曝出該p+型超晶格美 層1〇4;(3)蒸鍍基極金屬於該/型超晶格基極層1〇41， 200903800 以完成基極金屬之歐姆接觸；⑷遮住略大於該基極金屬 區域，化學㈣去除該P+型超晶格基極層1G4及該m 摻雜集極層1〇3,以曝出該n+型摻雜次集極層1〇2;(5)蒸 鍍集極金屬於該η、摻雜次集極^ 1〇2 i，再以高溫短 時間燒結’使該集極金屬浸入，以完成集極之歐姆接觸; (6)遮住略大於該集極金屬區域，化學_去除胃n+型推 雜人集極層1G2直至部分該未摻雜半導體料材基板⑻， 以將元件間隔離（mesa)。 為使本發明更易瞭解及實施，請參見以下實施例說明 [實施例】 於此實施例中，本發明超晶格基極元件1〇〇之該未推 雜半導體材料基板101為GaAs材質；該n+型摻雜次集極 層_:〇2為GaAs材質，厚度為5〇〇〇埃，漠度為i X， 該η型摻雜集極層1G3$材質，厚度為 埃’濃度為 5 X 1 〇16 ^ cm ，該p型超晶格基極層ι〇4為200903800 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention discloses an indium gallium phosphide/delta gallium (InGaP) having a superlattice base of an indium gallium arsenide/arsenide gallium arsenide (InGaAs/GaAs) superlattice base. /GaAs) Heterostructure emitter bipolar transistor. The transistor element of the present invention has high current gain, relatively low base-to-emitter (B_E) pole turn-on voltage (tUrn-on v〇ltage), and set-emitter (C_E) compensation voltage (〇ffset voltage) Low power consumption circuit applications. [Prior Art] Heterojunction bipolar transistor (HBT) based on Shi Shenhuahong has high current gain, high output current and high frequency microwave characteristics, and has become one of the main high-speed semiconductor components. Typically, the base-emitter turn-on voltage of a heterojunction bipolar transistor is large, which limits the minimum operating voltage. In addition, the heterojunction bipolar transistor has a base-emitter heterojunction whose conduction voltage is larger than the base-collector homojunction due to the asymmetry of the base-emitter heterojunction and the base-collector homojunction. The turn-on voltage difference between the two junctions will result in a large collector-emitter compensation voltage, which will increase power consumption in circuit applications. If the base-emitter turn-on voltage can be lowered, the collector-emitter polarity compensation voltage can be reduced. In the past, some conventional techniques have been proposed to reduce the base-emitter conduction and voltage sensing methods using a heterogeneous emitter structure, i.e., a heterostructure emitter bipolar transistor (brain T). The structure adds a small-energy gap n-type emitter layer between the large-gap 射 偈 偈 layer and the small-gap P-type base layer, so that the emitter becomes an n-type hetero-f structure for The potential IV of the base-emitter surface is eliminated, thereby reducing the base-emitter turn-on voltage of 200903800 and the collector-emitter compensation voltage. However, if the small-gap η-type emitter layer is too thick, its localized effect on the hole is reduced, which will cause excessive recombination current in the neutral-emitter region and increase the base. Extreme current and reduced current gain. On the other hand, if the n-type emitter layer of the small energy gap is too thin, the potential spike of the base-emitter surface still exists. As with the conventional HBT, its excessive base-emitter turn-on voltage has not improved. . Another conventional method is to use a base layer of a small energy gap. In the past, indium gallium arsenide (InGaAs) materials and lnxGai_xAsi_yNy materials have been used as the base layer. Since the base layer has a small energy gap and a high intrinsic concentration, the base-emitter turn-on voltage can be improved. However, the indium gallium arsenide (InGaAs) and gallium arsenide (GaAs) lattice constants do not match, which leads to stress generation, and the thickness of the indium gallium (InGaAs) is also limited. Although the base layer made of inxGahAsbyNy has the advantages of small energy gap and improved stress, the discontinuous value of the conduction band of the base-collector (BC) heterojunction (ΔΕ(:) will cause a large curved knee effect ( Knee effect) 'Let some electrons be blocked at this base-collector (BC) heterojunction' to reduce the collector current and current gain. SUMMARY OF THE INVENTION The present invention discloses an indium gallium arsenide/gallium gallium nitride ( InGaAs/GaAs) super-lattice base indium gallium phosphide/gallium arsenide (InGaP/GaAs) heterostructure emitter bipolar transistor. The device of the invention has high current gain, relatively low base-emitter turn-on voltage And set-emitter compensation voltages, which are well suited for low power consumption circuit applications. Preferred embodiments of the invention include, but are not limited to, the following: 200903800. A superlattice based heterostructure bipolar transistor, The invention comprises: a semiconductor substrate; an n+ type doped collector layer on the semiconductor substrate; an n. type doped collector layer on the n+ type doped collector layer; P+ type superlattice base layer on the collector layer An n-type doped emitter layer on the P-type superlattice base layer; an n-type doped localization layer on the n-type doped emitter layer; and a layer on the 11-type doped localization layer η+ type doped semiconductor cap layer. The superlattice base heterostructure bipolar transistor of item 1 of the article, wherein the semiconductor substrate is semi-insulating GaAs. a lattice-based heterostructure bipolar transistor, wherein the n+-type doped collector layer is GaAs, and the n+-type doped collector layer has a thickness ranging from 0.2 μi μπι and a range of 1 X The concentration of 1018 〜3 X 1019 cm-3 is as described in item 1 of the superlattice base heteropolar structure bipolar 1 hum, wherein the η-type doped collector layer is GaAs, and the n- The type of the hybrid collector a has a thickness ranging from 0.2 to 1 μηι and a concentration ranging from η = ι 1 X 1 〇 17 cm · 3 "the superlattice base heterostructure bipolar of item 1 of the item" Electromorphic crystal: wherein the p+ type superlattice base layer is InxGaixAs/GaAs supercrystal 'where X is 0.05~0.25. (1) The superlattice base heterostructure double of item 1 of the item a polar electric crystal Z, wherein the n-type doped emitter layer is GaAs, and the n-type doped emitter η has a thickness ranging from 15 〇 to 15 Å, and a concentration range is 1 χ 1017 〜 5 X 1018 Doping of cm-3. 200903800 7. The superlattice heteropolar structure bipolar transistor according to the above item, wherein the n-type doped confinement layer is In〇49Ga〇5iP, and the n-type: impurity The confinement layer has a thickness ranging from 5 〇〇 to 2 〇〇〇 Å and a concentration range of η = 1 X 1 〇 17 〜 5 x 1 〇 ucm. / 辰8. The superlattice-based heterostructure bipolar transistor of item i of the foregoing item, wherein the n+ type doped semiconductor cap layer is GaAs having a thickness ranging from 0.1 to 0.5 μm A doping range of n+ = ! X i〇i8~3 X 1019 cm_3. The superlattice heteropolar structure bipolar electrocrystal of item 5, wherein the InxGa] xAs in the InxGai_xAS/GaAS superlattice is a well layer and the GaAs is an energy barrier layer. 1〇_ The superlattice-based heterostructure bipolar electro-crystal of item 9 of the preceding item, wherein the well layer is N-period and the barrier layer is periodic, and the 曰N in the crucible is 5-20. . 11: The superlattice base heterostructure double body of item 9 of the preceding item, wherein the well layer has a thickness ranging from 30 to 70 angstroms and a range of p+=lx1018~"ww doping. 12: := The superlattice base heterostructure of the ninth item of the head; wherein the barrier layer has a thickness ranging from 3q to 7q angstroms and a range of p+ = 1 X 1 〇 18~ 19 4 χΐ ο 3 13. A super-lattice-weighted bipolar transistor according to the above item, wherein the 1-doped localization layer is AlxGalxAS, wherein ~〇·5, and the n-type doped confinement layer, - ' ' is a thickness of 500 to 2000 angstroms, and - a concentration range of n = 〜 5 χ 10 cm of 200903800. With the superlattice base element of the present invention, due to carrier penetration behavior There are a large number of minority carriers (ie, electrons) stored in the base region of the δH superlattice with a current gain of up to 246 and a collector-emitter compensation voltage of only 16 mV. The 10,000-emitter current is 1 μΑ. The base-to-emitter (b_e) pole conduction voltage is only 〇·966 V, which is 40 mV lower than the conventional conventional heterostructure emitter bipolar transistor. Embodiments of InGaAs/GaAs super-lattice indium gallium arsenide/indium gallium arsenide (InGaP/GaAs) heterogeneous in accordance with a preferred embodiment of the present invention The structure of the emitter bipolar transistor has a structure as shown in Fig. 1. The superlattice base element of the present invention is in an undoped semiconductor material base 102, an rT type doped n-type doped emitter An n+ type doped collector collector layer 103, a P+ type superlattice base layer 104, a layer 105 type 11 doped confinement layer 106, and an n+ type doped semiconductor cap layer are sequentially formed on the board 101. 107 wherein the p-type superlattice base layer comprises a ν cycle well layer ι 8 and a Ν υ cycle energy barrier (barder ^ 1 〇 9, where ν can be 5 to 20. The invention The steps of fabricating the components are as follows: (丨) vapor-depositing the emitter metal on the n+-type doped semiconductor cap layer 1〇7, and then sintering at a high temperature for a short time to immerse the emitter metal to complete the emitter Ohmic contact; (2) using the emitter metal as a hard mask, chemically etching to remove the doped semiconductor cap layer 1G7, the n-type doped germanium: layer 1 8 and the n-type doped emitter layer 1〇5 to expose the p+ type superlattice layer 1〇4; (3) vapor-deposited base metal to the/type superlattice base layer 1〇41 , 200903800 to complete the ohmic contact of the base metal; (4) to cover slightly larger than the base metal region, chemically (4) remove the P+ type superlattice base layer 1G4 and the m doped collector layer 1〇3 to expose The n+ type doped sub-collector layer 1〇2; (5) vapor-depositing the collector metal at the η, doping the second collector ^1〇2 i, and then sintering at a high temperature for a short time to immerse the collector metal, To complete the ohmic contact of the collector; (6) to cover slightly larger than the collector metal region, chemically remove the stomach n+ type dopant collector layer 1G2 until part of the undoped semiconductor material substrate (8) to Isolation (mesa). In order to make the present invention easier to understand and implement, please refer to the following embodiments. [Embodiment] In this embodiment, the unlatched semiconductor material substrate 101 of the superlattice base device 1 of the present invention is made of GaAs; n+ type doped collector layer _: 〇2 is GaAs material, thickness is 5 〇〇〇, and the degree of i x is n-type doped collector layer 1G3$ material, thickness is '' concentration is 5 X 1 〇 16 ^ cm , the p-type superlattice base layer ι〇4 is
超晶格材質，本實施例中N為10,其中該N 週期(亦即10週期)之井⑽⑴層1〇8為、仙。…材質， 每層井厚度為50埃，濃度為5 χ 1〇18 cm.3,且該週 期（亦即9週期）之能障（⑽⑺層109為GaAs材質，每層 能障層厚度為50埃’濃度為5 χ 1〇18 cm.3;該η型摻雜 射，層105為GaAs材質，厚度為3〇〇埃，濃度為5χΐ〇ΐ7 瓜，該11型摻雜侷限層1〇6為ln〇 49Ga〇 5ΐΡ材質，厚度 為1000埃，濃度為5 χ 1〇17心3 ;帛〆型換雜半導體蓋 層1〇7為GaAs材質，厚度為3000Α，濃度為i x 10i9 cm-3。 200903800 為顯現本發明之功效，吾人列出習知技術之磷化銦鎵/ 砷化鎵（InGaP/GaAs)異質結構射極雙極性電晶體200以和 本發明超晶格基極元件1 0 0相比較。此習知技術之磷化銦 鎵/砷化鎵（InGaP/GaAs)異質結構射極雙極性電晶體2〇〇 其結構如圖二所示。該結構包含：未摻雜半導體材料基板 20 1、n+型摻雜次集極層202、rf型摻雜集極層203、 p + 型基極層204、η型推雜射極層205、η型換雜侷限層206 及η+型摻雜半導體蓋層207。其中，該未摻雜半導體材料 基板20 1為GaAs材質；該η+型摻雜次集極層202為GaAs 材質，厚度為5000埃，濃度為1 X 1 cm.3 ;該n_型捧 雜集極層203為GaAs材質，厚度為5000埃’濃度為5 χ 1〇16 cm·3 ;該ρ+型基極層2〇4為GaAs材質，厚度為95〇 埃’濃度為5 χ 1〇18 cm·3 ;該n型摻雜射極層2〇5為 材質’厚度為300埃’濃度為5xl〇17 cm_3 ;該η型摻雜 侷限層206為In〇 49Ga〇 5lP材質，厚度為1〇〇〇埃，濃度 為5x 10”cm_3;該n+型摻雜半導體蓋層之们為^八8材 質，厚度為3000埃，濃度為i χ 1〇19 cm.3。 相較於本發明超晶格基極元件1〇〇和習知技術之磷化 銦鎵/坤化鎵（InGaP/GaAs)異質結構射極雙極性電晶體 ，本發明元件100的基極層為InGaAs/GaAs超晶格材 質，而習知技術200的基極層為GaAs體咖叫材質。兩 者基極層總厚度相同且皆為950埃，且摻雜濃度亦相同， 射極及集極面積皆分別為5〇x5〇_2與1〇“ 1〇〇_2。 對於該二元件的實施例，以二維半導體元件模擬軟體 200903800 SILVACO進行分析與比較。模擬時皆考慮方程 式電子與電洞連續方程式、Shockley-Read-Hall (SRH) 復合、Auger復合及B〇hzmann統計學。 圖二為本發明實施例之該超晶格基極元件1〇〇於熱平 衡及偏壓日寺的能帶圖。而圖四為該習知技術元件2〇〇於熱 平衡及偏壓時的能帶圖。明顯地，此二元件從熱平衡至偏 壓VEB = +1.〇 v時其基-射極接面之位障尖峰皆可消除。 因該一元件在大旎隙n型射極侷限層與小能隙p型基極層 之門白力入層小月匕隙的η型射極層，使pn接面為同質 結構，可使射極側之能帶拉低’進而消除位障尖峰。 圖五為本發明超晶格基極元件100及習知技術元件 200的二端電流-電壓（I_V)特性曲線圖。圖中實線為本發 明實施例的特性曲線圖，虛線為習知技術元件的特性曲線 圖。明顯地，本發明超晶格基極元件1〇〇較習知技術元件 200具有更大的輸出電流及增益。圖六為本發明超晶格基 極兀件1 00及習知技術元件200於低電流低電壓時的三端 電流-電壓放大特性曲線圖。圖中實線為本發明實施例的 特性曲線圖，虛線為習知技術元件的特性曲線圖。當基極 電流IB = 50 μΑ時，習知技術元件200的集-射極補償電 壓為40 mV，而本發明元件1〇〇的集_射極補償電壓僅為 1 6 mV。 圖七為本發明超晶格基極元件1 〇 〇及習知技術元件 200於基_集極電壓vBC=〇V時的Gummel圖。圖中可看 出本發明超晶格基極元件1 〇〇較習知技術元件2〇〇有較大 12 200903800 的集極電流。當集極電流Ic，A時，本發明超晶格基極 兀件100的基射極導通電壓為〇 966 V’而習知技術元件 200的基-射極導通電壓為i 〇〇6Ve因此，本發明元件工㈧ 的基-射極導通電壓較習知技術元件200降低有40 之 多，此可降低元件的操作電壓及集_射極補償電壓，極適 於低功率消耗之電路應用。而當基·射極電壓為125 V 時，本發明超晶格基極元件100及習知技術元件200的增 :分別為246及70。圖中亦可看出，該二元件的集極電 流理想因子（ideality factor) nc於低電流時幾乎等於丨，此 表示電子傳輸經過基-射接面由擴散機制所支配，且基-射 接面之位障尖峰應已被消除。此外，該二元件的基極電流 理想因子nb於低電流時幾為h9,此表示本發明超晶格基 極元件採用超晶格基極層並不會增加基極電流或使元件 輸出特性退化。 圖八為熱平衡時本發明超晶格基極元件丨〇〇及習知技 術元件200於基-射極附近的載子分佈圖。由於砷化銦鎵/ 砷化鎵（InGaAs/GaAs)超晶格基極存在價電帶不連續值 (ΔΕν) ’部分砷化鎵能障層ι〇9之電洞易於擴散至砷化銦 鎵之井層108中，因此井層1〇8的電洞濃度將較能障層 1 09為高。相同地，由於此砷化銦鎵/砷化鎵（In(JaAs/GaAs) 超晶格基極存在導電帶不連續值（ΔΕ(^，井層1〇8的電子 濃度亦較能障層1 〇 9為高。 圖九為順向偏壓VBE=+1V時本發明超晶格基極元件 100及習知技術元件200於基·射極附近的載子分佈圖。 13 200903800 相較於習知技術元件彻，本發明超晶格基極元件_於 順向偏壓時其基極區具有較高的少數載子（電子）儲存。由 於電子在基極區除以擴散傳輸外，亦可以穿透的方式進入 超曰曰秸基極區，因此超晶格基極區内的少數載子儲存濃度 杈咼。此高濃度的少數載子儲存可使集極電流快速增加， 進而降低了基_射極的導通電壓（t則·。n vGhage)、集-射極 補償電壓及電路應用之功率消耗。 、雖然本發明已利用上述實施例說明，但是本發明並不 被所揭露的實施例所限制，熟悉本項技藝之人士仍可作出 不脫離本發明範圍之修飾及變化。 【圖式簡單說明】 圖-係本發明實施例之具超晶格基極之異質結構射極 雙極性電晶體的結構圖。 圖二係習知技術之傳統異質結構射極雙極性冑晶體的 結構圖。 圖三係本發明實施例於熱平衡及偏壓時的能帶圖。 圖四係習知技術元件於熱平衡及偏壓時的能帶圊。 圖五係本發明實施例及習知技術元件的電流-電壓三 鳊特性曲線圖。實線為本發明實施例的特性曲線圖，虛線 為習知技術元件的特性曲線圖。 圖六係本發明實施例及習知技術元件於低電流低電壓 時的三端電流-電壓放大特性曲線圖。實線為本發明實施 例的特性曲線圖，虛線為習知技術元件的特性曲線圖。 14 200903800 圖七係本發明實施例及習知技術元件於於基-集極電 壓為零時的GUmmel圖。實線為本發明實施例的特性曲線 圖’虛線為習知技術元件的特性曲線圖。 圖八係熱平衡時本發明實施例及習知技術元件於基_ 射極附近的載子分佈圖。實線為本發明實施例的特性曲線 圖’虛線為習知技術元件的特性曲線圖。 圖九係基-射極偏壓+1V時本發明實施例及習知技術 ( 元件於基-射極附近的載子分佈圖。實線為本發明實施例 的特性曲線圖，虛線為習知技術元件的特性曲線圖。 【主要元件符號說明】 1 00超晶格基極之異質結構射極雙極性電晶體結構 101未摻雜半導體材料基板 102 n+型摻雜次集極層 103 rT型摻雜集極層 ( 104 P+型超晶格基極層 105 η型摻雜射極層 106η型摻雜侷限層 107 η+型摻雜半導體蓋層 1 0 8井層 109能障層 201未摻谁半導體材料基板 202 η+型摻雜次集極層 203 rT型摻雜集極層 15 200903800 204 p +型基極層 2 0 5 η型摻雜射極層 206 η型摻雜侷限層 207 η+型摻雜半導體蓋層 16In the superlattice material, N is 10 in the embodiment, wherein the well (10) (1) layer 1 〇 8 of the N period (that is, 10 cycles) is sin. ...material, each layer has a thickness of 50 angstroms and a concentration of 5 χ 1〇18 cm.3, and the energy barrier of the period (ie, 9 cycles) ((10)(7) layer 109 is made of GaAs, each layer has a barrier layer thickness of 50 The concentration of Å' is 5 χ 1〇18 cm.3; the η-type doping, layer 105 is made of GaAs, the thickness is 3 〇〇, the concentration is 5χΐ〇ΐ7 melon, the type 11 doped confined layer 1〇6 It is ln〇49Ga〇5ΐΡ material with a thickness of 1000 angstroms and a concentration of 5 χ 1〇17 cores 3; the 帛〆-type semiconductor cover layer 〇7 is made of GaAs, with a thickness of 3000 Α and a concentration of ix 10i9 cm-3. 200903800 To demonstrate the efficacy of the present invention, we have listed prior art indium gallium phosphide/gallium arsenide (InGaP/GaAs) heterostructure emitter bipolar transistor 200 and the superlattice base element of the present invention. In comparison, the conventional indium gallium arsenide/gallium arsenide (InGaP/GaAs) heterostructure emitter bipolar transistor has a structure as shown in FIG. 2. The structure includes: an undoped semiconductor material substrate 20, n + doped sub-collector layer 202, rf-type doped collector layer 203, p + -type base layer 204, n-type irritating emitter layer 205, n-type heterogeneous layer 206 and +-doped semiconductor cap layer 207. The undoped semiconductor material substrate 20 1 is made of GaAs; the n+-type doped sub-collector layer 202 is made of GaAs, has a thickness of 5000 angstroms, and has a concentration of 1×1 cm. .3; the n_ type holding collector layer 203 is made of GaAs, and has a thickness of 5000 Å and a concentration of 5 χ 1 〇 16 cm·3; the ρ+ type base layer 2 〇 4 is made of GaAs and has a thickness of 95 The concentration of 〇 ' is 5 χ 1 〇 18 cm·3; the n-type doped emitter layer 2 〇 5 is a material having a thickness of 300 angstroms and a concentration of 5×1 〇 17 cm −3 ; the n-type doped localization layer 206 is In 〇49Ga〇5lP material, thickness 1 〇〇〇, concentration 5× 10”cm_3; the n+ type doped semiconductor cap layer is 八8 material, thickness 3000 ing, concentration i χ 1〇19 cm .3. The basis of the element 100 of the present invention compared to the superlattice base element 1 of the present invention and the prior art indium gallium arsenide/indium gallium (InGaP/GaAs) heterostructure emitter bipolar transistor. The pole layer is made of InGaAs/GaAs superlattice material, and the base layer of the prior art 200 is a GaAs body coffee material. The total thickness of the base layer is the same and both are 950 angstroms, and the doping concentration is also the same, the emitter And collector The products are respectively 5〇x5〇_2 and 1〇“1〇〇_2. For the two-element embodiment, the two-dimensional semiconductor component simulation software 200003800 SILVACO is analyzed and compared. The equations are considered electronic and electrical. Hole continuous equation, Shockley-Read-Hall (SRH) compound, Auger complex and B〇hzmann statistics. FIG. 2 is an energy band diagram of the superlattice base element 1 in thermal equilibrium and biased Japanese temple according to an embodiment of the present invention. Figure 4 is an energy band diagram of the prior art component 2 in thermal equilibrium and bias voltage. Obviously, the barrier elements of the base-emitter junction can be eliminated when the two components are from thermal equilibrium to bias voltage VEB = +1.〇 v. Because the element is in the n-type emitter layer of the large gap n-type emitter confinement layer and the small energy gap p-type base layer, the n-type emitter layer of the small moon gap is made to make the pn junction a homogenous structure, so that the pn junction can be made into a homogenous structure. The energy band on the emitter side is pulled low to eliminate the barrier peak. Figure 5 is a graph showing the two-terminal current-voltage (I_V) characteristic of the superlattice base element 100 and the prior art element 200 of the present invention. The solid line in the figure is a characteristic diagram of the embodiment of the invention, and the broken line is a characteristic diagram of a conventional technical component. Significantly, the superlattice base element 1 of the present invention has greater output current and gain than the prior art element 200. Fig. 6 is a graph showing the three-terminal current-voltage amplification characteristic of the superlattice base element 100 and the prior art component 200 of the present invention at low current and low voltage. The solid line in the figure is a characteristic diagram of an embodiment of the present invention, and the broken line is a characteristic diagram of a conventional technical component. When the base current IB = 50 μΑ, the collector-emitter compensation voltage of the conventional technology component 200 is 40 mV, and the collector-emitter compensation voltage of the component 1〇〇 of the present invention is only 16 mV. Figure 7 is a Gummel diagram of the superlattice base element 1 and the prior art component 200 of the present invention at the base_collector voltage vBC = 〇V. It can be seen that the superlattice base element 1 of the present invention has a larger collector current of 12 200903800 than the conventional technique element 2 . When the collector current Ic, A, the base emitter conduction voltage of the superlattice base element 100 of the present invention is 〇 966 V' and the base-emitter conduction voltage of the conventional technology component 200 is i 〇〇 6Ve. The base-emitter turn-on voltage of the component (8) of the present invention is reduced by more than 40 compared with the conventional technology component 200, which can reduce the operating voltage of the component and the collector-emitter compensation voltage, and is highly suitable for circuit applications with low power consumption. When the base and emitter voltages are 125 V, the superlattice base element 100 of the present invention and the prior art element 200 are increased by 246 and 70, respectively. It can also be seen that the collector current ideal factor nc of the two components is almost equal to 丨 at low current, which means that the electron transport is dominated by the diffusion mechanism through the base-emitter junction, and the base-shooting The peak of the barrier should have been eliminated. In addition, the base current ideal factor nb of the two elements is h9 at a low current, which means that the superlattice base element of the present invention uses a superlattice base layer without increasing the base current or degrading the output characteristics of the element. . Figure 8 is a diagram showing the carrier distribution of the superlattice base element 本 of the present invention and the conventional technical element 200 in the vicinity of the base-emitter in thermal equilibrium. Due to the valence band discontinuity value (ΔΕν) of the indium gallium arsenide/arsenide gallium arsenide (InGaAs/GaAs) superlattice base, the part of the gallium arsenide barrier layer ι〇9 is easily diffused to indium gallium arsenide. In the well layer 108, the hole concentration of the well layer 1〇8 will be higher than the energy barrier layer 109. Similarly, since the indium gallium arsenide/arsenide gallium (In(JaAs/GaAs) superlattice base has a discontinuous value of the conduction band (ΔΕ(^, the electron concentration of the well layer 1〇8 is also higher than that of the barrier layer 1). 〇9 is high. Figure 9 is a distribution diagram of the carrier of the superlattice base element 100 and the prior art element 200 in the vicinity of the base and the emitter when the forward bias voltage VBE = +1 V. 13 200903800 Knowing the technical components, the superlattice base element of the present invention has a higher minority carrier (electron) storage in the base region when forward biased. Since the electron is divided by the diffusion transmission in the base region, The penetrating mode enters the base region of the super-tipped straw, so the minority carrier in the base region of the superlattice stores a concentration 杈咼. This high concentration of minority carrier storage can increase the collector current rapidly, thereby reducing the base. The on-voltage of the emitter (t is · n vGhage), the collector-emitter compensation voltage, and the power consumption of the circuit application. Although the invention has been described using the above embodiments, the invention is not disclosed. The person skilled in the art can still make modifications without departing from the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 2 is a structural diagram of a heterostructure emitter bipolar transistor having a superlattice base according to an embodiment of the present invention. FIG. 2 is a conventional heterostructure emitter bipolar 胄 of the prior art. Figure 3 is an energy band diagram of the embodiment of the present invention in thermal equilibrium and bias voltage. Figure 4 is an energy band diagram of a conventional technical component in thermal equilibrium and bias voltage. Figure 5 is an embodiment of the present invention and The current-voltage triad characteristic diagram of the technical component is shown in the figure. The solid line is the characteristic graph of the embodiment of the present invention, and the broken line is the characteristic graph of the conventional technical component. FIG. 6 is the embodiment of the present invention and the conventional technical component is low. A three-terminal current-voltage amplification characteristic diagram when the current is low voltage. The solid line is a characteristic diagram of an embodiment of the present invention, and the broken line is a characteristic diagram of a conventional technical component. 14 200903800 FIG. 7 is an embodiment and a prior art of the present invention. The technical component is a GUmmel diagram when the base-collector voltage is zero. The solid line is a characteristic curve diagram of the embodiment of the present invention, and the broken line is a characteristic curve diagram of a conventional technical component. Examples of the carrier distribution of the prior art components in the vicinity of the base_emitter. The solid line is a characteristic curve of the embodiment of the present invention. The broken line is a characteristic diagram of a conventional technical component. Fig. 9 is a base-emitter bias +1V, the embodiment of the present invention and the prior art (the distribution map of the component in the vicinity of the base-emitter. The solid line is the characteristic curve of the embodiment of the present invention, and the broken line is the characteristic curve of the conventional technical component. Component symbol description] 1 00 superlattice base heterostructure emitter bipolar transistor structure 101 undoped semiconductor material substrate 102 n+ type doped collector layer 103 rT type doped collector layer (104 P+ type super Lattice base layer 105 n-type doped emitter layer 106 n-type doped confinement layer 107 n + type doped semiconductor cap layer 1 0 8 well layer 109 energy barrier layer 201 undoped semiconductor material substrate 202 η + type doping Secondary collector layer 203 rT type doped collector layer 15 200903800 204 p + type base layer 2 0 5 n type doped emitter layer 206 n type doping confinement layer 207 n + type doped semiconductor cap layer 16