TW200901380A - Dynamic random access memory and fabricating method thereof - Google Patents

Abstract

A dynamic random access memory is provided, including a semiconductor substrate, a capacitor and a transistor. A plurality of column structures, each has an insulating layer, a semiconductor layer and a semiconductor protrusion part from bottom to top, is disposed on the semiconductor substrate. The capacitor includes a bottom electrode, a top electrode and a capacitor dielectric layer. The bottom electrode is disposed in the gap between the adjacent column structures, and connected to the semiconductor substrate. The top electrode is disposed in the semiconductor layer. The capacitor dielectric layer is disposed between the bottom electrode and the top electrode. The transistor includes a gate, a first doped region, and a second doped region. The gate is disposed on the sidewall of the semiconductor protrusion part. The first doped region is disposed in the semiconductor protrusion part below the gate, and coupled with the top electrode. The second doped region is disposed in the semiconductor protrusion part above the gate.

Description

200901380 2005-0108 22658twf.doc/n IX. Description of the Invention: [Technical Field] The present invention relates to a memory element and a method of fabricating the same, and particularly to a dynamic random access memory (dynamic rand) 〇in access memory, DRAM) and its making method. [Prior Art] As the functions of today's computer microprocessors become more and more powerful, the programs and operations of software are becoming more and more complex. Therefore, the memory technology has become one of the important technologies in the semiconductor industry. In general, memory can be classified into volatile memory and non-volatile memory depending on the type of data stored. The dynamic random access memory is a kind of volatile memory, which consists of a memory cell. Each memory cell is mainly composed of a transistor and a capacitor, and each memory cell is electrically connected to each other by a word line (WL) and a bit line (bit Une, bl). . 1 is a schematic cross-sectional view of a conventional dynamic random access memory. 2 The dynamic random access memory of the present invention includes a substrate (10), a capacitor 110, and a transistor 120 disposed laterally. The substrate 1 has a trench 102' and the capacitor 11 is located within the trench 1〇2. The capacitor ιι〇 includes a lower electrode 104, a tortoise layer, and an upper electrode. Transistor I]. The configuration is on the substrate 100. The transistor 120 includes a gate 124, a drain region 122b, and a source region 122a. The drain region 122b and the source region 122a are disposed in the substrate 1 on the side of the gate 124. The drain region of the transistor 12 is connected to the substrate 1 through the buried conductive strip 13 形成 and the capacitor 11 形成 formed in the substrate 1 2009 6 200901380 2005-0108 22658 twf.doc/n 122a The pole 108 is electrically connected, and the source location is 7G line contact window 14〇. The random access memory is arranged such that the capacitor 110 and the horizontally-arranged 元-element _140 correspond to different positions of the substrate m, respectively. That is to say, the 〇〇 〇〇 , the transistor 120 and the bit line contact window 140 respectively occupy; == P sub-area, so it can be limited by _ s per unit area. Even though the technique is refined and the line width of the piece is small, but the limited community configuration, the increase in component accumulation is still limited. Plastic I Therefore, how to make more components in a limited space without affecting the size of the components to improve the component accumulation and wafer usage is an urgent problem to be solved. SUMMARY OF THE INVENTION The present invention provides a dynamic random access memory having a coaxial vertical arrangement of memory cells capable of increasing cell density and improving component performance. The present invention provides a method for fabricating a dynamic random access memory, which can improve the number of memory cells that can be produced per unit area, and thus can achieve the purpose of improving component accumulation. The present invention proposes a dynamic random access method. Memory, which includes a semiconductor, a bottom, a capacitor, and a transistor. A plurality of columnar structures are arranged on the semiconductor substrate. Each of the columnar structures includes an insulating layer, a semiconductor layer and a semiconductor protrusion from the semiconductor substrate from bottom to top. The capacitor includes a lower electrode, an upper electrode, and a ϋ ϋ a 钨 tungsten surrounding semi-conducting 200901380 2005-0108 22658twf.doc/n . The lower electrode is disposed in the __, of the subtraction structure. The upper electrode is disposed in the semiconductor layer. Capacitor dielectric 3 between the pen and the upper electrode. The transistor includes an open electrode, a first; a "dipole-doped region. The second region of the semiconductor protrusion (4) is disposed in the semiconductor protrusion under the gate, and is coupled to the semiconductor having the second doped region disposed above the gate In the embodiment of the present invention, the semiconductor protrusion of the above-mentioned semiconductor protrusion is, for example, smaller than the size of the semiconductor layer. In one embodiment of the present invention, the dynamic random access function is disposed in the transistor. Above, and in combination with the second doping; in one embodiment of the invention, the material of the contact window is, for example, in an embodiment of the invention, wherein the gate is, for example, a body protrusion. In the present invention - In an embodiment, the transistor further includes an idle layer disposed between the gate and the semiconductor protrusion. In an embodiment of the invention, the dynamic random access memory further includes a spacer disposed on the semiconductor protrusion. The sidewall, and above and below the gate, in one embodiment of the invention, the capacitor dielectric layer is, for example, a composite dielectric layer. In one embodiment of the invention, the composite dielectric layer is, for example, Is an oxide/nitride layer or an oxide/nitride/oxide (ΟΝΟ) layer. In one embodiment of the invention, the material of the lower electrode is, for example, 8 200901380 2005-0108 22658twf.doc/n doping In the embodiment of the present invention, the material of the upper electrode is, for example, doped yttrium. In the embodiment of the present invention, the material of the above-mentioned gate is, for example, Ο ο The method of accessing the memory is to provide a substrate on which the towel has been formed with a hiding layer. Then, a part of the wire and the insulating layer are used to form a channel in the form of a scarf, and the substrate is under the insulating layer. Then, a dielectric layer is formed on the side of the trench. The lower electrode is filled in the trench, and the upper surface of the lower electrode is lower than the surface of the substrate. Then, part of the substrate is removed to form a width above the lower electrode. It is larger than the width of the trench, and the adjacent two openings in the substrate have a protrusion. In the ion implantation process, an upper electrode is formed in the substrate between the trenches of the 2 、 and the remaining insulating layer. Later 'under the prominence Forming a first doped region, and forming an open sidewall on the first doped region in sequence; = a gate and a gate. Thereafter, a second doped region is formed in the protrusion above the gate. In one embodiment of the invention, the method of fabricating a dynamic random access memory further includes forming a second doped region, forming a contact with the second doped region, for example, in the present invention. In one embodiment, the forming of the opening and the protruding portion is, for example, forming a mask layer on the substrate. Thereafter, the first patterned photoresist layer is formed on the substrate. The first patterned photoresist layer Formed above the substrate between the adjacent two, and the width of the first patterned photoresist layer is, for example, 9 Ο u 200901380 2005-0108 22658 twf.doc / n is smaller than the width of the substrate between adjacent two trenches. The resist layer is a mask' that removes the exposed mask layer from the substrate, the lower electrode. The first patterned photoresist layer is then removed. The violent road is oxygen-extracting - the above-mentioned phase material is, for example, a part. In the example of the month of the moon, the above-mentioned gates are, for example, surrounded by protrusions and two real-cuts, and the latter is formed after the formation of the 帛-_ region, and the lower spacer is formed on the side wall of the opening. For example, it is a method of forming a spacer below the entrance opening, and a layer of a secret dielectric material. The dielectric material layer is, for example, filled with a dielectric material layer to form a second mesh photoresist layer. The width of the photoresist layer is, for example, smaller than the width of the opening. 3 The exposed portion of the dielectric material is removed: The layer is, for example, the lower spacer. Then, the width:: ί=ditch: the second patterned photoresist layer is as follows: the upper surface of the spacer below the surface t is first ===, the upper=gate_forming method, for example, layer' Covering the lower gap, 10 200901380 2005-0108 22658t%vf.doc/n The upper surface of the protrusion. In an embodiment of the invention, the upper spacer is formed on the sidewall of the opening after the gate is formed and before the second doped region is formed. The upper gap wall covers, for example, the gate. In the embodiment of the present invention, further comprising forming a liner on the sidewall of the trench after forming the dielectric layer and before forming the lower electrode. In an embodiment of the invention, the medium is a thermal oxidation treatment. Example of Forming Four Layers - In one embodiment of the present invention, the above-mentioned ions from X are, for example, N-type ions. Implantation of the Difficult Implantation Process In one embodiment of the invention, the doped polycrystalline spine is described. The material is, for example, implemented in the present invention, wherein the gate (four) material is, for example, the sinusoidal random access memory of the present invention, and the capacitor is formed in the substrate, and then the capacitor is used for the capacitor. The crystal, and then the second of the transistor, is vertically disposed in the fabricated dynamic random access memory. And the contact window is arranged in a coaxial vertical configuration, and the transistor is arranged on the surface of the wafer and is arranged in a right-handed manner, which can be formed in the substrate, and adjacent thereto, the capacitor electrode疋 Through the semiconductor base 200901380 2005-0108 22658twf.doc/n bottom coupling, that is to say several dynamic random access memory cells use the lower electrode. Therefore, the present invention can greatly increase the surface area of the lower electrode of the capacitor and effectively increase the capacitance of the electric grid, thereby facilitating the fabrication of the small-sized memory element and improving the performance of the element. In order to make the above-mentioned remainder and superiority of the present invention more secret, the following is a detailed description of the present invention. [Embodiment] ❹ A 2A to FIG. 20A is a top view showing the flow of the operation of the memory access memory according to an embodiment of the present invention. 2B to 2B are schematic cross-sectional views taken along line 1_1 of Figs. 2A to 20A. First, referring to FIG. 2A and FIG. 2B simultaneously, a substrate 2 is provided, and the substrate 200 is, for example, a substrate of a silicon-on-insulator (s). The material of the substrate 200 is, for example, a P-type semiconductor. That is, the substrate 2, for example, germanium is composed of the semiconductor substrate 200a, the insulating layer 200b, and the semiconductor body 00c. The insulating layer 2〇〇b is disposed between the semiconductor substrate 200a and the semiconductor body 2〇〇c, for example, to separate the semiconductor substrate 2(8)& and the semiconductor body 2 for fabricating the device, thereby reducing power consumption, = Low component error and improved component performance. The material of the semiconductor substrate 2A and the semi-body body 200c is, for example, a p-type semiconductor, which is, for example, a small amount of boron or other suitable trivalent atom added to the crucible. The material of the insulating layer 200b is, for example, oxidized stone. Then, a pad oxide layer 2, a pad nitride layer 204, and a mask layer 206 are sequentially formed on the substrate 200. The pad oxide layer 202 is, for example, a hafnium oxide layer or other suitable oxide layer. The pad nitride layer 204 12 200901380 2005-0108 22658twf.d〇c/n is, for example, a tantalum nitride layer or other suitable nitride layer. The mask layer 2〇6 is, for example, a b〇r〇silicate glass (BSG)/#. Of course, the mask layer 206 may be made of a material other than borosilicate glass, and a material having an appropriate etching selectivity may be selected. The formation method of the pad oxide layer 202 is, for example, a chemical vapor deposition method or a thermal oxidation method. The method of forming the pad nitride layer 204 and the mask layer 2〇6 is, for example, a chemical vapor deposition method. Thereafter, a patterned photoresist layer 208 is formed over the mask layer. After that, referring to FIG. 3A and FIG. 3B simultaneously, the photoresist layer 2〇8 is patterned as a mask, and an etching process is performed to remove the exposed mask layer 206, the pad nitride layer 204, and the pad oxide layer 2〇2. . Accordingly, the patterned photoresist layer 2 (10) is removed. Next, the exposed mask body 206 is used as a mask to remove the exposed semiconductor body 200c to expose the insulating layer 2〇〇b to form a trench 210 above the insulating layer 2〇诎. On the other hand, the remaining semiconductor bodies 2〇〇c are, for example, columnar structures 2〇〇c which are arranged in a matrix. By using the above-mentioned mask layer as a mask, it is possible to avoid the problem of rounding at the corners of the pad nitride layer after the process of the finishing process. 〇 A special succinct 疋, in the top view of the present embodiment (as shown in Fig. 3), each block of the cover screen han 206 has a circular shape. In other embodiments, the shape of each of the mask layers 206 may be, for example, elliptical, (four), square, or other shapes, and the technology has a clear need for financial know-how. When the columnar structure is viewed, it corresponds to the shape of the upper layer of the mask layer 2G6, and the columnar shape can be a columnar shape, a cylindrical shape or a corresponding polygonal column shape.

O ϋ 200901380 2005-0 ] 08 22658twf. doc/n Bean 2: B: T according to Figure 4A and Figure 4B ' remove the mask layer 206, ditch; ίο 二式钱刻法 or wet money engraving. Thereafter, a dielectric layer 212 is formed on the sidewall of the trench 210. The impurity layer f or f is the appropriate layer. Dielectric layer: Shape: two = 匕 The surface of the sidewall is thermally oxidized to form an emulsifying stone layer bounded by the trenches 210 and 2(8). Then, a liner layer 214 is formed on the surface of the trench 210. The layer 214 is, for example, a nitride layer, which is formed by, for example, a chemical (10) and a paste, and a mask layer 216 is filled in the trench 2H. The mask layer 21-like structure 200c, the upper portion and a portion of the upper portion of the trench 21 are ^4. The material of the mask layer 216 is, for example, light.

It is the first to cover the columnar structures 200c, 21 by a spin coating method using a layer of mask material. The mask in the middle: one layer of the mask material is located in the trench. Then, referring to FIG. 5 and FIG. SB, the lining layer 214 and the dielectric layer 212 exposed by the mask layer 216 are used. The method of removing the liner 214 ^ 曰 212 is, for example, a seat type residual method. The removed (4) surface and the top surface of the dielectric layer 212 are, for example, approximately equal to the upper surface of the mask layer 216. Next, the mask layer 216 is removed and moved 14

Ο 200901380 2005-0108 22658twf.doc/n The method of division is, for example, dry-type engraving. After that, please also show that < A t is located in , , :r; giant 2ω A and FIG. 6B, and an etching process is performed to remove the liner 214 located at the bottom of the trench 210 to form an annular liner 214. Connected | $2〇〇c sidewalls The money 'department' is removed by the remaining sounds of 2丨4 i g by the trenches 210 exposed by ^214 as the mask, ?ηπκ bar edge layer 200b. The method of removing the bottom liner layer 214 and the insulating layer 2_ is, for example, a dry (four) method. Then, referring to Fig. 7A and Fig. 7B at the same time, the lower electrode 218 is inserted into the trench 2 early. The lower electrode 218 μ is filled into the upper surface of the upper portion of the upper portion of the upper layer 18, for example, approximately the same as the south surface of the upper surface of the lining 214, and the material thereof is, for example, potassium-doped polycrystalline stone. The shaft method of the lower electrode 218 is, for example, a hybrid gas vapor deposition method to form a conductor layer (not shown) on the substrate 200, which conformably covers the columnar structure 200c and fills the trench 21〇+. After that, the process of returning to the last name is performed, and the conductor layer is etched back to expose the upper part of the trench 21〇. It is worth mentioning that since the bottom of the trench 210 is connected to the semiconductor substrate 2〇〇a under the insulating layer 2〇〇b, the lower electrodes 218 formed in the adjacent trenches 21〇 can be connected to each other by the semiconductor substrate. 2〇〇a electrical connection. That is to say, a plurality of capacitors formed in the subsequent substrate 200 share a lower electrode. Taking the test' Referring to Figures 8A and 8B simultaneously, another layer of mask layer 220 is formed on the substrate 200. The mask layer 220 conformally covers the columnar structure 2〇〇c' ' and fills the trench 21〇. The material of the mask layer 22 is, for example, oxidized stone or other suitable material. After the mask layer 220 is formed, a chemical mechanical polish (CMP) method is also selectively performed to planarize the surface of the mask layer 220. Thereafter, a patterned photoresist layer 222 is formed over the mask layer 15 200901380 20U5-U1U8 22658twf.doc/n 220. The projected position of the patterned photoresist layer 222 is, for example, corresponding to the center of the columnar structure 2〇〇c, and the width of the patterned photoresist layer 222 is, for example, smaller than the width of the columnar structure 200c. Then, referring to FIG. 9A and FIG. 9B simultaneously, the patterned photoresist layer 222 is used as a mask to remove the exposed mask layer 22, the pad nitride layer 2〇4, the pad oxide layer 202 and a portion of the columnar structure. 200c, to form an opening 224. The bottom of the opening 224 is, for example, exposed to the top of the liner 214 and the lower electrode 218. The opening : 224 is formed, for example, on the trench 21 , and the width of the opening 224 is, for example, the width of the trench 210 . That is, the bottom of the opening 224, for example, also exposes a portion of the columnar structure 2〇〇c. Further, after the opening 224 is formed, the upper portion of the columnar structure 200C' is formed, for example, by a projection 225 which is sandwiched by the adjacent opening 224. Continuing with reference to Figures 9A and 9B, the patterned photoresist layer 222 is moved, and then a liner oxide layer 226 is formed on a portion of the surface of the opening 224. The liner oxide layer 226 is, for example, exposed to the top surface of the liner layer 214 and the top surface of the dielectric layer 212. The material of the lining oxide layer 226 is, for example, oxidized stone or other suitable oxide, and the forming method thereof is, for example, a thermal oxidation method. Referring to the ® 10A and FIG. 10B simultaneously, an ion implantation process is performed, and a columnar structure 2〇〇c under the opening 224 forms an implantation region. Ion implantation The human ions implanted in the process are, for example, N (tetra), such as the clock (four). Ion Implantation = If multiple implants are used, and _ no _ implant energy to make the implants to different degrees of twist. The ion= and concentration, implant angle and implant energy used in the ion implanting process towel are adjusted in this technical field by the knowledge of the skilled person. 16 〇ϋ 200901380 2005-0108 22658twf.d〇c/n Bu, after _ yuan into the ion implantation process, 1 more selectively enters the post-ion, into (p0st i〇n lmp)_ati〇n) The tempering is performed to restore the structure and electrical properties of the surface atoms and to distribute the ions appropriately in the columnar structure 2'. Due to the columnar structure theory, the material is, for example, a semiconductor stone, after the columnar structure 2〇〇c after the ion implantation process, the layer is thus two == two mediation - _ lower = doping =: ? '= The formation method of ::: G of G_5 is, for example, performed at 10:3 and the t ion is, for example, an N-type ion having a concentration of, for example, 1 〇 Cm-H-3. Ion === amount and implant angle, so that N-type ions can be implanted in ^ ^ 225. After the above ion implantation process is completed, the tempering process of ion implantation after the line is further enabled to restore the junction of the surface atoms. The ions can also be appropriately distributed in the lower portion of the protruding portion. In the embodiment, the material of the protrusion 225 is, for example, a P-type semi-conducting layer: the doped region 25 〇 implanted ions are, for example, ν-type ions. In the case of t, the material of the protrusion 225 can also be a body', and the implanted ions of the doped region 250 can correspond to the visual process requirements of the general knowledge in the field of technology; the county and the month simultaneously refer to FIG. 12A and FIG. 12B. The oxide layer formed on the bottom of the opening is formed by a layer of dielectric material, and the material of the dielectric material layer 228 is filled with oxygen, for example, by oxygen cutting. Or other materials' forming method is, for example, chemical vapor deposition. Further, ς ' can also selectively perform surface planarization of the chemical mechanical dielectric material layer 228. Thereafter, a patterned photoresist layer 23() is formed on the dielectric layer 228. The position of the Ο 例如 is, for example, at the center of the ditch (10) and the opening 224. The width of the same as 0 == is, for example, smaller than the width of the opening, and is large: Next, please refer to FIG. 13A and FIG. The mask will expose a portion of the dielectric material layer 22 曰::. In an embodiment, the material of the mask layer 22 is, for example, 2 〇 = can be removed by dry correction: and ^ =, the layer of the electrically conductive material 228 is not removed to expose the bottom of the opening 0 224 Instead, a small portion of the dielectric material layer 228 is left between the patterned photoresist layer 23 and the protrusions 225 as the lower spacers 228a. The upper surface of the lower spacer 228a is, for example, lower than the doped region 25A', and the second patterned patterned photoresist layer 23. Remove. After that, the part 2 ^ removal method such as the H-cut method. After the partial lining of the ruthenium oxide is removed, the upper surface of the remaining lining oxide layer 226, for example, the upper surface of the dam wall 228a has the same height.疋/, lower gap/after, please refer to FIG. 14A and FIG. 14B simultaneously, and the second electric layer 232' is used as a gate dielectric layer on the protruding portion side. The material of the dielectric layer 232 is oxygen-cut, and the green color thereof is, for example, a chemical gas accumulation method or a thermal oxygen method. A layer of conductive material 234 is then formed over the substrate 200 to conformally cover the pad nitride layer 204, the dielectric material layer 228, and the dielectric layer 232. The material of the conductor material layer 234 is, for example, a doped polysilicon, a metal such as tungsten, copper, a copper-containing alloy or a tungsten-containing alloy, or a metal halide or the like, which is formed by, for example, a physical vapor deposition method. Further, after the conductor material layer 234 is formed, a chemical mechanical polishing method may be selectively performed to planarize the surface of the conductor material layer 234. 〇 Ο 同 同 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 A method of removing a portion of the conductor material layer 234 is, for example, a dry etching method. The gate 23 is formed, for example, above the lower spacer 228a. The gate 2343 is, for example, between the dielectric layer 232 and the dielectric layer 228 and surrounds the protrusion 225. The upper surface of the gate 234a is, for example, lower than the upper surface of the protrusion 225, and the lower surface of the gate 234a is, for example, lower than the upper surface of the doped region 250. It is to be noted that, referring to the top view shown in FIG. 15A, the pole 234a is, for example, an elongated structure surrounding the protrusion 225 so that the gates 234a of the side walls of the respective protrusions 225 in the longitudinal direction can be mutually formed. + The word line formed in the dynamic random access memory. (4) Next, please refer to Figs. 16A and 16B, and a layer 236 is provided on the substrate 200. The spacer material layer 236 is, for example, a compliant nitride layer 2 〇 4, a dielectric layer 232, a gate 23, and a material such as oxygen cut. Further, the H i forming method is, for example, chemical vapor deposition. law. In addition, after the formation of the spacer material layer 236, the chemical mechanical polishing method may be further performed by the step selectivity 19 200901380 2005-0108 22658twf.d〇〇/n ^, so that the surface of the spacer material layer 236 is flattened. Referring to FIGS. ΠΒ and ΠΒ, an etch back process is performed to remove the spacer material layer 236 to form the upper spacer 23, and the upper portion 236a covers the gate 234a. In the embodiment, since the material of the dielectric material layer and the material of the spacer material layer 236 is, for example, the same as the oxide oxide layer 28 = part of the spacer material layer 236, the exposed dielectric material layer is on the surface. The electrical layer 232 is also removed at the same time such that the upper surface of the dielectric layer 232 7 and the upper spacer 23 & upper surface are approximately equal but lower than the upper surface of the protrusion 225. r Guangran t Please refer to FIG. 18A and FIG. 18B at the same time, and the pad nitride layer is a dry paste method or a wet method. Thereafter, the f portion forms the formation of the #杂 region 252 ° erase region 252 5 :=亍f: implantation process. The implanted ions are, for example, N-type ionization processes, for example, by different deniers. Ion implantation: The structure of the atom: the material of 225 can also be an N-type semiconductor, which can be a P-type ion. The structure formed by the L hetero-region 2 5 2 implanted from the configurating step is a vertical sputum transistor. Vertically arranged lightning, π soil and extremely moving. The gate 234a, for example, has a vertically arranged surrounding gate, such as a transistor in the longitudinal direction, 20 200901380 2005-0108 22658twf.doc/n as a character line of a subsequently preformed dynamic random access memory Used to pick up memory cells. After that, please refer to FIG. 19A and FIG. 19Β simultaneously to remove the pad oxide layer 2〇2. Accordingly, a conductor layer 238 is formed on the substrate 200, and the conductor layer conformally covers the columnar structure 200c', the dielectric layer 232, and the gap material layer 236. The material of the conductor layer 238 is, for example, a metal material such as tungsten, a copper-containing alloy or an age-containing gold, and the like is formed by, for example, a vapor deposition method. Further, after the conductor layer 238 is formed, a chemical mechanical polishing method can be selectively performed to planarize the surface of the conductor layer 238.

随之 Accordingly, please refer to FIG. 20A and FIG. 2B simultaneously, and the conductor layer is shifted to form a contact window tear on the protrusion 225. The contact window 2 is torn: for example, a patterned photoresist layer, *: 先 is formed over the conductor layer 238, and the patterned photoresist layer covers the body layer 238 above the protrusion 225. The exposed conductor layer is then removed by patterning the patterned impurity layer and using dielectric material = 228 as the termination layer. The remaining conductor layer 238 is, for example, located at the projection 22^, and the miscellaneous region 252 serves as the contact window 238a. The contact window 23^ = a gap is formed over the dielectric material layer 228, for example, and a second 40 is implanted in the gap. The inner dielectric layer 240 is formed by passing adjacent two contact windows, for example, by chemical vapor deposition. The invention is not intended to limit the present invention, but only serves as a plurality of manufacturing methods for the mobile grabber access memory. 21 200901380 2005-0108 22658twf.doc/n FIG. 21A is an embodiment of the present invention. The figure shows a schematic diagram of the structure of the dynamic random memory. Figure 21B is a cross-sectional view taken along line Ι-Γ in Figure 21A. Referring to Fig. 21A and Fig. 21B, the dynamic random access memory 3GG package conductor substrate of the present invention, the vertical arrangement of the transistor and the capacitor 32〇1 container 320 are disposed on the semiconductor substrate 3〇2. The band crystal 3K) is disposed above the capacitor 32A, and is disposed with a contact port 33〇 above the capacitor 3 电 u transistor 310, and is coupled to the transistor. The semiconductor substrate 302 is provided with a columnar structure 3〇4 including a tree layer a from the bottom and a semiconductor layer; and an outlet 304e. The size of the semiconductor protrusion 3 is, for example, smaller than the size of the layer 304b. The material of the semiconductor substrate 3, 2, and the semiconductor layer 3_ with the conductor projecting portion 3G4e is, for example, a p-type turn. In the upper view of Fig. =, the top view of the columnar structure tears ^: that is, the columnar structure is, for example, cylindrical. However, in other embodiments, the structure 304 may also be cylindrical, rectangular, or the like. </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The lower electrode 322 is disposed between the adjacent two dendrites 3. 4 and 夂It is connected to 3〇2. The material of the lower electrode 322 is, for example, adulterated:. The upper electrode 324 is disposed on the semiconductor layer 3〇4b. The material of the upper electrode is, for example, doped stone. The capacitor dielectric layer 326 is disposed between the power supply 22 200901380 2005-0108 22658 tw.d〇c/n pole 322 and the upper electrode 324. The capacitor dielectric layer 326 is, for example, a complex

The electric layer is composed of a nitride layer 326a and an oxide layer 326b, and the oxide layer 326b is disposed, for example, on the sidewall of the semiconductor layer 3, and the nitride layer 326a is disposed between the lower electrode 322 and the oxide layer 2, for example. . In other real films, the capacitor dielectric layer 326 is more likely to be such as an oxygen layer, a nitride layer or a commonly-used oxide oxide/nitridite eve/oxidized oxide 〇 (〇 °° The material and thickness of the electrical layer 326 are not stored in the real

The embodiment shows that there is a general knowledge in this technical field, which can be adjusted according to its needs. The vertically arranged transistor 3U) includes a via 312, a doped region (10), and a doped region 3Ub. The gate 312 is disposed on the side wall ' of the semiconductor projection paper and surrounds the semiconductor protrusion 3〇4c. The upper surface of the gate 312 is lower than the upper surface of the doped region 314b, and the lower surface of the gate 312 is, for example, 疋, ',, /, the upper surface of the doped region 314a is equal, or is located on the doped region 31 such as the upper surface. Near and below. The gate 312 is, for example, a long strip structure, electrically

The transistor 310 of the line constitutes a dynamic random access memory 300-shaped line. In the present embodiment, the gate 312 is, for example, a longitudinal strip ', a port. The material of the gate 312 is, for example, doped (four), metal such as a crane, a copper alloy or a bearing alloy, or a gold alloy. In addition, the ΪΓ 10 further includes a gate dielectric layer 316 disposed between the gate 312 and the half body portion 304c and surrounding the semiconductor protrusions 3〇4c. The doped region 314a and the doped region 314b are respectively disposed on the semiconductor protrusion and the upper and lower ends. The doped region 314a is disposed in the half-dog-out neighbor 304c below the gate 312 and coupled to the upper electrode 324; the doped region 31 is on the top of the gate 312. Feng Hao set up, A 330 consumption. On the other hand, the gate 3H3, the middle, and the contact window 3 shirt, in order to isolate the gate 312 and the upper electrode, the touch can be touched. If there is J, the upper spacer 318b is disposed to be separated, and the dielectric layer is disposed. 317, to prevent the interpoles 312 on the two walls from contacting each other. '^体大出彳304c side

The contact layer 330 of the C o is, for example, above the columnar structure, and is different from the doped region 314b, and the material of the copper material, such as tungsten, copper, or copper 330, such as the contact window 330 is, for example, With or with crane alloy. And the age of the adjacent ones. The inner dielectric layer 332 has an inner dielectric layer 332 to separate the adjacent dielectric 2; the material of the electric current: 32 is, for example, borosilicate glass or its position d=== is disposed above the gate 312. u connect. The bit line described above is, for example, a vertical configuration, and in the present embodiment, the closed-cell example dynamic random access memory 30 is in a horizontal configuration. Therefore, between the character ', and the mother cell of the bit line, a contact transistor can be formed by forming a transistor, and then forming a vertical alignment above the electric shock U to form a contact window above the random access area. Capacitors, transistors, and 'windows, the configuration of the cell has a more (four) straight configuration' can be a more versatile cross-sectional area, so that 24 f per unit surface in the wafer: o 200901380 2005-0108 22658twf.doc/n The dynamic random access code that can be formed can achieve the result of improving the component accumulation. The number of hearts L will increase, and on the other hand, the mobile bear container of the present invention is formed in the substrate, and adjacent to the memory: the memory is pure, that is, several dynamic random ^^5^ The lower electrode is transmitted through the base electrode, so that the capacitance of the capacitor can be greatly increased, and the capacitance of the capacitor can be increased by a common electric effect. The surface area can be fabricated. (4) More (4) Small size memory definitions The present invention has been disclosed in the preferred embodiments as above. However, it is not intended to be used by any person who has a knowledge of the technology. In the spirit and scope of the month, The change and refinement of the invention is defined as the scope of the video material. [Simplified description of the drawing] FIG. 1 is a schematic cross-sectional view of a conventional random access memory cell. 2Α至图胤 is a top view of the production process of the dynamic 1-way access memory in accordance with the present invention. 2A to 20B are schematic cross-sectional views along the middle section of Fig. 2A to Fig. 2A. FIG. 21 is a schematic top view showing the structure of a dynamic random access memory according to an embodiment of the invention. Figure 21 is a cross-sectional view taken along line 14 of Figure 21; [Description of main component symbols] 100, 200: substrate 25 200901380 2005-0108 22658twf.doc/n 102, 210: trenches 104, 218, 322: lower electrodes 106, 326: capacitor dielectric layers 108, 324: upper electrode 110, 320: capacitors 120, 310: transistor 122a: source region ^ 122b: drain region ζ) 124, 234a, 312: gate 130: buried conductive strip 140: bit line contact windows 200a, 302: semiconductor substrate 200b 304a: insulating layer 200c: semiconductor body 200c', 304: columnar structure 202: pad oxide layer 204: pad nitride layer 206, 216, 220: mask layer 208, 222, 230: patterned photoresist layer 212, 232, 317: dielectric layer. 214: lining 224: opening 225: protrusion 226: lining oxide layer 26 200901380 2005-0108 22658 twf.doc/n 228: dielectric material layer 228a, 318a: lower spacer 234 : Conductor material layer 236: spacer material layer 236a, 318b: upper spacer 238: conductor layer 238a, 330: contact window 240, 332: inner dielectric layer 250, 252, 314a, 314b: doped region 300: dynamic random Access memory 304b: semiconductor layer 304c: semiconductor protrusion 316: gate dielectric layer 326a: nitride layer 326b : oxide layer t 27

Claims (1)

200901380 2005-0108 22658twf.doc/n X. Patent application scope: t kinds of dynamic random access memory, including: constituting county red ❹ (4) (4) The semiconductor layer and the conductor substrate include - insulating layer,: - capacitor, including: η, a galvanic connection === a gap between the doped structures, the semiconductor layer; and a transistor disposed between the lower electrode and the upper electrode, including: a 3-pole strain disposed on the semiconductor protrusion The side wall; the outlet is 'and coupled to the:: the semiconductor protrusion below the pole. The #L hetero-region is disposed above the closed pole of the semiconductor issue. The dynamic random access memory of the item is as small as the size of the semiconductor layer.趱, further comprising a contact, the dynamic random access memory of the first item, the second doped region: the contact window is disposed above the transistor, and the dynamic randomization of the three items is The material that takes the memory touch* includes tungsten 28 200901380 2005-0108 22658twf.doc/n 5. If the patent application circle is the first body, the gate surrounds the semiconductor to return to the dynamic random access memory. 6. If applying for a patent Fan Yuan's first -1 out. The body further includes a gate between the dynamic random access memories described in item %a. The electric θ is disposed at the gate and the semiconductor protrusion 7. As described in the 范围Lj body of the patent application, a gap wall is included, and the dynamic random access memory of the 认 认 所 所 34 is above and below the gate On both sides. The semiconductor protrusion side wall 'and the bit 8. As claimed in the patent scope body, wherein the capacitor dielectric ~ # - riding the dynamic random access memory 9. If the patent application is the first electrical layer. The composite, wherein the composite dielectric/oxide layer. θ 虱 虱 / 氮化 氮化 氮化 氮化 氮化 氮化 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. 10. The material of the upper electrode in the dynamic random access memory device described in the above paragraph includes the doped stone. 12. The method of claim 1, wherein the material of the gate comprises a method for manufacturing a random access memory of a tungsten random slave memory, comprising: a prism for a substrate, wherein the substrate has been formed with — Removing a portion of the substrate and the insulating layer, a 'Guang 2' channel, to form a plurality of trenches in the substrate to violently exit the substrate below the insulating layer; forming a dielectric layer on sidewalls of the trenches :, 29 200901380 2005-0108 22658twf.doc/n filling the trench with a lower electrode, the upper surface of the lower electrode is lower than the upper surface of the substrate; removing part of the substrate, forming a majority above the lower electrode The opening of the opening is larger than the width of the trenches, and the adjacent two openings in the substrate are sandwiched/projected; an ion implantation process is performed, adjacent to the trenches An upper electrode is formed in the substrate on the remaining insulating layer; a first doped region is formed under the canine portion, and the first doped region is coupled to the upper electrode; The open sides of a doped region Sequentially forming a gate dielectric and a gate electrode; and the projecting portion is formed on the gate of the above - the second doped region. 14. The method of fabricating a dynamic random access memory according to claim 13, further comprising forming a contact window on the substrate after forming the second doped region Miscellaneous area handle. 15' The method for forming a dynamic random access memory as described in claim 13 of the invention, the method for forming the opening without protrusions comprises: forming a mask layer on the substrate; forming a layer on the bottom a patterned photoresist layer, wherein the first patterned layer is formed above the adjacent two-year-old lining, and the width of the eucalyptus photoresist layer is smaller than the width between the adjacent two of the trenches a mask layer and the base patterned photoresist layer are masks, the exposed cover is removed until the lower electrode is exposed; and 30 200901380 2005-0108 22658twf.doc/n removes a patterned photoresist Floor. 16. For the method of making a dynamic inclusion as described in Item 15, wherein the material of the mask layer comprises oxidation =. Sub-five 5 恍 17. As described in the scope of application, the secret body described in the 13th item, wherein the pole surrounds the protrusion. Accessing the method 18. The method for manufacturing the dynamic random body described in claim 13 further includes forming a spacer on the sidewall of the opening when the f = 形成 is formed. 19. The method for fabricating a dynamic body according to claim 18, wherein the method for forming the lower spacer is to form a dielectric material layer on the substrate. a layer of dielectric material is filled in the chord: a second patterned photoresist layer is formed on the layer of dielectric material, and a photoresist layer is formed over the openings. The width of the layer is smaller than the plurality of layers. The width of the opening; only a patterned photoresist, the second patterned photoresist layer is a mask, and the layer of the dielectric material is removed, and the exposed exposed age is exposed. The gap; and, . &quot; an electrical material layer as the lower portion removes the second patterned photoresist layer. 2〇. If the manufacturing method of the 19th body of the patent application, the width of the movable random access memory trench is greater than the width of the patterned photoresist layer, such as the manufacturing method of the 19th body of the patent application scope, The upper surface of the movable random access memory spacer of the lower gate gap is lower than the upper surface of the first doping 200901380 2005-0108 22658twf.doc/n region. 22. The method of fabricating a dynamic random access memory according to claim 18, wherein the method of forming the gate comprises: forming a layer of a conductor material on the substrate; and removing a portion of the conductor material. The layer forms a gate covering the lower spacer wall. The upper surface of the idler is lower than the upper surface of the protrusion. ο ο. The dynamic random access memory according to claim 13, wherein the method further comprises: after the gate is formed, the second doped region is formed on the sidewall of the openings The wall, the upper gap covers the question pole. The dynamic random access memory method of claim 13 further includes forming the lower electrode after forming the dielectric layer; and forming a liner layer on the sidewall of the f trench. The dynamic random access memory method according to the item 13 of the invention, wherein the method for forming the dielectric layer comprises the dynamic random access memory type ion described in Item 13 of the manufacturer of the thermal oxidation body. /,, the ion implanted in the ion implantation process includes the N-body H&quot;, specifically the dynamic random access memory of the 13th. For example, the material of the lower electrode includes the doped polysilicon in the Shenzhi patent. . Body, where Lai (four) random access memory 32