TWI362721B - Dynamic random access memory and fabricating method thereof - Google Patents

Description

1362721 2005-0108 22658twf.doc/n IX. Description of the invention: * [Technical field to which the invention pertains] * The present invention relates to a memory element and a method of fabricating the same, and particularly to a dynamic random access memory Dynamic random access memory (DRAM) and its manufacturing method. V [Prior Art] • As the functions of today's computer microprocessors become more and more powerful, the programs and operations of software are becoming more and more complex, so the memory technology has become an important technology in the semiconductor industry. —. In general, memory can be classified into volatile memory and non-volatile memory depending on the type of data stored. The dynamic random access memory belongs to a kind of volatile memory, and ^ is composed of a plurality of memory cells. Each of the memory cells is mainly composed of a transistor and a capacitor, and each of the memory cells is electrically connected to the bit line (10) 丨B by a word line (WL). • Figure 1 is a schematic cross-sectional view of a conventional dynamic random access memory. Referring to FIG. 1, a conventional dynamic random access memory includes a substrate 1 , an electric grid 110 , and a laterally disposed transistor 120 . The substrate 100 has a trench 102 and the capacitor 11 is located within the trench 1〇2. The capacitor 11A includes a lower electrode 104, a capacitor dielectric layer, and an upper electrode 108. The transistor 12 is disposed on the substrate 100. The transistor 120 includes a gate 124, > and a polar region 122b with a source region 122a. The drain region 122b and the source region 122a are disposed in the substrate 10A on both sides of the gate I24. The drain region 122b of the transistor 120 is electrically connected to the source region 122a through the buried conductive strip 13〇 formed on the substrate 100 and the capacitor no. 6362721 2005-0108 22658twf.doc/n pole 108 is electrically connected. To the bit line contact window 140 disposed on the substrate 1 . The conventional dynamic random access memory is configured such that the capacitor 110, the laterally-arranged transistor 120, and the bit line contact window 140 correspond to different positions on the surface of the substrate v 1 , respectively, in a horizontal manner. That is, the capacitor 110, the transistor 120, and the bit line contact window 140 respectively occupy a portion of the area on the surface of the wafer, so the number of > memories that can be configured per unit area is limited. Even though the line width of the component can be gradually reduced by the technique, the increase in component integration is still limited by the above-mentioned configuration. Therefore, how to make more components in a limited space without affecting the size of the components to improve the component accumulation and the wafer usage rate is an urgent problem to be solved. SUMMARY OF THE INVENTION The present invention provides a dynamic random access memory having a memory cell having a coaxial vertical configuration capable of increasing cell density (ceU density) and improving component performance. The present invention provides a method for fabricating a dynamic random access memory, which can improve the number of memory cells that can be produced per unit area, and thus can achieve the purpose of improving component accumulation. The present invention proposes a dynamic random access method. A memory comprising a semiconductor substrate, an electric grid, and a transistor. A plurality of columnar structures are disposed on the semiconductor substrate. Each of the columnar structures includes an insulating layer, a semiconductor layer, and a semiconductor protrusion from the semiconductor substrate from bottom to top. The capacitor includes a lower electrode, an upper electrode, and a lower electrode disposed in the columnar region, and the connection is placed at ==:=::. Capacitor medium and second doped region. a closed-pole disposed in the semiconductor; a semiconductor-embedded portion of the first-doped region disposed under the gate; a semiconductor protrusion disposed above the gate with a doped-doped region = upper electrode °, for example; Body =: Dimensions of the above-mentioned semiconductor protrusions. In one embodiment of the invention, the dynamic random access etch contact is disposed above the transistor and is switched with the second doped region. In an embodiment of the invention, the material of the contact window is, for example, in one embodiment of the invention, wherein the gate is, for example, a body protrusion. In one embodiment of the invention, the transistor further includes a gate dielectric layer disposed between the gate and the semiconductor protrusion. In an embodiment of the invention, the DRAM further includes a spacer disposed on the sidewall of the semiconductor protrusion and on the upper and lower sides of the gate. In one embodiment of the invention, the capacitor dielectric layer is, for example, a composite dielectric layer. In one embodiment of the invention, the composite dielectric layer described above is, for example, an oxide/nitride layer or an oxide/nitride/oxide (germanium) layer. In an embodiment of the invention, the material of the lower electrode is, for example, 2005-0108 22658 twf.doc/n doped polysilicon. In an embodiment of the invention, the material of the upper electrode is, for example, a replacement stone. Tungsten In one embodiment of the present invention, the material of the gate is, for example, a method of fabricating a dynamic random access memory, which first provides a substrate in which an insulating layer has been formed. Then, a portion of the substrate and the insulating layer are removed to form a plurality of trenches in the substrate and expose the substrate under the insulating layer. Next, a dielectric layer is formed on the sidewall of the trench: then the lower electrode is filled in the fresh towel, and the upper surface of the lower electrode is lower than the upper surface of the substrate. Next, a portion of the substrate is removed to form an opening above the lower electrode. The width of the opening is greater than the width of the trench, and a plurality of protrusions are sandwiched between adjacent openings in the substrate. Subsequently, an ion implantation process is performed, and an upper NMOS is formed in the substrate between the adjacent trenches and the remaining insulating layer, and then a first doping is formed under the protruding portion, and is connected to the upper electrode. Next, the opening (4) on the first doping layer sequentially forms a gate dielectric and a gate. Thereafter, a second holding is formed in the protrusion above the opening. In the present invention, the memory is further included in the memory after the second doped region is formed, for example, coupled to the second doped region. Or Contact In the embodiment of the present invention, the above-described method of opening and protruding is, for example, forming a layer of transition on the substrate. After that, the fourth J-patterned photoresist layer. The first patterned photoresist layer is formed over the substrate between the trenches and the width of the first-type hybrid layer is, for example, ^ 1362721 2005-0108 22658twf.doc/n is smaller than the substrate width between adjacent trenches. Thereafter, the first pattern 2 is used as a mask: the exposed mask layer and the substrate are removed until the exposed electrode is exposed. Next, the first patterned photoresist layer is removed. Cerium Oxide In the embodiment of the invention, the material of the above-mentioned mask layer is, for example, a portion. In the embodiment of the present invention, the above-mentioned problem pole is, for example, surrounded by protrusions. In the embodiment of the present invention, it is further included to form the lower spacer before the formation of the first erasing region. "iff Invention-In the embodiment, the method of forming the lower spacer described above is to form a dielectric material layer on the substrate. Example of a dielectric material layer Ϊ a second patterned photoresist layer is formed on the dielectric material layer. The patterned photoresist layer is formed over the opening, for example, and the width of the second photoresist layer is, for example, smaller than the opening. width. Thereafter: the mask is a mask to remove a portion of the exposed dielectric material layer:: Width example: the second patterned photoresist layer described above is in the present invention - in the embodiment, the above is lower than the first blend The surface above the miscellaneous area. Upper surface example of the soil 1. In the embodiment, the above-described method of forming the gate is formed, for example, on a conductor material layer. Thereafter, a portion of the conductor material layer is removed to form a gate covering the lower spacer. Upper surface of the gate (4) 1362721 2005-OIog 22658tw-f.doc/n Surface above the protrusion. In an embodiment of the invention, the upper spacer is formed on the sidewall of the opening after the formation of the interpole and before the formation of the second doped region. The upper gap wall covers, for example, the gate. $(四)—In the embodiment, the lining is formed on the sidewall of the trench after forming the dielectric layer and before forming the lower electrode. For example, in the embodiment, the method of forming the dielectric layer described above is, for example, a thermal oxidation treatment. The ion implanted by the implanting process described above is, for example, a sputum ion. In one embodiment of the invention, the above-described Ray-doped polysilicon is used. The material of the electrode is, for example, a crane. In the present invention, the material of the above-mentioned gate is, for example, minus = month, and the manufacturing method of the memory access memory is formed by first == then forming a vertical configuration of the next day on the capacitor, and then The second mode of the transistor is incorporated in the fabricated dynamic random access memory. The configuration of the y touch and the contact window is vertical: the configuration of the second == has a smaller size on the surface of the wafer. Main -, illusion cut · area. That is to say, the number of dynamic random accesses that can be formed in the area of the mother branch increases, so that the degree of integration of components can be improved. . In addition, the dynamic random access in the present invention is formed in the substrate, and the electric thief is coupled through the edge of the phantom capacitor, which is connected to the bottom, that is, several dynamic random access memory cells. Share the electrode. Therefore, the present invention can greatly increase the surface area of the lower electrode of the capacitor and effectively increase the capacitance of the capacitor, thereby facilitating the fabrication of a small-sized memory element and improving the performance of the element. In order to make the above features and advantages of the present invention more obvious, the following

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments, together with the drawings, are described in detail below. [Embodiment] FIG. 2A to FIG. 20A are top views of a manufacturing process of a dynamic machine access s memory in accordance with an embodiment of the present invention. Fig. 2B is a schematic cross-sectional view taken along line 1-1 of Fig. 2A to Fig. 20A.

First, referring to Figures 2A and 2B, a substrate 200 is provided. The substrate 200 is, for example, a silicon on insulator (SOI) substrate. The material of the substrate 200 is, for example, a p-type semiconductor. That is, the substrate 2 is composed of, for example, a semiconductor substrate 2A, an insulating layer 2 rib, and a semiconductor body 200C. The insulating layer 2B is disposed between the semiconductor substrate 2A and the semiconductor body 200c, for example, to separate the semiconductor substrate 200a and the semiconductor body thin e for fabricating the device, thereby reducing power consumption and reducing component errors. And improve component performance. The semiconductor substrate 200a and the semiconductor main body, the material example of the 200c is #! > Type + conductor, which is, for example, boron added to V in Shi Xi or other suitable trivalent atom. The material of the insulating layer 2〇〇b is, for example, cerium oxide. Next, a pad idexide layer 202, a pad nitride layer 204, and a mask layer 206 are sequentially formed on the substrate 200. The pad oxide layer 2〇2 is, for example, a hafnium oxide layer or other suitable oxide layer. Pad nitride layer 2 Correction 12 v 1362721 2005-0108 22658twfd〇c/n Example = is a tantalum nitride layer or other suitable nitride layer. The mask layer 206 is, for example, a layer of b〇r〇sincate giass (BSG). Of course, the mask layer 2〇6 may be made of a material other than boron enamel, as long as a material having an appropriate selection ratio is selected. The formation method of the pad oxide layer 202 is, for example, a chemical vapor deposition method or a thermal oxidation method. The pad nitride layer 2〇4 and the mask layer are formed by, for example, chemical vapor deposition. Thereafter, a patterned photoresist layer 208 is formed on the mask layer 2〇6. After that, referring to FIG. 3A and FIG. 3B simultaneously, the photoresist layer 2〇8 is patterned as a mask, and an etching process is performed to remove the exposed mask layer 2〇6, pad nitride 204, and pad oxide layer 2. 〇 2. Accordingly, the patterned photoresist layer 2〇8 is removed. Then, the remaining mask layer 206 is used as a mask to remove the exposed semiconductor body 2GGe wire to expose the insulating layer, so as to form a trench 21 〇m over the insulating layer b, for example, the remaining semiconductor body is formed. The columnar structure 200c arranged in rows and columns. The use of the above-mentioned mask layer 2〇6 as a mask' can avoid the problem of rounding at the corners of the tantalum nitride layer 2?4 after the finish process. It is to be noted that in the top view of the present embodiment (as shown in Fig. 3A), each of the blocks of the mask layer 2〇6 has a circular shape. However, in other implementations, the shape of each mask of the mask layer 2G6 may be, for example, a _ shape, a (four), a square, or other miscellaneous, and the technical person skilled in the art may adjust it according to his needs. Of course, the shape of the columnar structure 2〇〇c corresponds to the shape of the mask layer eagle view, the columnar structure 20Ge, which may be a columnar, _ columnar or corresponding polygonal column 13 ubirn 2005-0108 22658twf .doc/n Basin Referring to Figure M and Figure 4B, the mask layer 206 is removed, such as a dry or wet type. Thereafter, a dielectric layer 212 is formed on the sidewall of the ^:. Dielectric layer 212 is, for example, a dielectric film layer that is oxidized. The dielectric layer 212 is formed by, for example, thermally oxidizing the sidewall surface of the private 210 to the oxidized stone layer of the trench 21 层. Then, on the surface of the trench 210

Forming layer 214. The layer 214 is, for example, a dielectric film layer of a nitride layer, which is formed by, for example, a chemical vapor deposition method. Alternatively, the lining layer 214 may be made of a material other than a nitride, such as a carbide or a nitrogen carbide seam, which has a different etching selectivity than the county layer.

Seventh, the mask layer 216 is filled in the trench 210. The mask layer is called the exit column structure to win, the upper portion and a portion of the lining 214 located in the upper portion of the trench 21G. The material of the mask layer 216 is, for example, a photoresist. The mask layer 216 is formed by, for example, a ruthenium-transfer coating method to form a mask (four) layer on the substrate (unknown), and the mask-cap column structure 200c' is placed after the trench 21G. In the ozone retroreflective manner, the column structure is removed, the upper mask material layer and a portion of the mask material layer located in the trench 210. 〃 Then, referring to FIG. 5A and FIG. 5B simultaneously, the exposed lining layer 214 and the dielectric layer 2U are removed by using the mask layer 216 as a mask. The method of removing the liner layer 214 and the dielectric layer 212 is, for example, a 钱 type of money engraving & The top surface of the removed liner 214 and the top surface of the dielectric layer 212 are, for example, approximately equal to the upper surface of the mask layer 216. Next, the mask layer 216 is removed, which is shifted by 14 - L JUZ / Z1 2005-0108 22658twf.doc / n. The method is, for example, a dry etching method. Thereafter, referring to Fig. 6A and Fig. 6B, the lining 214 at the bottom of the channel 2K) is applied to the columnar structure; the side is a lining 214 which is formed into a soil. Next, the remaining liner 214 is used as a mask to expose the insulating layer 200b. The method of removing the underlying liner layer 214 and the insulating layer 200b is, for example, a dry etching method.

1 Then, please refer to FIG. 7A and FIG. 7β simultaneously, and the height of the upper surface of the lower electrode 218 in the trench 21〇 is, for example, approximately equal to the degree of the lining layer, and the material thereof is, for example, a polycrystalline spine doped with a clock. . The method is formed by, for example, chemical vapor deposition prior to the base 200, forming a bulk layer (not shown) which conforms to the columnar structure c into the trench 21〇. Thereafter, a process of returning the ink is performed to etch back the conductor layer to expose the upper portion of the trench 210. It is worth mentioning that the bottom of the trench 21G is connected to the semiconductor substrate 2〇〇a of the insulating layer 200b, and thus is formed in the adjacent trench 21〇.

Underneath, 218 can be electrically connected to each other by a semiconductor substrate, and a lower electrode is used in a plurality of capacitors formed in the substrate 2A. σ /, Next, please refer to FIG. 8A and FIG. 8A simultaneously to form another mask f 22G on the substrate 2〇〇. The mask layer 220 conformally covers the columnar structure 2〇〇C 3' and is filled into the trench 210. The material of the mask layer 220 is, for example, yttrium oxide or other suitable material. After the formation of the mask layer 220, a chemical mechanical polish (CMP) method is also selected to planarize the surface of the mask layer 22A. Thereafter, a patterned photoresist layer 222 is formed over the mask layer 15 1362721 2005-0108 22658twf.d〇c/n 220. The projected position of the patterned photoresist layer 222 is, for example, corresponding to the center of the columnar structure 200c', and the width of the patterned photoresist layer 222 is, for example, smaller than the width of the columnar structure 200c. Then, referring to FIG. 9A and FIG. 9B, the exposed photoresist layer 222 is used as a mask to remove the exposed mask layer 220, the pad nitride layer 204, the pad oxide layer 202 and the partial columnar structure 200c, To form an opening 224. The bottom of the opening 224 is, for example, exposed to the top of the liner 214 and the lower electrode 218. The opening 224 is formed, for example, on the trench 21, and the width of the opening 224 is, for example, the width of the trench 210. That is, the bottom of the opening 224, for example, also exposes a portion of the columnar structure 200c. Further, after the opening 224 is formed, the upper portion of the columnar structure 2〇〇c' is formed, for example, by a projection 225 which is sandwiched by the adjacent opening 224. Referring to FIG. 9A and FIG. 9B, the patterned photoresist layer 222 is moved. Thereafter, a liner oxide layer 226 is formed on a portion of the surface of the opening 224. A liner oxide layer 226, such as germanium, exposes the top surface of liner layer 214 and the top surface of dielectric layer 212. The material of the oxide layer 226 is, for example, an oxide (tetra), and an oxide thereof, which is formed by, for example, a thermal oxidation method. Please refer to item 10Α and Figure 1〇Β for the ion implantation process. The columnar structure below the port 224 forms the implanted area. Ion implantation j implanted human ions, for example, a bribe, such as the clock. The ion implantation system is more than suspicion: it is suspected that the implanted energy is used to make the ions used in the ion implantation process. The amount of ions used in the above-mentioned ion implantation process is generally known as 1362721, 2005-0108, 22658 twf. Doc/n According to the above, after the ion implantation process is completed, the ionic tempering process can be selectively performed to restore the structure and electrical properties of the surface atoms. The ions are appropriately decorated in the columnar structure 200c'. Since the material of the columnar structure 200c is, for example, a semiconductor stone, the columnar structure after the ion implantation process can form a conductor material as the upper electrode of the capacitor. Columnar community

• Shi, to. The dielectric layer between the body layers 218 and the liner layer 214 are the capacitive dielectric layers of the S•$ capacitor. Of course, the thickness of the dielectric layer 212 and the thickness of the liner 214 can be adjusted as needed. Thereafter, referring to Fig. 11A and Fig. UB, a doping region 250 is formed on the lower portion of the protruding portion 2. The method of forming the doped region 250 is, for example, performing implantation. The implanted ions are, for example, N-type ions, and the concentration thereof is, for example, between 10 cm-3 and 10〇2〇cnf3. The ion implantation process is, for example, a dream, an implantation energy, and an implantation angle, so that the N-type The ions can be implanted in the output portion 225. After the ion implantation process is completed, the post-ion implantation tempering process can be selectively performed to restore the structure and electrical properties of the surface atoms, and the ions can be appropriately selected. The ground is distributed in the lower portion of the protrusion 225. In the present embodiment, the material of the protrusion 225 is, for example, a p-type semiconductor, and thus the implanted ions of the doped region 250 are, for example, N-type ions. Of course, in other embodiments The material of the protrusion 225 may also be an NJ half, a conductor, and the implanted ions of the doped region 250 may correspond to a p-type ion, and the technical field is adjusted by the general knowledge to the process requirements. Referring to FIG. 12A and FIG. 12B simultaneously, a re-etching process is performed to remove the liner oxide layer 226 formed at the bottom of the opening 224. Thereafter, a dielectric material is formed on the substrate 17 1362721 2005-0108 22658twf.doc/n 200 . Layer 228, and the dielectric material layer is filled. The material of the material layer 228 is, for example, oxidized stone or other composites. The forming method thereof is, for example, chemical vapor deposition. Further, after the formation of the electric material layer 228, the dielectric material can also be selected = The surface of the layer dog is flattened.: The rear 23〇= position, for example, the width of the channel 21〇 and the opening 2 = ίι::Γ: is, for example, smaller than the width of the opening σ 224 and the square is large: then 'Please refer to FIG. 13 and FIG. 13Β, ^ is the mask, which will expose part of the dielectric material layer 228 and =?:::, the mask layer 22. _ For example with =: the main ^ β ^ with a dry type of smoke tree can be - And removing. It is worthwhile that the second layer 228 is not removed to expose the opening 224; a small layer of dielectric material layer 228 is left between the patterned photoresist layer 230 and the protrusion 225 as a lower gap. The upper surface of the wall is, for example, removed from the upper surface of the doped region 25Q. After that, part of the lining oxygen "after the second layer is, for example, wet _^° in the removal portion", the upper surface of the oxidized wall is lined with two layers high: above (four) wall two Ϊ = with reference to Figure MA and Figure 14B' Coffee. As a gate dielectric layer. The material of the dielectric layer 232 is formed by a chemical vapor deposition method or a thermal oxygen method, and then a conductive material layer 234 is formed on the substrate 200, and is compliant. The padded pad nitride layer 204, the dielectric material layer 228, and the dielectric layer 232 are formed. The material of the conductor material layer 234 is, for example, a doped polycrystalline stone, a metal such as tungsten, copper, a copper-containing alloy or a tungsten-containing alloy, or a metal halide or the like, which is formed by, for example, physical vapor deposition. Further, after the formation of the conductor material layer 234, a chemical mechanical polishing method may be optionally performed to planarize the surface of the conductor reed 234. 9A Referring to FIGS. 15A and 15B, an etch back process is performed to remove a portion of the conductor material layer 234 to form the gate 234a. A method of removing a portion of the conductor material layer 234 is, for example, a dry etching method. The gate 234a is formed, for example, above the lower spacer 228a. The gate 234a is, for example, located between the dielectric layer 232 and the dielectric layer 228 and surrounds the protrusion 225. The upper surface of the gate 234a is, for example, lower than the upper surface of the protrusion 225, and the lower surface of the gate 234a is, for example, lower than the upper surface of the doped region 250. 4 inch, please refer to the top view shown in FIG. 15A. The gate 234a is, for example, an elongated structure surrounding the protrusion 225, so that the gate 234a of the sidewall of each of the holes 225 in the longitudinal direction can be Lightly connected to each other to form a word line in a subsequently formed dynamic random access memory. Next, please refer to Figs. 16A and 16B simultaneously to form a layer of material 236 on the substrate 2 . The spacer material layer 236 is, for example, compliant to cover the pad nitride layer 204, the dielectric layer 232, the gate 234a, and the electrical material layer 228. The material of the spacer material layer 236 is, for example, ruthenium oxide or other suitable dielectric material, and the formation method thereof is, for example, chemical vapor deposition. Further, after the formation of the spacer material layer 236, further improvement can be made 19 1362721 2005- A chemical mechanical polishing method is performed at 0108 22658 twf.d〇c/n to planarize the surface of the spacer material layer 236.

Please simultaneously refer to 17A and FIG. 17B to perform a return process to remove a portion of the spacer material layer 236 to form an upper spacer (10), and the upper spacer 236a covers the gate 234a. In an embodiment, since the material of the dielectric material layer 228 and the spacer material layer 236 is, for example, the same as the oxidized stone, the exposed dielectric material layer 228 and the removed portion of the spacer material layer are removed. Part of the dielectric layer 232 is also removed at the same time, so that the upper surface of the dielectric layer, the upper surface of the dielectric material layer 228, and the upper spacer 23 are equal to the upper surface but lower than the upper surface of the protrusion 225. . Then. At the same time of the month, the makeup picture 18A and FIG. 18B, the removal method of the yttrium nitride 204 is, for example, a dry wire or a magnetic enthalpy method. Thereafter, a doping region 252 is formed on the upper portion of the protrusion 225. The method of forming the doped region 252 is, for example, a hybrid process.植人轩勤 is an n-type ion' whose concentration is, for example, between l〇I8Cm-3 and 1〇2〇cm-3. Ion implantation

For example, the N-type knife is removed from the upper portion of the protrusion 225 by different implanting energy and implanting angle. In addition, the ion implantation process can selectively perform a post-ion implantation tempering process to restore the surface atomic structure and electrical H. The material of the 225 can also be large. The exit P can be p-type.导体!+conductor, and the doped region 252 is implanted away from the configuration: the structure formed by the above steps is a vertical corona. The configured transistor has a vertically arranged surrounding gate 234a, for example, in a lightly connected longitudinal direction. Each of the transistors, 20 1362721 2005-0108 22658twf.doc / n as a subsequent pre-formed dynamic random access memory word line for connecting the memory cells.

Thereafter, please simultaneously remove the pad oxide layer 2〇2 with reference to FIGS. 19A and 19B. Accordingly, a conductor layer 238 is formed on the substrate 200, and the conductor layer 238 conformally covers the columnar structure 20〇c, the dielectric layer 232, and the interlayer material layer 236. The material of the conductor layer 238 is, for example, a metal material such as tungsten, copper, a copper-containing alloy or a tungsten-containing alloy, and the like is formed by, for example, a vapor deposition method. Further, after the conductor layer 238 is formed, a chemical mechanical polishing method can be selectively performed to planarize the surface of the conductor layer 238. Accordingly, referring to Figs. 20A and 20B, the conductor layer 238 is patterned to form a contact window 238a over the protrusion 225. The formation method is, for example, forming a pattern photoresist layer before the conductor layer 238.

(not shown) and the photoresist layer covers 2% of the conductor layer above the protrusions 225. After that, the patterned photoresist layer is used as a mask, and the dielectric layer = 228 is used as a termination layer, and the exposed conductive layer is removed. The remaining conductor layer 238 is, for example, above the protrusion 225, and the region 252 is coupled to serve as a contact window. Contact window test 2 = TAT will form a gap, fill the door 2, book a in the gap. The inner layer, the tantalum layer 240, separates the adjacent two contact windows 238a to avoid the occurrence of a short circuit. The material of the inner dielectric layer 24 is a chemical glass, and the forming material thereof is, for example, a chemical vapor deposition method. It is known that the above-mentioned New Zealand example is used as one of various manufacturing methods of the dynamic random access memory of this month. 0 21 1362721 2005-0108 22658twf.doc/nf 21A : According to the present invention The schematic diagram of the structure of the dynamic random access memory is shown in the embodiment. Figure 21B is a schematic cross-sectional view taken along line 图-Γ of Figure 21.彳阳银 Please also refer to Figs. 21A and 21B, the dynamic random access memory 3G0 of the present invention includes a semiconductor substrate-mounted, vertically-disposed transistor training capacitor 32 〇. The capacitor 32 is disposed on the semiconductor substrate 3〇2. Christine 31〇 is placed above the capacitor 32〇 and with the capacitor 3

Above the transistor 310, a contact window 33 is further disposed and connected to the transistor. A columnar structure 3〇4 is disposed on the semiconductor substrate 302. The columnar structure 3〇4 includes an insulating layer 304a, a semiconductor layer 3〇4b, and a semiconductor output portion 304c from bottom to top. The size of the sheep conductor projections 3〇4c is, for example, smaller than the size of the semiconductor layer 304b. The semiconductor substrate 3, 2, the semiconductor layer, and the semiconductor protrusions are, for example, p-type semiconductors. In the upper view of Fig. 21A of the present embodiment, the shape of the upper view of the columnar structure 3〇4 is, for example, a circle.

The shape 'i.e., the columnar structure 304 is, for example, a shape. In other embodiments, however, the columnar structure 304 can also be an elliptical cylinder, a rectangular dome, or other polygonal column, which can be adjusted by one of ordinary skill in the art to meet its needs. The capacitor 320 includes a lower electrode 322, an upper electrode 324, and a capacitor dielectric layer 326. The lower electrode 322 is disposed in the gap 2 between the adjacent two columnar structures 3〇4 and is connected to the semiconductor substrate 3〇2. The lower electrode 32; 2 ❸ material is, for example, a polycrystalline germanium. The upper electrode 324 is disposed in the semiconductor layer 3 . The material of the upper electrode 324 is, for example, doped germanium. The capacitor dielectric layer 326 is disposed between the power source 22 4 1362721 2005-0108 22658 twf.doc/n pole 322 and the upper electrode 324. The capacitor dielectric layer is composed of, for example, a composite dielectric layer, and is composed of a nitride layer 326a and an oxide layer 3, and the intermediate oxide layer 326b is disposed, for example, on the sidewall of the semiconductor layer, and the nitride layer is disposed, for example. The lower electrode 322 is overlapped with the oxide layer. In the embodiment of the ft, the capacitor dielectric layer 326 can be, for example, an oxidized dream/nitriding oxide (ΟΝΟ) which is commonly used in oxidized stone.

The material and thickness of the capacitor dielectric layer 326 are not limited to the present invention. The transistor 31G, which is generally configured in the art, includes a closed electrode 312 and a doped region 31. As shown in the figure, the township 312 is disposed on the side of the semiconductor protrusion 304c.

Around the exit 304c. The upper surface of the gate 312 is at the upper surface of the doped region 314b, and the lower surface of the gate 312 is equal to the upper surface of the wide region 314a, or is located near the junction of the impurity-changing region 314a. The question electrode 312 is, for example, a strip-like structure, and constitutes a dynamic random access memory 300 in the electrical body 310'. In the present embodiment, the gate 312 is, for example, a longitudinal strip. The material of the steel=1 pole 312 is, for example, a rubbed polycrystalline stone, a metal such as a spin, a gold or a tungsten-containing alloy, or a metal consumable. In addition, a gate dielectric layer 316 is further disposed between the gate 312 and the semiconductor protrusions 3〇4c. The impurity region 3 is coupled to the doped region 314b, which is disposed in the semiconductor protrusion portion conductor portion 304c, respectively, and is connected to the half-up electrode 324 below the pole 3f4H pole 312; the doped region 314b is 23 1362721 2005-0108 22658twf.doc/ n The semi-conductor is placed above the gate 312, and the conductor is out of the 4 3〇4c, which is connected to the contact window. On the other hand, '3' (10) may be disposed under the gate 312 to isolate the gate 312 from contacting the upper electrode; and the upper gap 312 is provided with an upper gap through to isolate the gate from the contact window 33. Connected. Further, there is, for example, a tantalum layer 3' between the adjacent two semiconductor protrusions 3 G 4 C to prevent the adjacent two semiconductor protrusions 3 and the gates 312 on the side soil from coming into contact with each other. The contact window 330 is disposed, for example, in a columnar structure on the semiconductor protruding portion. All genus and miscellaneous areas 贱 _. The material of the contact window is, for example, tungsten, copper, a copper-containing alloy or a crane-containing alloy. And the adjacent _ window. The inner layer _ " electrical layer 332 to separate adjacent appropriate dielectric: material C material such as borosilicate glass or its bit Cl can also be placed above the contact window 330, such as it and the contact window 33g _ . The above bit line is, for example, perpendicular to the direction of the ^^^. In the present embodiment, 'closed 312 cases are dynamic, and the horizontal line is, for example, a lateral arrangement. Therefore, each of the memory cells of the memory 300 can be connected by a predetermined line and a bit line. In the method of fabricating the dynamic random access memory of the present invention, a vertical alignment is formed over the capacitor to form a contact window over the doped region of the transistor, and the Si is taken as a memory cell. The above-mentioned dynamic random access memory cell knows that the C body and the contact window adopt a coaxial vertical configuration, which can have a smaller cross-sectional area than the conventional one, so that the unit per unit surface 24 1362721 2005-0108 22658 twf.doc/n product in the wafer The internal tangible __ access record can achieve the effect of improving the component accumulation. In the third (three) increase, on the other hand, the dynamic random storage container of the present invention is formed on the base towel, and the adjacent capacitor: 'reading, its electrical connection' is also a random number of random access electric power, through the substrate Extremely, so it can greatly improve the lower electrode of the capacitor

Effectively increasing the capacitance of the capacitor is therefore more advantageous: the product can be fabricated. The present invention has been disclosed in the above preferred embodiments, and is not intended to be exhaustive or otherwise ^Not = the scope of protection of the present invention # 视 附 附 附 附 须 须 须 须 须 须 须 须 须 须 须 须 须 须 须

1 is a schematic cross-sectional view of a conventional dynamic random access memory cell. 2A to 20A are top views of a process of manufacturing a dynamic random access memory according to an embodiment of the invention. 2B to 20B are schematic cross-sectional views taken along line Ι-Γ in Figs. 2A to 20A. FIG. 21A is a schematic top view showing the structure of a dynamic random access memory according to an embodiment of the invention. Figure 21B is a cross-sectional view taken along line I-Ι of Figure 21A. [Main component symbol description] 100, 200: substrate 25 1362721 2005-0108 22658twf.doc/n 102, 210: trench • 104, 218, 322: lower electrode 106, 326: capacitor dielectric layer 108, 324: upper electrode • 110, 320: capacitor - 120, 310: transistor 122a: source region 122b. gate region 124, 234a, 312: gate 130: buried conductive strip 140: bit line contact window 200a, 302: semiconductor substrate 200b 304a: insulating layer 200c: semiconductor body 200c', 304: columnar structure 202: pad oxide layer 204: pad nitride layer 206, 216, 220: mask layer • 208, 222, 230: patterned photoresist layer • 212, 232, 317: dielectric layer. 214: germanium layer. 224: opening 225: protrusion 226: lining oxide layer 26 1362721 2005-0108 22658twf.doc/n 228: dielectric material layer 228a, 318a: lower gap Wall 234: conductor material layer 236: spacer material layer 236a, 318b: upper spacer 238: conductor layer 238a, 330: contact window 240, 332: inner dielectric layer 250, 252, 314a, 314b: doped region 300: Dynamic random access memory 304b: semiconductor layer 304c: semiconductor protrusion 316: gate dielectric layer 326a: lu compound Layer 326b: oxide layer

27

Claims (1)

U02/21 2005-0108 22658twf.doc/n X. Application for patents: including L kinds of dynamic random access memory _ a gentleman structure, a plurality of configurations on the bottom of the county - the semiconductor layer and the conductor substrate are included - insulated a layer, a capacitor, comprising: a lower lower electrode, the drilled junction, a gap 1 , an upper electrode, and a sixth electrode, disposed in the semiconductor layer; and an electrical layer disposed on the lower electrode and the upper electrode — a transistor The method includes: a sidewall disposed on the sidewall of the semiconductor protrusion; and an output portion in the semiconductor protrusion under the gate. - the semiconductor tuner disposed above the gate is in the form of a j-th body of the patent application, and the semiconductor memory of the semi-conductor is accessed. 3. If the patent application size is smaller than the size of the semiconductor layer. The body 'more includes a face window, the dynamic _ access memory and the second doped region _ ^ contact _ disposed above the transistor, 4 · as claimed in the scope of the flute, wherein the contact window The material includes the dynamic random access memory described by the crane. 28 丄丄2005-0108 22658twf.doc/n 5 · For example, the application of the patented Fan Park 1st body' where the gate surrounds the read semi-guide 6. If the scope of patent application is 丄The body 'includes a gate dielectric; between the ministries. 7. For example, the scope of the patent scope includes a spacer wall on the upper and lower sides of the gate. 8. As claimed in the patent application, ^ + + ^ 。 1 of the dynamic random access memory 'where the capacitive dielectric layer comprises - a composite dielectric layer. 9. The scope of the patent application 箆^ # ^ .. The dynamic random access memory of the 8th item == The dielectric layer includes the dynamic random access memory of the item 1 of the oxide/gas body 1 The material of the lower electrode includes doped polycrystalline stone. The dynamic random access memory cell of the item. The dynamic random access memory of the item is disposed on the sidewall of the semiconductor protrusion and the dynamic random access memory of the semiconductor protrusion 1 is placed in a dynamic random memory as described in item 1 of the range The memory is taken, wherein the material of the upper electrode comprises doped stone. ^ The dynamic (four) access memory as described in claim i, wherein the material of the gate comprises a crane. A method for fabricating a dynamic random access memory, comprising: providing a substrate, an insulating layer is formed in the substrate; removing a portion of the substrate and the insulating layer, forming a plurality of trenches in the substrate to expose the insulating a substrate under the layer; forming a dielectric layer on the sidewalls of the trenches; 29 1362721 2005-0108 22658twf.doc/n The surface above the surface of the pupil is lower than the surface of the trench filled with the lower electrode a private portion of the substrate forming a plurality of openings above the lower electrode: the width of the openings is greater than the width of the trenches, and a plurality of the openings in the substrate are sandwiched between the openings; An ion implantation process, the substrate on the margin layer between adjacent ones of the adjacent channels, forming an upper electrode; forming a first-doping region with the portion, the first doping The sidewalls of the dielectric regions of the region are sequentially formed with a question mark = a second doped region is formed in the protrusion above the gate. The dynamic random access memory of the method described in claim 13 is included after forming the second doped region, and the contact window is connected to the second doped region. . The method for forming a random access memory is as follows: a method for forming the opening and the protruding portion includes: forming a mask layer on the substrate; forming a pattern on the substrate - forming a pattern The photoresist layer is formed between the adjacent two trenches and the first patterned photoresist reed, the width of the substrate is less than the thickness of the adjacent two trenches=basemap Removing the exposed cover for the mask to expose the lower electrode; and removing the first patterned photoresist layer β Γ f f f 专利 11 11 11 f 1 The method for manufacturing a memory device according to the item 5, wherein the material of the mask layer comprises ruthenium oxide. The movement of the 13th (4) moving machine accesses the memory of the basket, wherein the gate surrounds the protrusion. (4) The secret memory access memory of the item (4) includes: after the formation of the first doped region, the gate is formed, and the lower spacer is formed on the sidewall of the opening. The method for fabricating the secret random access memory described in claim 18, wherein the method for forming the lower spacer comprises: forming a layer of a dielectric material on the substrate, the dielectric material layer filling the layer The second patterned upper photoresist layer, the second patterned photoresist layer, the second patterned photoresist layer has an X degree smaller than the width of the openings; The patterned photoresist layer is a layer of dielectric material of the mask portion, and the remaining wall is covered by the remaining Nie; and the layer of dielectric material from the edge of the storm is removed as the lower portion. Brother II patterned photoresist layer. The volume of the dynamic random access memory of the volume is described. "The width of the meshed photoresist layer is greater than that of the 21st. For example, the manufacturing method of the corpuscle of the patent application scope, the upper surface of the lower spacer is lower than the sorrow random access memory. First 31