TW200900485A - Etching solution, method of surface modification of semiconductor substrate and method of forming shallow trench isolation - Google Patents

Abstract

An etching solution, a method of surface modification of a semiconductor substrate and a method of forming shallow trench isolation are provided. The etching solution is used for surface modifying the semiconductor substrate. The etching solution includes an oxidant and an oxide remover. The semiconductor substrate is oxidized to a semiconductor oxide by the oxidant, and the oxide remover subtracts the semiconductor oxide.

Description

200900485W35〇〇pa. IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method for surface treatment of etched/cold liquid, semiconductor substrate, and a method for forming shallow trench isolation, and particularly relates to an application. The method for treating the surface of the smashed material substrate and the method for forming the shallow trench isolation. [Prior Art] As the degree of accumulation in the integrated circuit increases, an isolation process for preventing leakage or short circuit between semiconductor elements relatively plays an increasingly important role. Traditionally, the Oxidation of Regional System is used.

Silicon, LOCOS) As the isolation technology between semiconductor components, the main steps include the formation of tantalum oxide layer and tantalum nitride layer, the unique formation of tantalum oxide layer and tantalum nitride layer, and the growth of tantalum fossils by thermal oxidation. The oxide layer of the material. However, in the growth of the field oxide layer, the edge of the pad oxide layer and the pad nitride layer is also affected by oxygen molecules and moisture in the thermal oxidation environment to form cerium oxide, and the pad is oxidized. The edge of the layer and the pad nitride layer is lifted up to form a bird's beak. The beak system formed here reduces the length of the active area, and as the length of the semiconductor process is pushed downwards, the length of the bird's beak significantly affects the length of the active area, further affecting the subsequent process of the semiconductor component. τ, therefore, recently, a few trench isolations have been developed (Shallow Trench fill = technology] to form isolation between semiconductor components by etching the trenches on the germanium wafer, and then by oxygen, etc.

fW35〇〇PA 200900485 —->·^^/)7ϊηυν\Λ area. The shallow trench isolation technology mainly utilizes the pad oxide layer and the pad nitride layer as a mask layer for the engraving of the trenches, and after the steps of filling and planarizing are completed, the mask layer is removed. However, when the mask layer is removed by wet etching, the etchant also erodes the germanium material or the polysilicon material of the germanium wafer, causing damage to the surface properties of the germanium wafer, and residual nitride after removing the mask layer. On the wafer, the surface of the wafer is damaged and the yield is reduced. In order to avoid the above-mentioned so-called "K〇〇i effect" and its accompanying white bandb interval phenomenon, the industry has developed a Sacrificial Oxide Layer to connect the Shi Xi wafer table. The method of loss of text. The sacrificial oxide layer is removed after the oxide layer of the sacrificial wafer is oxidized. However, this method of using the sacrificial oxidized ϋ ϋ 日 日 日 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 具有 。 。 。 。 。 。 。 。 In order to avoid the problem of nitrogen and nitrogen, the industry has developed a technology that does not require the use of pad nitride layer isolation technology. However, this method of not using a nitride layer is a method. Adding the steps and complexity of the clothing process' and increasing the production considerations as to how the process complexity can be added, and in line with the cost 'two: five to solve the above-mentioned defects in the surface quality of the wafer, the problem to be solved Problem history~

rW3500PA 200900485 SUMMARY OF THE INVENTION The present invention relates to a method for treating a solution, a method for treating a semiconductor substrate, and a method for isolating a ditch and a ditch, the side agent and the oxidizing agent are prepared to prepare a solution, and the semiconductor substrate is directly contacted. For surface treatment. It has the advantages of improving the surface quality of the semiconductor board, slowing down the effect of the library, and processing: this. According to the aspect of the invention, a solution is proposed for surface treatment of a conductor substrate. The solution of the money includes an oxidizing agent to remove the oxide. Oxidation (d) is used to oxidize the semiconductor substrate to a semiconductor oxide 'and oxide (4) to remove the upper semiconductor oxide. According to another aspect of the present invention, a surface treatment method of a semiconductor substrate is proposed. First of all, provide - semi-guided county board. Next, the above semiconductor substrate is brought into contact with a solution. This (iv) solution includes an oxidizing agent and an oxide removing agent. According to still another aspect of the present invention, a method of forming shallow trench isolation is provided. First, a semiconductor substrate is provided which has a trench. Next, a liner layer is formed on the surface of the trench. Then, a dielectric material is filled in the towel. Then, the semiconductor substrate is brought into contact with the (d) solution to perform surface treatment of the semiconductor substrate. The etching solution includes an oxidizing agent and an oxide removing agent. In order to make the above description of the present invention more comprehensible, the preferred embodiment of the present invention is described in detail below with reference to the accompanying drawings: ΓΨ3500ΡΑ 200900485 [Embodiment] The following is presented as an example of the present invention. The technical material of the present invention is limited to this, and the domain is _ and the scope of the protection is intended to be protected. Furthermore, the drawings in the embodiments are also shown to clearly show the technical features of the present invention. Please refer to Fig. 1 at the same time, and the method for forming a shallow trench isolation method according to the embodiment of the present invention is shown. The method of the actual _ separation mainly includes the following steps. First, a thin layer of two layers is provided on the surface of the red. Second, the filling-dielectric material is placed in the gully. Then, the semi-conducting plate is brought into contact with the solution to correct: surface treatment to improve the surface quality of the semiconductor substrate. Avoiding Brother Thickness The following is an example of the formation of shallow trench isolation on the -shixi substrate. However, any of the technical fields of the present invention can be understood that the shape of the trench isolation according to the preferred embodiment of the present invention can also be applied to other semiconductor devices for improving the surface.提升 Improve the performance of semiconductor devices in one step. . Please refer to FIG. 2 to FIG. 2G at the same time. FIG. 2 is a schematic view showing the substrate, the buffer layer and the mask layer according to the preferred embodiment. FIG. 2 is a view showing the groove formed on the substrate of the second drawing. a schematic circle; in FIG. 2, a schematic diagram of a non-liner layer formed on the surface of the trench of FIG. 2B; and a second schematic view of the dielectric material deposited on the trench and the mask layer of FIG. 2C; A schematic diagram showing the dielectric material of the 2D drawing and the mask layer after flattening. 200900485 ^

2G3500PA - FIG. 2F is a schematic view showing the mask layer and the buffer layer after the removal of the mask layer of FIG. 2E; and FIG. 2G is a schematic view showing the surface of the substrate of FIG. 2F after surface treatment. First, as shown in step 101 of Fig. 1, a semiconductor substrate having a trench is provided. As shown in FIG. 2A, in the embodiment, the surface 10a of the semiconductor substrate 10 is sequentially provided with a buffer layer 20 and a mask layer 30, and the buffer layer 20 and the mask layer 30 have The same one pattern. The mask layer 30 is, for example, a nitride layer, and the buffer layer 20 is, for example, an oxide layer for buffering the stress of the mask layer 30 adhering to the semiconductor substrate 1 . Next, the semiconductor substrate 10 has no corresponding pattern portion to form the trench 11, as shown in Fig. 2B. Then, as shown in steps 102 and 2C, a liner layer 12 is formed on the surface of the trench 11. In this embodiment, the liner layer 12 is formed by a high temperature oxidation process at about 900 ° C to 1000 °. (In the high temperature environment, the surface of the trench 11 is oxidized. In the embodiment, the shallow trench isolation method is formed, and then step 103 is performed to fill a dielectric material in the trench n. First, the dielectric material is used. The deposition, dielectric material 40 is completely filled with the trenches 11. In the present embodiment, the dielectric material 40 is, for example, cerium oxide (Si 〇 2), and preferably by chemical vapor deposition (Chemical Vapor Deposition, CVD) is deposited on the trench 11 and the mask layer 30 as shown in FIG. 2D. In addition, after the dielectric material 40 is deposited, a high temperature tempering step can be performed to improve the dielectric material 40. Electrical properties. Then, by means of chemical mechanical polishing, and using the mask layer 3 as the polishing end point, the dielectric material 4 is planarized as shown in the figure.

rW3500PA 200900485 Again, the method of the present embodiment preferably performs the steps of removing the buffer layer 20 and the mask layer 30 for exposing the semiconductor substrate 10. In this embodiment, the material of the mask layer 30 is nitride (e.g., tantalum nitride), and the buffer layer 20 and the mask layer 30 are preferably removed by wet etching. After the buffer layer 20 and the mask layer 30 are removed, nitride 50 remains in a portion adjacent to the surface of the semiconductor substrate 10. Next, in step 104, the semiconductor substrate 10 is brought into contact with an etching solution to perform surface treatment on the semiconductor substrate 10. The solution is removed from the surface of the semiconductor substrate 10 to a thickness D. As shown in Fig. 2G, the thickness D is about 〜50 angstroms. After the semiconductor substrate 10 is etched, the quality of the surface can be maintained. The etching solution described above includes an oxidizing agent and an oxide removing agent 'oxidizing agent for oxidizing the semiconductor substrate 10 into a semiconductor oxide' and an oxide removing agent for removing the semiconductor oxide. The surface of the semiconductor substrate 10 is etched to the above-described thickness D. In the present embodiment, the oxidizing agent is, for example, hydrogen peroxide (H2?2), the oxide removing agent is, for example, ammonium hydroxide (NHUOH), and the etching solution further includes de-iomzed water. Among these components, the oxide remover occupies a larger volume ratio than the oxidant. The oxide removing agent, the oxidizing agent and the deionized water have a volume ratio ranging from about 2 to 4: 1 : 8 〇 2 〇〇. Preferably, the volume ratio of oxide remover, oxidant and deionized water is about 4:1:11〇 and at 25. Under the temperature condition of the crucible, the surname solution was brought into contact with the semiconductor substrate 1G for about 6 minutes to remove the thickness D from the surface of the semiconductor substrate 10. Outside the gentry, in addition to the above composition, in accordance with this

200900485 Second hunger hunger 1W3500PA invention preferred embodiment _ solution, the oxide remover can also be, for example, deficient hydrogen (HF) 'where oxide remover, oxidant and deionized water, the volume ratio It is preferable that the surface of the semiconductor substrate 10 is removed by the thickness D by the contact of the side solution to the semiconductor substrate & 1 〇 for about 2 minutes under the temperature condition of about :. In the above preferred embodiments according to the present invention, nitrogen oxides, hydrogen peroxide and deionized water, and fluorinated gas, hydrogen peroxide and deionized water are used as examples, but in the technical field of the present invention, The person skilled in the art can understand that the technology of the present invention is not limited thereto, and the silver etching solution of any other usable material semiconductor substrate 10 (for example, the surface quality of hydrogen fluoride and the semiconductor substrate after the removal. M improves the formation of shallow 'existing channels; the following For example, in the process of applying the semiconductor device, the threshold voltage value of the front and rear conductor devices of the method for applying the isolation method of the preferred embodiment of the present invention is applied. The semiconductor material is, for example, a P-channel gold semi-transistor (PMOS) and The N-channel gold-oxygen semi-transistor (nm〇s) is taken as an example. Please refer to FIG. 3A to ride the differential voltage value A1 of the PMqs before and after the method of isolating the trench isolation using the preferred embodiment of the present invention. It indicates that the distribution range of the PMOS critical electric device is not applied in the method of the embodiment, and the second voltage range A2 indicates the distribution range of the critical voltage value of the PM〇S after the method of the present embodiment. Shows' (iv) a second electrical line A2 is smaller than the circumference of the - ^ voltage range, that is, should embodiment Choi, bribes good drainage material of Example isolation method can effectively reduce the error range of the critical electrical Furthermore M, 11 by the first voltage range.

fW3500PA 200900485 • The average value PI of A1 and the flat value of the second voltage range A2 show that the PMOS of the shallow trench isolation method of this embodiment has a large negative critical voltage value. In addition, please refer to FIG. 3B, which shows a distribution diagram of Nm〇s threshold voltage values before and after the method of forming shallow trench isolation using the preferred embodiment of the present invention. The second electric house range A3 indicates the distribution range of the NMOS threshold voltage value when the method of the present embodiment is not applied, and the fourth voltage range A4 indicates the distribution range of the NMOS threshold voltage value after the method of the present embodiment is applied. As shown in FIG. 3B, the fourth voltage range A4 is smaller than the third voltage range A3, and the average value P3 of the third voltage range A3 and the average value P4 of the voltage range A4 are known. NMOS has a large positive threshold voltage value. In general, the method for forming shallow trench isolation according to the preferred embodiment of the present invention is capable of lowering the critical voltage error range of pM〇s and NMOS, and relatively improving pM〇s and NMOS operation stability, and further improving Avoid the problem of critical electricity and financial decline, and further improve the quality of PMOS and NMOS. The etching solution, the surface treatment method of the semiconductor substrate and the method for forming the shallow trench isolation according to the preferred embodiment of the present invention remove the surface of the semiconductor substrate by an etching solution composed of an oxidizing agent and an oxide removing agent. The thickness 'by removing the nitride remaining in the surface of the semiconductor substrate in the process can improve the surface quality of the semiconductor substrate' to avoid the occurrence of the Cuy effect. In addition, in the etching solution, the surface treatment method of the semiconductor substrate, and the method for forming the shallow trench isolation according to the preferred embodiment of the present invention, it is only necessary to simply contact the rice etching solution on the surface of the semiconductor substrate and directly etch the surface of the semiconductor substrate. Yes, it has a simple method of excellent 12 200900485

— xW3500PA • Point. Further, since the composition of the etching solution is a chemical which is generally available in the industry, it has the advantage of low cost, and the cost of the process can be saved. In the above, the present invention has been disclosed in the preferred embodiments, and is not intended to limit the present invention. It will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. 13 200900485

-FW3500PA • [Simplified Schematic] FIG. 1 is a flow chart showing a method for forming shallow trench isolation according to a preferred embodiment of the present invention; FIG. 2A is a diagram showing a substrate, a buffer layer and a cover according to a preferred embodiment of the present invention. 2B is a schematic view showing a groove formed on the substrate of FIG. 2A; FIG. 2C is a schematic view showing a groove layer formed on the surface of the groove of FIG. 2B; f 2D is a dielectric view A schematic view of the material deposited on the trench and the mask layer of FIG. 2C; FIG. 2E is a schematic view showing the dielectric material and the mask layer of FIG. 2D after planarization; and FIG. 2F is a mask of FIG. 2E FIG. 2G is a schematic view showing the surface of the substrate of FIG. 2F after surface treatment; and FIG. 3A is a diagram showing the PMOS criticality before and after the method for forming shallow trench isolation using the preferred embodiment of the present invention. A distribution map of voltage values; and FIG. 3B is a diagram showing distributions of NMOS threshold voltage values before and after the method of forming shallow trench isolation using the preferred embodiment of the present invention. 14 20090Q485w_pa [Description of main component symbols] 10 : Semiconductor substrate 10a : Surface of semiconductor substrate 11 : Ditch 12 : lining layer 20 : Buffer layer 30 : Mask layer 40 : Dielectric material 50 : Nitride A1 First voltage range A2 Second voltage range A3 Third voltage range A4 Fourth voltage range D: Thickness P Bu P2, P3, P4: Average 15

Claims (1)

IW3500PA 200900485 .-JiJ U X. Patent Application Range: 1. An etching solution for performing surface treatment of a semiconductor substrate. The etching solution comprises: an oxidizing agent for oxidizing the semiconductor substrate as a semiconductor oxide; An oxide remover for removing the semiconductor oxide. 2. The surname solution of claim 1, wherein the oxidizing agent comprises hydrogen peroxide (h2〇2) or ozone (〇3). 3. The surname solution of claim 1, wherein the oxide remover comprises ammonium hydroxide (NH4〇h) or hydrogen fluoride (HF). 4. The silver engraving solution of claim 1, wherein the oxidizing agent comprises hydrogen peroxide, and the oxide removing agent comprises a proportion of the volume of the oxyhydroxide removing agent greater than the volume occupied by the oxidizing agent. 5. The etching solution according to claim 4, further comprising: de-ionized water; wherein the volume ratio of the oxide removing agent, the oxidizing agent and the deionized water is about 2~ 4 : 1 : 80 to 200. 6. The etch solution according to claim 4, further comprising: deionized water; wherein the oxide remover, the oxidant and the deionized water have a volume ratio of about 4:1:110. 7. The rice cutting solution of claim 1, wherein the oxidizing agent comprises hydrogen peroxide, and the oxide removing agent comprises hydrogen fluoride. 16 W3500PA 200900485, 8. The etching solution according to claim 7 of the patent application, further comprising deionized water; the volume of ionized water, wherein the oxide removing agent, the oxidizing agent and the de-proportion are about 1: 2 : 500 . 9 The second and second panels of the table * treatment method 'includes contacting the semiconductor substrate with a surname solution, including an oxide remover. ^ and 10. The surface treatment method described in claim 9 of the patent scope, wherein the ratio of the volume of the oxide to the volume of the oxide is greater than the proportion of the volume of the oxidant. The surface treatment method of claim </ RTI> wherein the oxidizing agent comprises hydrogen peroxide, the oxide removing agent comprises oxidizing water, and the etching solution further comprises deionized water; wherein the oxide removing agent The volume ratio of the oxidizing agent and the deionized water is about 2 to 4: 1 : 8 〇 to 200. 12. The surface treatment method of claim 1, wherein the oxidizing agent comprises hydrogen peroxide, the oxide removing agent comprises hydrogen peroxide, and the etching solution further comprises deionized water; wherein the oxide is removed The volume ratio of the remover, the oxidant and the deionized water is approximately 4:1:11 〇. 13. The surface treatment method of claim 9, wherein the oxidizing agent comprises hydrogen peroxide, and the oxide removing agent comprises hydrogen fluoride. 17 200900485 二连纲2/ΰ · fW350〇PA J STTW + method for opening trench isolation isolation (shall〇w trench isolation 'sti), including: = semiconductor substrate, the semiconductor substrate has a trench; (linerlaye 〇 on the surface of the trench; filling-dielectric material in the trench; and contacting the semiconductor substrate with a surface treatment of the ruthenium plate; An oxidizing agent and a method for removing a oxidizing agent, wherein the oxidizing agent comprises a double hydrazine water, wherein the oxidizing liquid further comprises deionized water; * k Including the hydrogen peroxide, the name of the surname = the volume of the oxidant and deionized water (17. As claimed in item 15 of the scope of the patent, the + ^ ^ agent includes hydrogen peroxide, the oxide removal The oxidizing solution further comprises deionized water; the liquefaction of the oxidizing solution is ???the ratio of the etchant=the amount of the eliminator, the oxidizing agent and the deionized water. 18. The method according to claim 14, wherein The removing agent includes hydrogen peroxide, which The chemical agent includes hydrogen peroxide. 19. In the step of reading the outline layer of the patent application range, the method of selecting the Ω Ω element is used in the formation of the ruthenium layer, which is about 9 〇〇 18 • W3500PA The method of claim 14, wherein the dielectric material is filled in the trench by chemical vapor deposition (CVD). The method of claim 14, wherein the surface of the semiconductor substrate is sequentially provided with a buffer layer and a mask layer, the buffer layer and the mask layer having a pattern to provide the semiconductor The step of the substrate further includes: etching the semiconductor substrate without corresponding to the pattern to form the trench. 22. The method of claim 21, wherein the step of filling the dielectric material further comprises: depositing the dielectric a material in the trench and on the mask layer; and planarizing the dielectric material and the mask layer. 23. The method of claim 21, wherein the semiconductor is Before the step of contacting the substrate with the etching solution, the method further comprises: removing the buffer layer and the mask layer to expose the semiconductor substrate. 24. The method of claim 23, wherein the buffer is removed The method of the layer and the mask layer is carried out by wet etching. The method of claim 21, wherein the buffer layer is an oxide layer, and the mask layer is a vaporized layer. Layer. 19