200849490 九、發明說明： [發明所屬之技術領域] 本發明係有關於一種半導體元件之製程方法，且特別有關於半導 體電晶體之自行對準掺雜方法。 [先前技術] (Λ 一直以來，半導體工業一方面為了提高積體電路裝置，如動態隨 機存取記憶體(DRAM)等，的工作速度，另一方面又為了符合消費者 對於小型化電子裝置的需求，已使得半導體裝置中的電晶體之尺寸持 績縮小。也就是說，例如DRAM中電晶體的通道長度、接面深度以 及許多組成部份的尺寸都必須縮小。而當電晶體的通道長度越小，電 晶體的工作速度便越快。 W㈣DRAM電晶體—般為平面式電晶體，其巾電晶體通道介 G 於雜舰關，該通道的長制細減度相同，當為滿足上述目 • 的而縮小元件尺寸時，通道長度的縮減將會導致電晶體臨界電壓變 • 小。為解決此問題，現今科技已發展出垂直式電晶體，其可用以克服 平面式電晶體的限制。但由於垂直式電晶體的源極與汲極區域是在相 同平面上且由於通道長度的麵，因此料使用光罩來執行自行對準 離子佈植步驟，以將雜質摻入。 因此’需要有解決上述問題的方法，本發明即提供一選擇， 200849490 供進行自行對準摻雜。 [發明内容] 本發明之一目的係在於提供一種形成溝槽式垂直電晶體之方 法’利用斜角離子佈植之自行對準摻雜（self aligned doping) 的手段’來形成電晶體之源極與汲極，進而製作溝槽式垂直電 晶體。 本發明之另一目的係在於提供一種形成溝槽式垂直電晶體之方 法’其可解決習知垂直電晶體中，由於閘極通道長度的變異， 而使得自行對準摻雜方法在執行上困難的問題。 本發明之又一目的係在於提供一種據以形成之溝槽式垂直電晶體，其 閘極之溝槽長度增加，可改善因元件尺寸縮小時所導致的短 通道效應，而增進臨界電壓值。 依本發明之一方面，一種溝槽式垂直電晶體之方法，該方法包 各·提供一具溝槽之基底，以該溝槽的一中心軸為基準，以界定基底 之一第一側及一第二侧；形成一第一罩幕層覆蓋於該基底及溝槽之表 面，再來形成一第二罩幕層覆蓋第一罩幕層；接下來對第二罩幕層進 行斜角離子佈植，以形成—佈植區域。接著去除該佈植區域後，去除 暴路之第一罩幕層，供暴露該基底及溝槽之一部份表面；對暴露之該 部份表面進行摻雜，而於該部份表面之基底形成—摻雜區域；去除剩 6 200849490 餘的第I幕層及第二罩幕層，使該基底及溝槽之表面暴露；於暴露 的表面形成_介電層；於該溝槽之該介電層的表面形成—雜結構； 於第一摻雜區域之介電層無酿結制-部絲面上形成一圖案 化罩幕層；以及職第二侧之基絲面進行獅，於第二侧之基底形 成一另一摻雜區域。 依本發明之另一方面，一種自行對準摻雜之方法，包含··提供一 具溝槽之基底，崎溝獅—巾心軸為基準，界定基底之—第一側及 第側’开v成第一罩幕層覆蓋於該基底及溝槽之表面；形成一第 二罩幕層覆蓋第-罩幕層；以及對第二罩幕層進行斜角離子佈植，以 形成-佈植區域；去除該佈植區域；去除暴露之第—罩幕層，供暴露 魏底及溝槽之—部份表面；以及對暴紅該部份表面進行換雜，而 於該部份表面之基絲成—摻雜區域。 [實施方式] 以下將參照所附圖式詳細說明本發明之實施例。 圖1A至圖1M顯示根據本發明之一實施例的形成動態隨機存取 記憶體(DRAM)之H讀直電晶體之各方法步騎職的截面示 意圖。 首先於圖1A中，提供具有—溝槽2〇〇的基底1〇〇，例如為石夕基 底’以溝槽200的-中心軸L為基準，界定基底觸之一第一側si 7 200849490 及-第二侧S2，第一侧S1可為左側或右側，第二侧&則為第一側 之另-侧。例如使用化學氣相沉積技術(CVD)形成一罩幕層皿，覆 蓋於該基底1〇〇及溝槽200之表面，如圖m所示，罩幕層ι〇ι例如 由二氧化石夕構成，然後，例如使用電漿辅助化學氣相沉積(PECVD) •方式，例如形成由非晶石夕㈣:H)所組成的罩幕層1〇2，覆蓋於罩幕層 101上’如® 1C所示，以供進行後續斜角離子佈植步驟。 减圖1D，接著，例如使用肥離子來進行斜角離子佈植，該 斜角的角度必須使離子進入第一側S1之溝槽2〇〇中，如圖中箭頭所 表不’至^在勒f 巾的部分繼及絲面形成佈植區域1⑽。 之後’如圖1E所示，可利用濕_方式，將佈植區域102A去除， 留下麵的罩幕層112，使得罩幕|1〇1之部份表面暴露。接著，參 見圖1F ’例如利用乾侧方式，去除暴露的罩幕層應，留下剩餘的 〇 罩幕層111，因而暴露基底100及溝槽200之部分表面。 參關1G，其中對暴露的基底1〇〇及溝槽之部份表面，進 亍U隹例如以氣相摻雜(gas沖咖d_祕術，於基底⑽中形成 、 摻雜區域ΠΒ ’其可供作為沒極，並且換雜區域剛的深度能夠隨溝 才曰200的冰度而舰。接著，如圖ih所示，可利用濕侧方式，去 除剩餘的罩幕層111及112,使基底1〇〇及溝槽之整體表面暴露。 接下來 > 圖II’其中於該暴露的基底刚及溝槽施表面上形成 8200849490 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method of fabricating a semiconductor device, and more particularly to a self-aligned doping method for a semiconductor transistor. [Prior Art] (Λ The semiconductor industry has been on the one hand to improve the operating speed of integrated circuit devices such as dynamic random access memory (DRAM), and on the other hand, to meet consumer expectations for miniaturized electronic devices. Demand, the size of the transistor in the semiconductor device has been reduced. That is, for example, the channel length of the transistor in the DRAM, the junction depth, and the size of many components must be reduced. The smaller the transistor, the faster the working speed of the transistor. W (four) DRAM transistor is generally a planar transistor, and its towel transistor channel G is connected to the miscellaneous ship. The length reduction of the channel is the same, when the above-mentioned mesh is satisfied. • When the component size is reduced, the reduction in channel length will cause the transistor threshold voltage to become smaller. To solve this problem, today's technology has developed vertical transistors that can be used to overcome the limitations of planar transistors. Since the source and drain regions of the vertical transistor are on the same plane and due to the length of the channel, a photomask is used to perform self-alignment. Sub-planting step to incorporate impurities. Therefore, there is a need for a method for solving the above problems, and the present invention provides an option, 200849490 for self-aligned doping. [Invention] It is an object of the present invention to provide a method The method of forming a trench-type vertical transistor "uses a self-aligned doping method of oblique ion implantation" to form a source and a drain of a transistor, thereby fabricating a trench-type vertical transistor. Another object of the present invention is to provide a method for forming a trench vertical transistor which can solve the difficulty in performing self-aligned doping in a conventional vertical transistor due to variations in the length of the gate channel. A further object of the present invention is to provide a trench-type vertical transistor formed according to which the groove length of the gate is increased, which can improve the short channel effect caused by the reduction of the size of the element, and enhance the criticality. Voltage value. According to one aspect of the invention, a method of trench vertical transistor, each of which provides a substrate with a trench, one of the trenches The mandrel is referenced to define a first side and a second side of the substrate; a first mask layer is formed to cover the surface of the substrate and the trench, and a second mask layer is formed to cover the first mask Layer; then the second mask layer is obliquely ion implanted to form a planting area. After removing the planting area, the first mask layer of the storm path is removed for exposing the substrate and the trench a portion of the surface; doping the exposed portion of the surface, and forming a doped region on the surface of the portion of the surface; removing the remaining 1 200849490 of the first and second mask layers to make the substrate And exposing the surface of the trench; forming a dielectric layer on the exposed surface; forming a hetero structure on the surface of the dielectric layer of the trench; and forming a dielectric layer in the first doped region without a brewing process A patterned mask layer is formed on the surface; and the base surface of the second side of the job carries the lion, and the base on the second side forms a further doped region. According to another aspect of the invention, a self-aligned doping method includes providing a grooved substrate, the sloping lion-to-candle axis as a reference, defining a first side and a first side of the substrate v forming a first mask layer covering the surface of the substrate and the trench; forming a second mask layer covering the first-mask layer; and obliquely ion-coating the second mask layer to form-planting a region; removing the implanted region; removing the exposed first-mask layer for exposing the surface of the Wei-bed and the groove; and modifying the surface of the reddish portion to the surface of the portion Wire-doped regions. [Embodiment] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. 1A through 1M are cross-sectional views showing the steps of the method of forming a H-reading transistor of a dynamic random access memory (DRAM) in accordance with an embodiment of the present invention. First, in FIG. 1A, a substrate 1 具有 having a trench 2 〇〇 is provided, for example, a shi ding base 'based on the center axis L of the trench 200 , defining a first side of the substrate contact si 7 200849490 and - second side S2, the first side S1 may be the left side or the right side, and the second side & the other side of the first side. For example, a masking layer is formed by chemical vapor deposition (CVD) to cover the surface of the substrate 1 and the trench 200. As shown in FIG. m, the mask layer ι〇ι is composed of, for example, SiO2. Then, for example, using a plasma-assisted chemical vapor deposition (PECVD) method, for example, forming a mask layer 1〇2 composed of amorphous stone (4): H), covering the mask layer 101, such as ® 1C Shown for subsequent oblique ion implantation steps. Subtract Figure 1D, and then, for example, using the ferrite ions for oblique ion implantation, the angle of the bevel must make the ions enter the trench 2〇〇 of the first side S1, as shown by the arrow in the figure The portion of the lef towel is followed by the surface of the filament to form the implanted area 1 (10). Thereafter, as shown in Fig. 1E, the implanted region 102A can be removed by the wet method, leaving the underlying mask layer 112 such that a portion of the surface of the mask |1〇1 is exposed. Next, referring to Fig. 1F', the exposed mask layer should be removed, for example, by the dry side method, leaving the remaining mask layer 111, thereby exposing portions of the substrate 100 and portions of the trench 200. Participate in 1G, in which the exposed substrate 1〇〇 and part of the surface of the trench, such as the gas phase doping, is formed in the substrate (10), doped region ΠΒ ' It can be used as a poleless, and the depth of the replacement area can be compared with the ice of the ditch 200. Then, as shown in Figure Ih, the remaining mask layers 111 and 112 can be removed by the wet side method. Exposing the entire surface of the substrate 1 and the trenches. Next > Figure II' where the exposed substrate and trench surface are formed 8
200849490 -介電層104,其材料例如為氧化層，以熱氧化方式形成。 於圖中，以習知方式在介電層·表面上、於溝槽細中形成 一閘極結構105，閘極結構1〇5可 了依據不冋的製程而有不同的變化， 例如除包含閘極外，亦可選擇 、释性形成盍層(未圖示）、間隙壁層(未圖 不）。接著，參照圖1K，在摻雜F… 〃 &域103之鄰近閘極結構1〇5的介電 層104與閘極結構1〇5的部份 丨切表面上形成一圖案化光阻層，形成方式 可利用習知之微影技術。 之後於圖1L中’利用圖案化光阻層作為一圖案化罩幕層⑽， 射弟-側S2的基底⑽表面，峰子佈_方式來進行摻雜，而於 第二側S2之基底腦形成摻雜區域1〇7，其可供作為源極，之後， 例如是以驗刻方式來移除圖案化罩幕層1%。圖中則顯示一根 據上述方法步齡· DRAM溝槽結直電晶體之截面圖。 自前述可知，本發明利用斜角離子佈植之自行對準摻雜 方法，來形成電晶體的源極與汲極，以進一步製作溝槽式垂 直電晶體。此可解決習知垂直電晶體中，由於閘極通道長度 的變異’而使得自行對準摻雜方法在執行上困難的問題，並 且由於閘極之溝槽長度增加，可改善因元件尺寸縮小時所導 致的短通道效應，而增進臨界電壓值。 雖然已就實施例作例示性說明本發明之原理以及功效， 9 200849490 然而上述實施例並非用於限制本發明。任何熟知此項技藝 者，在不悖離本發明之精神與範疇内，當可做變更與潤飾。 本發明之保護範圍係如所附之申請專利範圍所界定。 [圖式簡單說明] 本發明之内容可參照下列圖式配合說明，將可輕易的了 解上述内容及此項發明之諸多優點，其中： Γ 圖1A至1L係為根據本發明之方法的各步驟所分別對應 之截面圖；以及 圖1M係為根據本發明之方法所完成該電晶體之截面圖。 [元件符號說明] 100 基底 # 101、111、102、112 罩幕層 102 A 佈植區域 103 摻雜區域 " 104 介電層 105 閘極結構 106 圖案化罩幕層 107 摻雜區域 200849490 200 溝槽 L 中心軸 51 第一侧 52 第二侧 Ο π200849490 - Dielectric layer 104, the material of which is, for example, an oxide layer, formed by thermal oxidation. In the figure, a gate structure 105 is formed on the dielectric layer and surface in a fine manner in a conventional manner, and the gate structure 1 〇 5 can be changed according to a flawless process, for example, including Outside the gate, a layer of ruthenium (not shown) or a layer of spacers (not shown) may be selected and released. Next, referring to FIG. 1K, a patterned photoresist layer is formed on the dielectric layer 104 of the adjacent gate structure 1〇5 of the doping F... 〃 & field 103 and a portion of the tantalum surface of the gate structure 1〇5. The formation method can utilize the conventional lithography technology. Then, in FIG. 1L, 'the patterned photoresist layer is used as a patterned mask layer (10), and the surface of the substrate (10) of the emitter-side S2 is doped, and the base brain is formed on the second side S2. A doped region 1 〇 7 is available as a source, after which, for example, the patterned mask layer is removed 1%. The figure shows a cross-section of a DRAM trench junction transistor according to the above method. As can be seen from the foregoing, the present invention utilizes a self-aligned doping method of oblique ion implantation to form the source and drain of the transistor to further fabricate a trench-type vertical transistor. This can solve the problem that the self-aligned doping method is difficult to perform due to the variation of the gate channel length in the conventional vertical transistor, and since the gate length of the gate is increased, the size reduction can be improved. The resulting short channel effect increases the threshold voltage value. Although the principles and effects of the present invention have been illustrated by way of example, the following embodiments are not intended to limit the invention. Anyone skilled in the art can make changes and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS The contents of the present invention can be easily understood by referring to the following drawings, and the advantages of the present invention and the advantages of the invention can be easily understood, wherein: Γ Figures 1A to 1L are steps of the method according to the present invention. Corresponding cross-sectional views; and FIG. 1M is a cross-sectional view of the transistor completed in accordance with the method of the present invention. [Element Symbol Description] 100 Substrate #101, 111, 102, 112 Mask Layer 102 A Buried Area 103 Doped Area " 104 Dielectric Layer 105 Gate Structure 106 Patterned Mask Layer 107 Doped Area 200849490 200 Groove Slot L Center axis 51 First side 52 Second side Ο π