200848976 九、發明說明： 【發明所屬之技術領域】 本毛明係關方、-種驅動器，特別係有關於一種閑區 動電路及其驅動方法。 【先前技術】 由於某些特定的應用電路需要巨大驅動能力的元 件’該兀件通常是功率電晶體，而為了控制功率電晶體來 f 推動这些應用電路’必須輸入一控制訊號至功率電晶體的 閘極端，因此’會在功率電晶體的前級配置一間極驅動電 路。例如馬達的驅動原理，就是控制依照特定連接方式的 南壓端功率電晶體與低壓端功率電晶體，以按照順序使立 :通與關閉來讓馬達轉動。而要使功率電晶體導通或關 閉，必須在其閉極端輸入—高態或低態的控制訊號M曰由 二在：壓功率電晶體的閑極端所輸入的控制訊 ^其㈣與低的電壓位準並不相同。為此，必須在功 ¥電晶體前配置一閘極驅動雷路， 、 換成可控___“:般控制訊號轉 意圖^路電路之示 產生器m、一高壓電壓位準轉換器13〇奉^衝 14〇、-曝路150、-高壓端驅動級160、—=器 動級170及一低電壓偵測器⑽。而“ ，堡知驅 用訊號輸入端HIN、LIN來接收輪入訊號。甩略11〇利 局壓端的輸出訊號AT係經過脈衝產生 電壓位準轉換器13〇做電壓位 、，2〇及高壓 ~ n錢由脈_濾波器 5 200848976 140及閂鎖電路150的處理而產生，其中高壓電壓位準 換器130之後的電路（包含脈衝濾波器140、閂鎖電路 及高壓端驅動級160)的電壓操作範圍是具有較高電厣、 VB至VS。低壓端的輸出訊號ΑΒ則直接受控於輪二 電路110,並且電壓位準相對較低，其電壓操作範圍是 至VSS。此外VB與VS的差值會等於V]yj[與VSS的差值 然後透過高壓端驅動級160及低壓端驅動級17()的驅 輸出元件的開關切換，來決定輸出訊號AT、的=熊成 然而，高壓端的脈衝濾波器丨4〇、閂鎖電路15〇 ^古 壓端驅動級160的負端供應電源vs並不等於Vss。因此^ 上述之驅動電路在一般高壓製程實現時，將由於N型金严 氧化半導體場效電晶體的基板端(bulk)電壓位準Vss =蜀 極端電壓位準VS不相等，因而產錄體效應 = \ 電壓(VT)變得很大，進而衍生出驅動能力不佳的問題二;| 了要消除基體效應，通常的作法都是利用複雜且特 壓製程技術(如：三井(Tnple Well)製程）來解決。如办呵 不僅製程複雜，並且耗費成本。 一來， 另一方面，當咼壓端驅動級16〇在做驅動級 的開關切換時，其電壓範圍係為VB〜VS，以至於含=件 位準轉換器130無法使用—般的架才冓。並且，^ 位準轉換器13Q持續消耗功率，通f會加人脈^ 裔12(3以及關電路15G來閃鎖脈衝產生器12〇的訊 進而再利用脈衝濾波器140來濾掉高壓電壓位準轉換 二I0 t切換瞬間時所產生的雜訊。但如此-來，將使元 牛曰夕而又進一步造成成本的上揚。 200848976 不同於上述之驅動電路，本發明將提供可避免基體效 應、間化而壓端電路且可在一般高壓製程實現的問極驅動 電路，以克服先前技術所產生的問題。 【發明内容】 - 树料—閘極驅動電路及其驅動方法，係於直接利 用笔G位準I換為將輸入端訊號的電壓操作位準範圍轉 換，並且在高壓端驅動級輸出元件採用串接的p型金屬氧 化半導體場效電晶體來作為開關切換，以避免在一般的高 ^ 壓製程中產生基體效應。 ° …本發明所提供之閘極驅動電路，包含輸入邏輯電路、 高壓電壓位準轉換器、低壓電壓位準轉換器、高壓端驅動 級、低壓端驅動級及低電壓偵測器。高壓電壓位準轉換器 及低壓電壓位準轉換器把輸入邏輯電路所提供之訊號的電 壓操作位準範圍，執行轉換動作。高壓端驅動級連結於高 壓包壓位準轉換器，根據高壓電壓位準轉換器轉換後的訊 號，來控制產生高壓端之輸出訊號。低壓端驅動級連結於 ( 低壓笔壓位準轉換器，根據低壓電壓位準轉換器轉換後的 訊號’來控制產生低壓端之輸出訊號。 【實施方式】 請芩考第二圖所示，其係為本發明内容之閘極驅動電 路之方塊示意圖。本發明之閘極驅動電路20包含一輸入邏 輯電路（input logic circuit) 210、一高壓電壓位準轉換器 (high voltage level shifter) 220、一低壓電壓位準轉換器 (low voltage level shifter)230、一 高壓端驅動級（high side driver) 240、一低壓端驅動級（l〇w side driver) 250 及一 低電壓偵測器（low voltage detector ) 260。 200848976 輸入邏輯電路210透過訊號輸入端HI及LI來接收一 輸入訊號’並將此輸入訊號透過輸入逛輯電路210内部電 路的運算，而轉換成一高壓端訊號（high side signal) HD 及一低壓端訊號（low side signal) LD。其中，輸入邏輯電 路210的電壓操作範圍係在VSS至VCC之間。而VSS與 VCC在設計上可分別例如為〇v及5V，但亦可因實際應用 狀況之不同而有所不同。200848976 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a driver and a driver, and particularly relates to a free-standing circuit and a driving method thereof. [Prior Art] Since some specific application circuits require a large driving capability component, the component is usually a power transistor, and in order to control the power transistor to drive these application circuits, a control signal must be input to the power transistor. The gate is extreme, so 'a pole drive circuit will be placed in the front stage of the power transistor. For example, the driving principle of the motor is to control the south-voltage power transistor and the low-voltage power transistor according to a specific connection manner, so as to make the motor rotate in the order of turning on and off. In order for the power transistor to be turned on or off, it must be at its closed-end input—the high or low state control signal M曰 is controlled by: the control signal input to the idle terminal of the voltage power transistor (4) and the low voltage. The level is not the same. To this end, it is necessary to configure a gate drive lightning path in front of the power ¥ crystal, and replace it with a controllable ___ ": general control signal to the intention circuit circuit generator m, a high voltage voltage level converter 13" Feng Chong 14 〇, - exposure 150, - high-voltage terminal driver stage 160, - = device level 170 and a low-voltage detector (10). And "Fortune drive with signal input HIN, LIN to receive the wheel Signal. The output signal AT of the voltage terminal of the bank 11 is subjected to a pulse generating voltage level converter 13 for voltage level, 2 〇 and high voltage ~ n money by pulse_filter 5 200848976 140 and latch circuit 150 processing The voltage operating range of the circuit (including the pulse filter 140, the latch circuit, and the high side driver stage 160) after the high voltage voltage level changer 130 is generated has a higher power, VB to VS. The output signal at the low voltage side is directly controlled by the wheel circuit 110, and the voltage level is relatively low, and its voltage operation range is to VSS. In addition, the difference between VB and VS will be equal to V]yj [the difference from VSS and then switched by the switching of the output of the high-voltage driver stage 160 and the low-side driver stage 17 () to determine the output signal AT, = bear However, the high-voltage pulse filter 〇4〇, the latch circuit 15 古 古 压 驱动 驱动 驱动 驱动 驱动 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Therefore, when the above-mentioned driving circuit is realized in a general high-voltage process, the substrate voltage level Vss = 蜀 extreme voltage level VS of the N-type gold oxidized semiconductor field effect transistor is not equal, and thus the recording body effect is produced. = \ Voltage (VT) becomes very large, which leads to the problem of poor driving ability; | To eliminate the matrix effect, the usual practice is to use complex and special press technology (such as: Tnple Well process) ) to solve. If you do it, it is not only complicated, but also costly. On the other hand, when the rolling end drive stage 16 is switched at the drive stage, the voltage range is VB VS VS, so that the position level converter 130 cannot be used. ten billions. Moreover, the level shift converter 13Q continues to consume power, and the pass f will add the human body 12 (3 and the off circuit 15G to flash the pulse generator 12 进而 and then use the pulse filter 140 to filter out the high voltage level. Converting the noise generated by the second I0 t switching instant. However, this will cause the Yuanniu to further increase the cost. 200848976 Unlike the above-mentioned driving circuit, the present invention will provide a matrix effect avoidance, The gate circuit and the gate drive circuit can be realized in a general high voltage process to overcome the problems caused by the prior art. [Summary of the Invention] - The tree-gate drive circuit and its driving method are directly used by the pen G The level I is changed to convert the voltage operation level range of the input signal, and the high-voltage terminal driver stage output component uses a series-connected p-type metal oxide semiconductor field effect transistor as a switching switch to avoid the high level in the general ^ The matrix effect is generated in the pressing process. The gate driving circuit provided by the invention comprises an input logic circuit, a high voltage voltage level converter, a low voltage voltage level converter, The voltage terminal drive stage, the low voltage side drive stage and the low voltage detector. The high voltage level level converter and the low voltage level level converter perform the conversion operation by performing the voltage conversion operation level of the signal provided by the input logic circuit. The driving stage is coupled to the high voltage package level converter, and controls the output signal of the high voltage end according to the converted signal of the high voltage voltage level converter. The low voltage end driver stage is connected to the (low voltage pen level level converter, according to the low voltage The converted signal of the voltage level converter controls the output signal of the low voltage end. [Embodiment] Please refer to the second figure, which is a block diagram of the gate driving circuit of the present invention. The gate driving circuit 20 includes an input logic circuit 210, a high voltage level shifter 220, a low voltage level shifter 230, and a high voltage terminal. High side driver 240, a low side driver stage (250) and a low voltage detector (low voltage detecto) r) 260. 200848976 The input logic circuit 210 receives an input signal through the signal input terminals HI and LI and converts the input signal into an internal circuit of the input circuit 210 to convert it into a high side signal HD. And a low side signal LD, wherein the voltage operation range of the input logic circuit 210 is between VSS and VCC, and VSS and VCC are designed to be, for example, 〇v and 5V, respectively, but The actual application status varies.
高壓電壓位準轉換器220連結於輸入邏輯電路210， 並接收輸入邏輯電路210所提供之高壓端訊號HD，以進 一步地將此高壓端訊號HD執行轉換，也就是將高壓端訊 號HD所具備之電壓操作位準由原來的至vss轉換 為VB至VSS。此外，高壓電壓位準轉換器22〇會運算此 咼壓端讥唬HD，以產生高壓端輸出控制訊號和， 其中高壓端輸出控制訊號HH係控制閘極鶴電路2〇之高 壓端的輸出呈現高態（hlgh)，而高壓端輸出控制訊號HL 係控制閉極驅動電路2 0之高壓端的輪出呈現低態（i 〇 w )。 低壓電壓位準轉換器23〇連結於輸入邏輯電路21〇， 並接收輸人邏輯電路21G所提供之低壓端訊號ld，以進 LD執行轉換，也就是將低壓端訊 號LD所具備之電壓操作位準由原來的vcc至娜轉換 = 。會運算此 端㈣控舰號，係控壓== 出呈現咼恶或低態。其中，m 士、 — 、刖 換器230以及低壓端驅動級25 為低壓電壓位準轉 川的供應電源。 8 200848976 高壓端驅動級240連結於高壓電壓位準轉換器22〇， 其内部包含驅動級輸出元件241及242，其中驅動級輸出 兀件24卜242皆係為- p型金屬氧化半導體場效電晶體 (P-type metal oxide semiconductor field effect transistor P-type MOSFET)，並且驅動級輪出元件241之汲極端 (dmmtemimal)與驅動級輸出元件祀之源極端（_似 terminal)連接。 當驅動級輸出元件241之閘極端（gate t_mal)接收 到高壓電壓位準轉換器22Q所提供之高壓端輸出控制訊號 HH為低態時，驅動級輸出元件241將導通，使得驅動級 輸出元件241之汲極端所輸出的輸出訊號pH呈現高態， 也就疋說輪出訊號PH的電壓位準等於vb。 畜驅動級輸出元件242之閘極端接收到高壓電壓位準 轉換裔220所提供之高壓端輸出控制訊號HL為低態時， 驅動級輸出元件242將導通，使得驅動級輸出元件242之 源極端所輸出的輸出訊號PH呈現低態，也就是說，輸出 訊號PH的電壓位準等於VSq而在初始的狀態下，輸出訊 號PH係為VS。並且VB與vs此時可分別例如為8〇v及 65V，但亦可因實際應用狀況之不同而有所不同。 低壓端驅動級250連結於低壓電壓位準轉換器230， 其内部包含驅動級輸出元件251及252，其中驅動級輸出 元件251係為PM〇S，驅動級輸出元件252係為N型金屬 氧化半 脰％效電晶體（N-type metal oxide semiconductor field effect transistor，N-type MOSFET)，並且驅動級輸出元 件251之没極端連接至驅動級輸出元件252之汲極端。 9 200848976 當驅動級輸出元件251之閘極端接收到低壓電壓位準 轉換器230所提供之低壓端輸出控制訊號LX為低態時， 驅動級輸出元件251將導通，使得驅動級輸出元件251之 汲極端所輸出的輸出訊號PL呈現高態，也就是說輸出訊 號PL的電壓位準等於VM。 當驅動級輸出元件252之閘極端接收到低壓電壓位準 轉換器230所提供之低壓端輸出控制訊號LX為高態時， 驅動級輸出元件252將導通，使得驅動級輸出元件252之 汲極端所輸出的輸出訊號PL呈現低態，也就是說，輸出 訊號PL的電壓位準等於VSS。而在初始的狀態下，輸出 訊號PL係為VSS。並且VSS與VM此時可分別例如為0V 及15V，但亦可因實際應用狀況之不同而有所不同。 低電壓偵測器260連結於輸入邏輯電路210，隨時偵 測低壓端（低壓電壓位準轉換器230及低壓端驅動級250) 之供應電源（即VM)是否低於一預設值，以進一步決定 是否輸出一控制訊號至輸入邏輯電路210，來控制高壓端 驅動級240及低壓端驅動級250的輸出皆為低態。藉由此 偵測及控制，可以確保馬達於供電不足的狀況下停止運作。 此外，高壓電壓位準轉換器220與低壓電壓位準轉換 器230中所採用之電路，如第三圖所示，其係為常見之電 壓位準轉換器之電路示意圖。 舉例來說，假設輸入邏輯電路210輸入至電壓位準轉 換器輸入端SI的高壓端訊號HD係為高態，其電壓位準等 於VCC;而輸入至電壓位準轉換器輸入端SIB為高壓端訊 號HD的反相訊號，即為低態·其電壓位準等於VSS，於 是電晶體Q3將導通，而電晶體Q4將截止。其中，電壓位 10 200848976 準vi便等於電壓位準VB。 當電晶體Q3導^§ ηp 現低態，其J位二ffff端-將呈 導通後的電晶體吸會使得Q2導通。 現高態，其電壓位準等於νΓ 命出端SOB呈 拖二ΐ 亥輪入訊號的電壓操作範圍轉 t而要的〶壓操作範圍輸出。最後，The high voltage terminal level converter 220 is coupled to the input logic circuit 210 and receives the high voltage terminal signal HD provided by the input logic circuit 210 to further perform conversion of the high voltage terminal signal HD, that is, the high voltage terminal signal HD is provided. The voltage operation level is converted from the original to vss to VB to VSS. In addition, the high voltage level level converter 22 运算 calculates the voltage terminal 讥唬HD to generate a high voltage end output control signal, wherein the high voltage end output control signal HH controls the output of the high voltage end of the gate crane circuit 2 The state (hlgh), and the high-voltage output control signal HL controls the round-out of the high-voltage end of the closed-circuit driving circuit 20 to assume a low state (i 〇 w ). The low voltage voltage level converter 23 is connected to the input logic circuit 21A, and receives the low voltage end signal ld provided by the input logic circuit 21G to perform conversion into the LD, that is, the voltage operation bit of the low voltage end signal LD From the original vcc to Na conversion = . This terminal (4) will control the ship number, and the control pressure == will appear abhorrent or low state. Among them, m, , , converter 230 and low-voltage terminal drive stage 25 are supply voltages for low-voltage voltage level transfer. 8 200848976 The high voltage side driver stage 240 is coupled to the high voltage voltage level converter 22A, which internally includes the driver stage output elements 241 and 242, wherein the driver stage output elements 24 242 are all - p type metal oxide semiconductor field effect A P-type metal oxide semiconductor field effect transistor (P-type MOSFET) is connected, and a drain terminal of the driving stage wheel-out element 241 is connected to a source terminal (like terminal) of the driver stage output element. When the gate terminal of the driver stage output component 241 receives the high voltage terminal output control signal HH provided by the high voltage voltage level converter 22Q is low, the driver stage output component 241 will be turned on, so that the driver stage output component 241 After that, the output signal of the extreme output is in a high state, that is, the voltage level of the output signal PH is equal to vb. When the gate terminal of the animal drive stage output component 242 receives the high voltage terminal output control signal HL provided by the high voltage voltage level conversion element 220 is low, the driver stage output component 242 will be turned on, so that the source terminal of the driver stage output component 242 is The output signal PH of the output is in a low state, that is, the voltage level of the output signal PH is equal to VSq, and in the initial state, the output signal PH is VS. Moreover, VB and vs can be, for example, 8 〇v and 65 V, respectively, but they may also differ depending on actual application conditions. The low-voltage terminal driver stage 250 is coupled to the low-voltage voltage level converter 230, which internally includes driver stage output elements 251 and 252, wherein the driver stage output element 251 is PM〇S, and the driver stage output element 252 is N-type metal oxide half. N-type metal oxide semiconductor field effect transistor (N-type MOSFET), and the driver stage output element 251 is not extremely connected to the 汲 terminal of the driver stage output element 252. 9 200848976 When the gate terminal of the driver stage output component 251 receives the low voltage terminal output control signal LX provided by the low voltage voltage level converter 230 to be in a low state, the driver stage output component 251 will be turned on, such that the driver stage output component 251 is turned on. The output signal PL outputted by the extreme is in a high state, that is, the voltage level of the output signal PL is equal to VM. When the gate terminal of the driver stage output element 252 receives the low side output control signal LX provided by the low voltage level level converter 230 to be high, the driver stage output element 252 will be turned on, such that the driver stage output element 252 is at the extreme end. The output signal PL of the output is in a low state, that is, the voltage level of the output signal PL is equal to VSS. In the initial state, the output signal PL is VSS. And VSS and VM can be 0V and 15V, respectively, at this time, but they may also differ depending on actual application conditions. The low voltage detector 260 is coupled to the input logic circuit 210 to detect whether the supply power (ie, VM) of the low voltage terminal (the low voltage voltage level converter 230 and the low voltage terminal driver stage 250) is lower than a preset value to further Determining whether to output a control signal to the input logic circuit 210 to control the outputs of the high voltage side driver stage 240 and the low voltage side driver stage 250 are all low. With this detection and control, it is ensured that the motor will stop operating under insufficient power supply. In addition, the circuit employed in the high voltage voltage level converter 220 and the low voltage voltage level converter 230, as shown in the third figure, is a schematic circuit diagram of a common voltage level converter. For example, suppose the input high voltage terminal HD of the input logic circuit 210 input to the voltage level converter input terminal is high, and its voltage level is equal to VCC; and the input to the voltage level converter input terminal SIB is a high voltage end. The inverted signal of the signal HD is low and its voltage level is equal to VSS, so the transistor Q3 will be turned on and the transistor Q4 will be turned off. Among them, the voltage level 10 200848976 quasi vi is equal to the voltage level VB. When the transistor Q3 leads to a low state, its J-bit 2 ffff terminal will be turned on and the transistor will be turned on to make Q2 turn on. In the current state, the voltage level is equal to νΓ. The output terminal SOB is dragged and the voltage operation range of the round-in signal is turned to the desired output range. At last,
«so^ SOB ，來控制南壓端驅動級24Q的切換動作。此時，高网端 =控制訊號HH及HL因為是用以開啟或關閉同^為 s的驅動級輸出元件241及242 ’故其可運作範圍並 不像習知技術般被限制於VS〜VB，而可以運作於VSS〜VB 的範圍之内。 雖然本案係利用第三圖之電壓位準轉換器來作為本 案之南壓電壓位準轉換器22〇及低壓電壓位準轉換器23〇 的實施例，但本發明内容並不受限於此，凡可達到將訊號 之電壓位準轉換的電壓位準轉換器皆係本發明内容之範 根據上述關於閘極驅動電路2〇内部結構方塊之敘述 可知，鬲壓端驅動級24〇的輸出電路係採用pM〇s來作為 驅動級輸出元件242,因此可以避免在一般高壓製程下’， 驅動級輸出元件242採用NM〇S時之基板端（buik)與源 極端之間所產生的高電壓差，以進一步防止基體效應办 effect) ° 為了更進一步地闡述本發明内容中第二圖之閘極驅 動電路2G的運作流程，請參考第四_示，其係為本發明 200848976 内容之閘極驅動方法之流程圖。首先，透過訊號輸入端HI 及LI輸入一組輸入訊號至邏輯電路21〇中，如步驟S41〇。 由於閘極驅動電路20在運作過程中，低電壓偵測器 260會隨時偵測低壓端（包含低壓電壓位準轉換器230及 低壓端驅動級250)之供應電源VM，以監控低壓端供應 電源VM是否小於一預設值，如步驟S42〇。因此，輸入邏 輯電路210即可根據低電壓偵測器26〇偵測的結果來決定 其輸出的結果。 當低壓端供應電源VM小於此預設值時，如步驟 S421 ’低電壓偵測器26〇會輸出一控制訊號至輸入邏輯電 路210，迫使輪入邏輯電路21〇透過高壓端訊號HD來控 制南壓端驅動級240的輸出訊號ph為低態，以及透過低 壓端訊號LD來控制低壓端驅動級2 5 〇的輸出訊號p L也為 低態。 Μ低壓纟而供應電源VM大於或等於此預設值時，如步 驟S430 ’輸入邏輯電路21〇直接將透過訊號輸入端ΗΙ、 LI所接收到的輸入訊號轉換成高壓端訊號hd及低壓端訊 號LD，並且分別將高壓端訊號hd傳送至高壓電壓位準轉 換器220 ’以及將低壓端訊號LD傳送至低壓電壓位準轉 換器230。 接著’如步驟S440，高壓電壓位準轉換器220會利用 其内部之電路結構，來轉換高壓端訊號HD的電壓操作位 準，也就是根據高壓端訊號HD的狀態，來決定輸出至高 壓端驅動級240的兩個反相的高壓端輸出控制訊號HH及 HL的狀態，以進—步決定高壓端最後輸出的輸出訊號ph 的狀態。 200848976 而另一方面，如步驟S440，低壓電壓位準轉換器230 也會利用其内部之電路結構，來轉換低壓端訊號LD的電 壓操作位準，也就是根據低壓端訊號LD的狀態，來決定 輸出至低壓端驅動級250的低壓端輸出控制訊號LX的狀 態，以進一步決定低壓端最後輸出的輸出訊號PL的狀態。 此外，此時低壓端輸出控制訊號LX因為是用以開啟或關 閉驅動級輪出元件251及252,理論上可以運作於VSS〜VM 的範圍之内。 由於高壓端輸出控制訊號HH係傳送至高壓端驅動級 240之驅動級輸出元件241，用以控制驅動級輸出元件241 的開關切換；而高壓端輸出控制訊號HL則係傳送至高壓 端驅動級240之驅動級輸出元件242，用以控制驅動級輸 出元件242的開關切換。另外一方面，低壓端輸出控制訊 號LX係傳送至低壓端驅動級250之驅動級輸出元件251 及252,用以控制驅動級輸出元件251及252的開關切換。 因此，如步驟S450，高壓端驅動級240將根據高壓端 輸出控制訊號HH及HL的狀態’來決定相對應的驅動級 輸出元件241、242的開關切換，以控制高壓端的輸出訊號 PH係為高態或低態；低壓端驅動級250將根據低壓端輸出 控制訊號LX的狀態，來決定驅動級輸出元件251、252的 開關切換，以控制低壓端的輸出訊號PL係為高態或低態。 當高壓端輸出控制訊號HH為低態，而高壓端輪出控 制訊號HL·為高態時，高壓端輸出控制訊號HH會使驅動 級輸出元件241導通，高壓端輸出控制訊號HL則會使驅 動級輸出元件242截止。因此’此時的南壓端的輸出係為 高態，也就是輸出訊號PH等於電壓位準VB。 13 200848976 當高壓端輸出控制訊號HH為高態，而高壓端輸出控 制訊號HL為低態時，高壓端輸出控制訊號HH會使驅動 級輸出元件241截止，高壓端輸出控制訊號HL則會使驅 動級輸出元件242導通。因此，此時的高壓端的輪出係為 低態，也就是輸出訊號PH等於電壓位準VS。 當低壓端輸出控制訊號LX為低態時，低壓端輪出控 制訊號LX會使驅動級輸出元件251導通，同時低壓端輸 出控制訊號LX也會使驅動級輸出元件252截止。因此， 此時的低壓端的輸出係為高態，也就是輸出訊號PL等於 電壓位準VM。 當低壓端輸出控制訊號LX為高態時，低壓端輸出控 制汛號LX會使驅動級輸出元件251截止，同時低壓端輸 出控制訊號LX也會使驅動級輸出元件252導通。因此， 此日守的低壓端的輸出係為低態，也就是輸出訊號PL等於 電壓位準VSS。 由上述之閘極驅動電路20的結構及其閘極驅動方法 可知’本發明内容利用高壓電壓位準轉換器220，直接將 輪入端（輸入邏輯電路21〇)的高壓端控制訊號的電壓操 ，位準範圍由VCC至VSS轉換為VB至VSS，再根據高 壓電壓位準轉換器轉換後的訊號，來控制高壓端驅動級 〇產生咼壓端之輸出訊號，而且該輸出訊號的電壓操作 位準範圍為VB至vs ;同時利用低壓電壓位準轉換器 、，將輸入端（輸入邏輯電路210)的低壓端控制訊號的 兒壓知作位準範圍由VCC至VSS轉換至VM至VSS，再 根f低壓電壓位準轉換器轉換後的訊號，來控制低壓端驅 、、、產生低壓端之輸出訊號，而該輸出訊號的電壓操 200848976 作位準範圍為VM至VSS。如此一來，由於不必要的元件 已完全被省略，此閘極驅動電路20將可大幅降低電路元件 的使用，因而減少成本的耗費。 根據本發明之閘極驅動電路之特性，其可以應用於驅 動三相馬達，如第五圖所示，閘極驅動電路50利用驅動器 51、52及53來分別提供驅動訊號給推動三相馬達的N型 功率金屬氧化半導體場效電晶體的閘極，使三相馬達轉動。 本發明内容所提供之優點在於，直接利用電壓位準轉 換器將輸入端的電壓位準範圍轉換，以降低電路元件的使 用，並減少成本的耗費。 本發明内容所提供之另一優點在於，高壓端係採用串 接的PMOS來作為驅動級輸出元件，以避免在一般高壓製 程下，串接的PMOS連接至NMOS時，NMOS基板端與 源極端之間所產生的高電壓差所造成的基體效應。 所附圖式僅提供參考與說明用，並非用來對本發明加 以限制者。惟以上所述僅為本發明之較佳可行實施例，非 因此即侷限本發明之專利範圍，故舉凡運用本發明說明書 及圖示内容所為之等效結構變化，均同理包含於本發明之 範圍内，合予陳明。 【圖式簡單說明】 第一圖係為習用技術之閘極驅動電路示意圖； 第二圖係為本發明内容之閘極驅動電路之方塊示意圖； 第三圖係為常見之電壓位準轉換器之電路示意圖； 第四圖係為本發明内容之閘極驅動方法之流程圖；以及 第五圖係為本發明内容之閘極驅動電路之方塊示意圖。 15 200848976 【主要元件符號說明】 閘極驅動電路 10,20,51，52,53 三相閘極驅動器 50 • 輸入邏輯電路 110,210 - 脈衝產生器 120 高壓電壓位準轉換器 130,220 低壓電壓位準轉換器 230 高壓端驅動級 160,240 # 低壓端驅動級 170,250 脈衝濾波器 140 閂鎖電路 150 低電壓偵測器 180,260«so^ SOB, to control the switching action of the south end drive stage 24Q. At this time, the high network end = control signals HH and HL are used to turn on or off the driver stage output elements 241 and 242 of the same s', so the operable range is not limited to VS~VB as in the prior art. And can operate within the scope of VSS~VB. Although the present embodiment uses the voltage level converter of the third figure as an embodiment of the south voltage voltage level converter 22 and the low voltage level level converter 23A of the present case, the present invention is not limited thereto. The voltage level converter which can achieve the voltage level conversion of the signal is the content of the present invention. According to the description of the internal structure of the gate driving circuit 2, the output circuit of the driving terminal 24〇 is known. By using pM〇s as the driver stage output element 242, it is possible to avoid the high voltage difference between the substrate and the source terminal when the driver stage output element 242 is NM〇S in the general high voltage process. In order to further prevent the operation process of the gate driving circuit 2G of the second figure in the present invention, please refer to the fourth embodiment, which is the gate driving method of the invention of 200848976. Flow chart. First, a set of input signals are input to the logic circuit 21 through the signal input terminals HI and LI, as in step S41. Since the gate driving circuit 20 is in operation, the low voltage detector 260 detects the supply power VM of the low voltage terminal (including the low voltage voltage level converter 230 and the low voltage side driver stage 250) to monitor the low voltage end supply power. Whether the VM is smaller than a preset value, as in step S42. Therefore, the input logic circuit 210 can determine the output of the low voltage detector 26 based on the result of the detection. When the low-voltage end supply power VM is less than the preset value, in step S421, the low-voltage detector 26 outputs a control signal to the input logic circuit 210, forcing the wheel-in logic circuit 21 to pass the high-voltage signal HD to control the south. The output signal ph of the terminal driver stage 240 is in a low state, and the output signal p L of the low-voltage terminal driver stage 2 5 透过 is also low through the low-voltage terminal signal LD. When the power supply VM is greater than or equal to the preset value, in step S430, the input logic circuit 21 directly converts the input signal received through the signal input terminals LI, LI into the high voltage end signal hd and the low voltage end signal. The LD transmits the high voltage terminal signal hd to the high voltage voltage level converter 220' and the low voltage terminal signal LD to the low voltage voltage level converter 230, respectively. Then, as in step S440, the high voltage voltage level converter 220 uses its internal circuit structure to convert the voltage operation level of the high voltage terminal signal HD, that is, according to the state of the high voltage terminal signal HD, to determine the output to the high voltage terminal drive. The two inverted high voltage terminals of stage 240 output the states of control signals HH and HL to further determine the state of the output signal ph that is output last at the high voltage terminal. 200848976 On the other hand, in step S440, the low voltage voltage level converter 230 also uses its internal circuit structure to convert the voltage operation level of the low voltage terminal signal LD, that is, according to the state of the low voltage terminal signal LD. The output to the low-voltage side of the low-voltage terminal driver stage 250 outputs the state of the control signal LX to further determine the state of the output signal PL finally outputted at the low-voltage side. In addition, at this time, the low-voltage terminal output control signal LX is theoretically operable within the range of VSS to VM because it is used to turn on or off the driver-stage wheel-out elements 251 and 252. The high-voltage output control signal HH is transmitted to the driving stage output component 241 of the high-voltage terminal driving stage 240 for controlling the switching of the driving-stage output component 241; and the high-voltage output control signal HL is transmitted to the high-voltage terminal driving stage 240. The driver stage output component 242 is configured to control the switching of the driver stage output component 242. On the other hand, the low side output control signal LX is transmitted to the driver stage output elements 251 and 252 of the low side driver stage 250 for controlling the switching of the driver stage output elements 251 and 252. Therefore, in step S450, the high-voltage terminal driving stage 240 determines the switching of the corresponding driving stage output elements 241, 242 according to the state of the high-voltage terminal output control signals HH and HL to control the output signal PH of the high-voltage terminal to be high. State or low state; the low-voltage terminal driver stage 250 will determine the switching of the driver stage output components 251, 252 according to the state of the low-voltage terminal output control signal LX to control the output signal PL of the low-voltage terminal to be high or low. When the high-voltage terminal output control signal HH is in a low state and the high-voltage terminal output control signal HL· is in a high state, the high-voltage terminal output control signal HH causes the driving-stage output component 241 to be turned on, and the high-voltage terminal output control signal HL causes the driving. Stage output element 242 is turned off. Therefore, the output of the south voltage terminal at this time is high, that is, the output signal PH is equal to the voltage level VB. 13 200848976 When the high-voltage output control signal HH is high and the high-voltage output control signal HL is low, the high-voltage output control signal HH will turn off the driver-level output component 241, and the high-voltage output control signal HL will drive Stage output element 242 is turned "on". Therefore, the wheel of the high voltage terminal at this time is in a low state, that is, the output signal PH is equal to the voltage level VS. When the low-voltage side output control signal LX is in a low state, the low-voltage terminal output control signal LX turns on the driving stage output element 251, and the low-voltage side output control signal LX also turns off the driving stage output element 252. Therefore, the output of the low voltage terminal at this time is high, that is, the output signal PL is equal to the voltage level VM. When the low side output control signal LX is high, the low side output control signal LX will turn off the drive stage output element 251, and the low side output control signal LX will also turn on the drive stage output element 252. Therefore, the output of the low-voltage terminal of this day is low, that is, the output signal PL is equal to the voltage level VSS. According to the structure of the gate driving circuit 20 and the gate driving method thereof, the present invention utilizes the high voltage voltage level converter 220 to directly control the voltage of the high voltage terminal control signal of the wheel input terminal (input logic circuit 21A). The level range is converted from VCC to VSS to VB to VSS, and then according to the signal converted by the high voltage voltage level converter, the output signal of the high voltage terminal driving stage is generated, and the voltage operation bit of the output signal is The quasi-range is VB to vs. At the same time, the low-voltage voltage level converter is used to convert the voltage of the low-voltage control signal of the input terminal (input logic circuit 210) into a level range from VCC to VSS to VM to VSS. The signal converted by the low-voltage voltage level converter is used to control the low-voltage end drive, and the output signal of the low-voltage end is generated, and the voltage operation of the output signal is 200848976 as the level range from VM to VSS. As a result, since the unnecessary components are completely omitted, the gate driving circuit 20 can greatly reduce the use of circuit components, thereby reducing the cost. According to the characteristics of the gate driving circuit of the present invention, it can be applied to drive a three-phase motor. As shown in FIG. 5, the gate driving circuit 50 uses the drivers 51, 52, and 53 to respectively provide driving signals for driving the three-phase motor. The gate of the N-type power metal oxide semiconductor field effect transistor rotates the three-phase motor. SUMMARY OF THE INVENTION An advantage provided by the present invention is that the voltage level range of the input is directly converted by a voltage level converter to reduce the use of circuit components and reduce the cost. Another advantage provided by the present invention is that the high voltage end uses a series connected PMOS as the driving stage output element to avoid the NMOS substrate end and the source terminal when the serial PMOS is connected to the NMOS under the general high voltage process. The matrix effect caused by the high voltage difference generated between them. The drawings are provided for reference and description only and are not intended to limit the invention. However, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Therefore, equivalent structural changes that are made by using the specification and the contents of the present invention are equally included in the present invention. Within the scope, it is combined with Chen Ming. BRIEF DESCRIPTION OF THE DRAWINGS The first figure is a schematic diagram of a gate drive circuit of a conventional technology; the second figure is a block diagram of a gate drive circuit of the present invention; the third figure is a common voltage level converter The fourth diagram is a flowchart of the gate driving method of the present invention; and the fifth diagram is a block diagram of the gate driving circuit of the present invention. 15 200848976 [Main component symbol description] Gate drive circuit 10, 20, 51, 52, 53 Three-phase gate driver 50 • Input logic circuit 110, 210 - Pulse generator 120 High voltage voltage level converter 130, 220 Low voltage voltage level converter 230 high voltage side driver stage 160, 240 # low voltage side driver stage 170, 250 pulse filter 140 latch circuit 150 low voltage detector 180, 260
驅動級輸出元件 241，242,251，252 電壓位準 VCC，VSS，VB，VS，VM，V1 訊號輸入端 HIN，LIN5HI，LI，HI 1， LIl，HI2，LI2，ffl3，LB ί 高壓端訊號 HDDriver Stage Output Components 241, 242, 251, 252 Voltage Levels VCC, VSS, VB, VS, VM, V1 Signal Inputs HIN, LIN5HI, LI, HI 1, LIl, HI2, LI2, ffl3, LB ί High Voltage Signal HD
低壓端訊號 LD 高壓端輸出控制訊號 HH，HL 低壓端輸出控制訊號 LX ‘ 電壓位準轉換器輸入端 SI，SIB 電壓位準轉換器輸出端 S Ο，S OB 電晶體 Q1，Q2，Q3，Q4 輸出訊號 AT，AB，PH，PL，PH1，PL1， PH2，PL2，PH3，PL3 16Low-voltage terminal signal LD High-voltage terminal output control signal HH, HL Low-voltage terminal output control signal LX ' Voltage level converter input terminal SI, SIB voltage level converter output terminal S Ο, S OB transistor Q1, Q2, Q3, Q4 Output signals AT, AB, PH, PL, PH1, PL1, PH2, PL2, PH3, PL3 16