TW200847706A - MIMO transmission with explicit and implicit cyclic delays - Google Patents

Abstract

Techniques for transmitting data using a combination of explicit cyclic delay and implicit cyclic delay are described. A transmitter may perform first processing for cyclic delay diversity (or explicit cyclic delay processing) based on a first set of cyclic delay values known to a receiver. The transmitter may perform precoding based on a precoding matrix either before or after the explicit cyclic delay processing. The transmitter may perform second processing for cyclic delay diversity (or implicit cyclic delay processing) based on a second set of cyclic delay values unknown to the receiver. The transmitter may perform both explicit and implicit cyclic delay processing for data and may perform only implicit cyclic delay processing for pilot. One entity may select the first set of cyclic delay values and inform the other entity. The transmitter may autonomously select the second set of cyclic delay values without informing the receiver.

Description

200847706 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present disclosure relates generally to communications, and more particularly to techniques for transmitting data in a wireless communication system. U.S. Provisional Patent Application Serial No. 60/888,494, filed on Feb. 6, 2007, entitled " EFFICIENT CYCLIC DELAY DIVERSITY BASED PRECODING,, the priority of which has been given to its assignee, and This is incorporated herein by reference. [Prior Art] Wireless communication systems are widely deployed to provide various communication content, such as voice, video, packet data, messaging, broadcast, etc. These wireless systems can be Multiple access systems that support multiple users by sharing available system resources. Examples of such multiple access systems include code division multiple access (CDMA) systems, time division multiple access (TDMA) systems, and frequency division multiple access. (FDMA) system, quadrature FDMA (〇FMDA) system and single carrier FDMA (SC-FDMA) system. Wireless communication system can support multiple input multiple output (MIM〇) transmission. For ΜΙΜΟ, the transmitter can be used more Transmission antennas for transmitting data to receivers equipped with multiple (reverse) receiving antennas. The multiple transmission and receiving antenna formations can be used to increase throughput and / Or improve the reliability of the channel. For example, the transmitter can transmit up to one data stream from a single transmission antenna to improve the throughput. Or, the transmitter can transmit a single data stream from all the transmission antennas to improve reliability. Sex. In any way, you should send the μιμ〇 transmission in a way that achieves good performance. 129018.doc 200847706 [Summary] This paper describes the technique of transmitting data using a group of people with explicit cyclic delay and implicit cyclic delay. It can be applied in the sub-carrier in the frequency domain = by shifting the sample in the day to achieve the 彳 环 ring (4). For the explicit 延迟 delay, different phases can be applied between the sub-carriers of each antenna. The ramp wave, and the receiver knows the phase ramp of all antennas. The receiver can perform a wide complement process to consider the explicit cyclic delay. For implicit cyclic delay, the old phase can apply different phase ramps between the subcarriers of each antenna. And receiving the phase ramp of the antennas that are crying unknown. The transmitter can transmit the pilots with the same implicit cyclic delay. The receiver can be based on the frequency derived from the pilots. Estimating to consider the implicit cyclic delay. In one design, the transmitter may perform a first process of cyclic delay diversity (or explicit cyclic delay processing) based on a first set of cyclic delay values known to the receiver. The precoding is performed based on the precoding matrix before or after the explicit cyclic delay processing. The transmitter may perform the second processing (or implicit cyclic delay processing) of the cyclic delay diversity based on the second set of cyclic delay values unknown to the receiver. Clear and implicit cyclic delay processing can be performed on the data and only implicit cyclic delay processing can be performed on the pilot. An entity (a) column, such as a transmitter or receiver, can be self-complexing delays (which can include zero delay, 1 small) A delay is selected among the delays and large delays and the selected delay can be sent to another entity (eg, a receiver or transmitter). The first set of cyclic delay values can be determined based on the selected delay. The transmitter can autonomously (e.g., pseudo-randomly) select the second set of cyclic delay values without notifying the receiver. Various aspects of the present disclosure and the features of the 129018.doc 200847706 are described in further detail below. [Embodiment] The techniques described herein may be used in various wireless communication systems, such as CDMA, TDMA, FDMA, OFDMA, SC-FDMA, and other systems. The term 11 system "and" network is often used interchangeably. A CDMA system may implement a radio technology such as Universal Terrestrial Radio Access Technology (UTRA), cdma2000, etc. UTRA includes Wideband CDMA (W-CDMA) and other CDMA variants. Cdma2000 covers the S-2000, IS-95 and IS-856 standards. TDMA systems can implement radio technologies such as the Global System for Mobile Communications (GSM). OFDMA systems can be implemented such as Evolved UTRA (E-UTRA), Ultra Mobile Broadband (UMB) , IEEE 802.1 l (Wi-Fi), IEEE 802.16 (WiMAX) > IEEE 802.20 > Flash-OFDM, etc. UTRA and E-UTRA are part of the Universal Mobile Telecommunications System (UMTS). 3GPP Long Term Evolution ( LTE) is an upcoming release of UMTS using E-UTRA. UTRA, E-UTRA, UMTS, LTE and GSM are described in the literature from an organization named ''Third Generation Partnership Project,' (3GPP). Cdma2000 and UMB are described in documents from an organization named "3rd Generation Partnership Project 2" (3GPP2). These various radio technologies and standards are known in the art. Node B 110 and a plurality of Wireless multiple access communication system 100 of a device (UE). A Node B may be a fixed station that communicates with a UE and may also be referred to as an evolved Node B (eNB), a base station, an access point, etc. Each Node B 110 Communication coverage is provided for a particular geographic area. The UEs 120 may be dispersed throughout the system, and each UE may be fixed or mobile. The UE may also be referred to as a mobile station, a terminal, an access terminal, a subscriber unit, by 129018.doc 200847706, The UE can be a cellular phone, a personal digital assistant (PDA), a wireless data modem, a wireless Up device, a palm-sized device, a laptop computer, a wireless phone, etc. The UE can be connected via the downlink and the uplink. Transmit and communicate with Node B. Downlink (or forward link) refers to the communication link from Node B to U]E, and uplink (or reverse link) refers to from UE to Node B Communication link 囷2 shows a block diagram of the design of node b 110 and UE 12〇, node b 110 and UE 120 are one of node B and one of UE* in Fig. 1. section ", 'occupied B 11〇 is equipped with multiple (τ) antennas 23仏 to 234t. It is equipped with a night (R) antenna 252a 252r. Each of the antennas 234 and 252 can be considered a physical antenna. At point B 11〇, the τχ data processor 22 can receive poor material from the data source 212, based on one or more modulation and coding mechanisms. To process (eg, encode and symbol map) the material and provide data symbols. As used herein, a feed is a symbol for a data, a pilot symbol is a symbol for a pilot, and 苻諕 can be a real value or a complex value. The data symbols and pilot symbols can be modulation symbols from a de-k mechanism such as PSK or QAM. The pilot is known in advance from Node B and UE. The τ χ MIM 〇 processor 23 处理 processes the batten symbols and pilot symbols as described below and provides τ output symbol streams to the modulators (乂00) 23 to 232t. Each modulator 232 can process its output symbol stream (e.g., for OFDM) to obtain an output sample stream. Each modulator 232 can further condition (e.g., convert to analog, filter, amplify, and upconvert) its output sample stream and generate a downlink signal. The downlink signals 129018.doc -10- 200847706 from the modulators 232 & to 2321 can be transmitted via the antennas 234 & 23 to respectively. At UE 120, R antennas 252a through 252r may receive T downlink signals from Node B 110, and each antenna 252 may provide the received signals to an associated demodulation transformer (DEMOD) 254. Each demodulation transformer 254 can condition (eg, filter, amplify, downconvert, and digitize) the received signal to obtain samples, and can further process the samples (eg, for OFDM) to obtain the received samples. symbol. Each demodulation transformer 254 can provide the received data symbols to the RX processor 260 and provide the received pilot symbols to the channel processor 294. The channel processor 294 can estimate the response from the node Β 110 to the UE 120 channel based on the received pilot symbols and provide the ΜΙΜΟ channel estimate to the RX ΜΙΜΟ processor 260. The RX processor 260 can perform frame detection on the received data symbols based on the channel estimate and provide detected symbols, which are estimates of the transmitted data symbols. The RX data processor 270 can process (e.g., symbol demap and decode) the detected symbols and provide the decoded data to the data store 272. UE 120 may evaluate channel conditions and generate feedback information, which may include various types of information as described below. Feedback information and data from data source 278 may be processed (e.g., encoded and symbol mapped) by data processor 280, spatially processed by processor 282, and further processed by modulators 254a through 254r to generate R uplinks. The signals may be transmitted via antennas 252a through 252r for the R uplink signals. At Node B 11〇, R uplink signals from UE 120 may be received by antennas 234a through 234t, processed by demodulation transformers 232a through 232t, spatially processed by RX(R) processor 236, and 129018.doc 11 200847706 by RX Data processor 238 further processes (e.g., symbol demaps and decodes) to recover feedback information and data transmitted by UE 120. The controller/processor 240 can control the transmission of data to the UE 120 based on the feedback information. Controllers/processors 240 and 29A can direct operation at node b u 〇 & UE 120, respectively. The memories 242 and 292 can store data and code for the node B ιι〇 and the UE 120, respectively. Scheduler 244 can schedule UE 120 and/or other UEs for data transmission on the downlink and/or uplink based on feedback received from all of them.

The techniques described herein can be used for transmissions on the downlink as well as on the uplink. For the sake of clarity, certain aspects of the techniques are described below for the transmission on the downlink in LTE. Lte uses orthogonal frequency division multiplexing (OFDM) on the downlink and single carrier frequency division multiplexing (SC_FDM) on the uplink. The 0FDM and sc_fdm divide the system bandwidth into a plurality of (K) orthogonal subcarriers, which are also commonly referred to as carrier frequencies, bins, and the like. Each subcarrier can be modulated by data. In general, the modulation symbols are transmitted in 频FDM in the frequency domain and the modulation symbols are transmitted in SC-FDM in the time domain. Node B 110 may simultaneously transmit L data symbols via L layers on each-subcarrier in each symbol period, where substantially the n-layer may correspond to the n-dimension of each sub-carrier used for transmission. The Node Bm can use various transport mechanisms to transmit data symbols. In the -state, one of the cyclic delay and the implicit cyclic delay can be clarified to transmit the gross ΜΙΜΟ transmission. Precoding can be used to further transmit the transmission. Clear loop delays, implicit loops can be performed in various ways. 129018.doc 200847706 Delay and precoding. In one design, Node B 110 may process the data symbols for each subcarrier as follows: ' yM) = c(8) WD(4) Ud(A〇, Equation (1) where: da) is moxibustion containing subcarriers to be passed through a symbol period [Lxl vector of L data symbols transmitted by each layer, L LxL layer to virtual antenna mapping matrix, 1 > (free) is sub-carrier 々 lxl explicit cyclic delay matrix, W is TxL precoding matrix, C ( Moxibustion is a τ χ implicit cyclic delay matrix of 曰 ij carrier ,, and h(4) is a Τχΐ vector of τ output symbols of data for τ transmission antennas containing subcarriers exempted in one symbol period.

Node B 1 1 导 can process pilot symbols for each subcarrier A as follows: yP(k) = c(k)P(k) JU ' Equation (2) where Ρβ) is contained in a symbol period The Txl vector of the pilot symbols transmitted on the subcarrier moxibustion, and (9) is the Txl vector of the T output symbols for the pilots of the plurality of transmission antennas on the subcarrier moxibustion in a symbol period. Equations (1) and (2) are for a subcarrier & The same processing can be performed for each subcarrier used for transmission. In the description herein, a matrix may have one or more rows. The precoding matrix 砰 can be used to form up to 虚拟 virtual force lines with τ solid antennas 23 to 23 shots. Each virtual antenna can be formed by one line. The $ symbol can be multiplexed by W-line and can then be sent on the virtual antenna and the two 129018.doc -13- 200847706 τ physical antennas. w can be based on a Fourier matrix or some other matrix. W can be selected from a set of precoding matrices. The layer-to-virtual antenna mapping matrix u can be used to map data symbols for L layers to L virtual antennas selected from τ available virtual antennas. U can be defined based on the layer-to-virtual antenna mapping selected for use. ϋ may also be an identity matrix 1 having one along the diagonal and zero at another. The same or not ‘the same mapping matrix can be used for one subcarrier. f'. Defining the cyclic delay matrix D (phantom can be used to achieve cyclic delay diversity, which can provide beamforming gain, frequency selective scheduling gain, and/or diversity increase JHL D(A) can also be used to achieve layer permutation (layer permUtati〇 n), which may have particular advantages. D (moxibustion) may be generated based on a delay selected from one of a set of delays, and the delay may include a large delay greater than a length of the first prefix. The implicit cyclic delay matrix C(k) can also be used to achieve cyclic delay diversity. c (k) can be generated in various ways and can be constrained to be smaller than the first code length of the loop in the design shown in equation (1), after performing the precoding with w after D (the explicit cyclic delay processing is performed magically) Therefore, it is clear that the cyclic delay is applied to the virtual antenna formed by the precoding matrix W (instead of the solid antenna). This design can be used for large delays. 囷3A shows the block diagram of the processor 230a, which implements the equation (1) And (2) and designed for one of the processors 230 at the Node B 110 of Figure 2. Within the data processor 220, the S stream processors 320a through 320s can receive S data streams from the data source 212. , which is substantially 1. Each stream 129018.doc • 14- 200847706 The processor 320 can encode, interleave, scramble and symbol map its data stream to obtain the data stream H f stream can be in each transmission time interval Carrying - conveying blocks or packets. Each stream processor 32 can process its transport block to obtain a codeword and; |## will map the code to the block of the modulation symbol. The terms ", data stream", "transport block", "packet " and "code word" are used interchangeably. Stream processing H32Ga to 32Gs provides 8 data symbol streams. Within the jTX MIM(R) processor 230a, the layer mapper 332 can map the data symbols for the s data streams to the (10) virtual antennas selected for use. In a s-counter, the mapper 332 can map the data symbols for the § data streams to the L layers and then map the data symbols for the [layers to the subcarriers for transmission and the virtual antenna. The explicit cyclic delay processor 334 can multiply the mapped symbols of each subcarrier by the explicit cyclic delay matrix DW. Precoder 336 may multiply the symbols from the processor of each subcarrier with the precoding (four)W and provide the precoded symbols for the (four) waves. Implicit cyclic delay processor 338 can receive the precoded symbols and pilot symbols from precoder 336 and can multiply the symbols of each subcarrier by an implicit cyclic delay matrix (10) to obtain an output symbol. Processor 338 can provide τ output symbol streams to a plurality of modulators 23 2 & to 2321. Each modulator 232 can perform 〇fdm modulation on the respective output symbol streams. Within each modulator 232, a κ-point inverse discrete Fourier transform (idft) can be used to transform the κ output symbols transmitted over a total of [subcarriers in the -OFDM symbol period to obtain κ time domain samples. Useful part. Each time domain sample is a complex value to be transmitted in a sample period. The last C samples of the useful portion can be copied and appended to the front of the useful portion to form an OFDM symbol containing Κ + C samples at 129018.doc -15· 200847706. The copied portion is called the cyclic first code and is used to combat inter-symbol interference (ISI) caused by frequency selective fading. Each modulator 232 can further process its sample stream to produce a downlink signal. Control/processor 240 can receive feedback information from UE 120 and generate control of stream processor 320 and layer mapper 332. The controller/processor 24A may also provide an explicit cyclic delay matrix D (provided to the processor 334, the precoding matrix Wk to the precoder 336 and the implicit cyclic delay matrix c(a) to the processor 338. In another design, Node B 110 may process the data symbols for each subcarrier as follows: y^(^) = C(A:)D(A:)Wud(A:) 5 Equation (3) 0 (media) is a subcarrier-mediated explicit cyclic delay matrix. Node B j 1〇 can process pilot symbols for each subcarrier a as shown in equation (2). The design shown in equation (3) In the case of precoding with w, the explicit cyclic delay processing is performed with D (the magic is performed. Therefore, the explicit cyclic delay is applied to the physical antenna instead of the virtual antenna. This design can be used for zero delay and small delay. Circle 3B shows ΤΧ A block diagram of processor 230b, which implements equations (2) and (3) and is another design of τ χ MIM 〇 processor 23 节点 at node B 丨 1 图 in Figure 2. Within ΤΧ processor 230b , layer mapper 342 can map the data symbols for the S data streams to selected for making The second virtual antenna. The precoder 344 can multiply the mapped symbols of each subcarrier by the precoding matrix W and provide the precoding symbol of the subcarrier. 129018.doc -16- 200847706 Clear Cyclic Delay Processing The 346 may multiply the precoded symbols of each subcarrier by an explicit cyclic delay matrix _. The implicit cyclic delay process 348 may receive symbols and pilot symbols from the processor 346 and may assign symbols for each subcarrier. The implicit cyclic delay matrix c(4) is multiplied to obtain an output symbol. The processor 348 can provide T output symbol streams to the tuned modulator 23 up to 232t. In a re-design, the Node B 110 can be for each subcarrier. Subsequent processing of pilot symbols:

y^W = c(A:) νρ(Λ:) » Equation (4) where V is a unitary matrix. The single matrix matrix is characterized by the attributes w] and W. This means that the rows of V are orthogonal to each other, the columns of ν are also orthogonal to each other, and each row and each column has a unit power. V can be based on a Fourier matrix or a matrix of some other type. The equation (4) is designed to allow, - to transmit, pilots from all of the shell antennas. This design can be used for pilot channel (CPICH), synchronous channel (SCH), and/or other channels.

Various types of precoding matrices can be used for the equations 〇) and (3) shown in (3) ° ° ° ° ° in the film, a set of Q precoding matrices can be defined as follows: W ' = A 'F, for the call ..., ^1 , Equation (5) where ··· is a Fourier matrix, Λ/ is a ζ··································· The elements of the ΤχΤFourier matrix f can be expressed as: ^ -]2π~ , τ, for w = 〇, τ —= , τ — 1, Equation (4) where Λ, ν is the “column and ν of the Fourier matrix” Element in the line. 129018.doc 200847706 In - • design eA, 0 0 Λ / = 0 0 0 phase shift matrix Λ, can be expressed as • ο Ί • 第 the phase of the Vth antenna in equation (7) Q different ί^.Τ-ι may be defined by different or more basic matrices, where ν is the phase/phase shift matrix phase Α/, ν and/or by rotating a phase shift matrix. In the design shown in (5), Q different TxT precoding matrices w can be defined based on the Fourier matrix F and (10) different phase shifting matrices (. Also: in addition to or in addition to the non-Fourier matrix Other single equations define the precoding matrices. The set of precoding matrices may also include an identity matrix of eight for transmitting each layer on the body antenna. For selective virtual antenna transmissions, the Q precoding matrices may be evaluated. Different combinations of rows (or sub-matrices), and precoding matrix w; L providing the best performance The row can be provided as a precoding matrix w, which is substantially BL^T. In a design towel, the cyclic delay matrix can be specified for the group-delay __ group. Each delay can be made with V phases of the ¥ antenna. The ramp wave is associated with: the antenna 〇 can have a zero-phase ramp wave. If the pre-coding is performed as shown in the figure: before the explicit cyclic delay is performed, then V=L, and the V antennas correspond to L selected ones. Virtual antenna. If explicit cyclic delay processing is performed after precoding as shown in Figure 3B, then V = T, and the v antennas correspond to a few physical antennas. The cyclic delay matrix D is defined (the magical dimension can therefore depend on The explicit cyclic delay processing is performed before or after precoding. For the sake of clarity, most of the following description assumes that 129018.d〇 ( -18- 200847706 φ cyclic delay processing is performed before precoding as shown in FIG. 3A. And 〇0) has the dimension LxL. In a design, 0 the set of explicit cyclic delay matrices can be defined as ... 0 0 Equation (8) where is the mth delay, which is the delay interval between consecutive antennas And Dm (the magic is the first delay Indeed cyclic delay matrix.

In the design shown in equation (8), the cyclic delay value kv and the phase ramp of each antenna v (9wv can be expressed as: 'for v = 0, ·, L-丨, and equation (9) 'v-γνν, for v = 〇,,. Equation (1〇) The design in equation (8) uses a uniform interval for the cyclic delay values of the different antennas. The uniform delay interval reduces the signaling additions because it can be based on a single The ^ value defines the cyclic delay value of all L antennas.

In one design, a set of M=3 delays can be defined to include the following: ~=〇, for zero delay, equation (11) L = 2, for small delays, and , for large delays. Equation (12) Equation (13) Small delays can be used to improve beamforming and frequency selective scheduling gains and can be particularly beneficial for low mobility channels, low geometry channels, low rank channels, and the like. Large delays can be used to improve transmit diversity gain and can be adapted for high mobility channels (eg, mobile UEs moving at 30 km/hr or faster), high geometry channels, higher rank channels, time or frequency Roughly opposite 129018.doc -19- 200847706 f and so on. Large delays provide similar performance to zero latency in low mobility channels, which enhances system robustness when feedback information is noisy. The geometric condition is related to the signal noise interference ratio (s leg). Low geometry conditions may correspond to low SINR' and high geometry conditions may correspond to high swr. Rank refers to the number of virtual antennas selected for use in 仏 and is also referred to as spatial multi-step. In one design, zero delay or small delay can be used for rank q transmission, and large delay can be used for rank-2 or higher transmission. The cyclic delay diversity processing with large delay can equalize the SINR of the L layers used for data transmission. In general, a clear cyclic delay matrix can be defined for any number of delays and any particular delay. For example, an explicit cyclic delay matrix can be defined for small delays of ^=1 or some other value, for large delays less than K/L or greater than K/L, and the like. As shown in equations (8) and (9), the cyclic delay values of the different antennas may have a uniform spacing. The cyclic delay values of different antennas may also have non-uniform spacing. In general, the small delay can be any value less than the length of the loop first code, and the large delay can be any value greater than the length of the loop first code. In one case, the implicit cyclic delay matrix C0) can be defined as: 1 0 ο Ί 〇e κ ... π CW= !:·..: Equation (14) _ .2 ££r-ljfc 0 0 ^ κ where G is the implicit cyclic delay value of the physical antenna ί. The phase ramp β of each physical antenna ί can be expressed as: 2ττ for Bu 0,·",Τ-1, Equation (15) where Θ. = = 0. 129018.doc -20- 200847706 In general, any set of implicit cyclic delay values can be used for the τ physical antennas. The implicit cyclic delay values may be pseudo-random values or may be selected to achieve a value that is good. The implicit cyclic delay value should be shorter than the loop first code length c, as follows: -C<G <c, for divination, T -i Equation (16) The constraint in equation (16) ensures that it is based on implicit The channel estimate of the pilot of the cyclic delay transmission is not excessively degraded due to the aliasing effect. In the f-design, 'each delay can be given by an integer number of samples—in this design, by: delay in the ring. In the other ... widely known as "knife to achieve implicit loop ^, by a non-integer sample" "per-real antenna antenna fe-type cyclic delay value ^., beans in the sigh juice, you can define a basic set of Ding For example, its too _ L-type 裱 delay value 〇, 卜 2 T1 I 仏 money delay value may include a cyclic delay of 2...T-1. The receiver may pseudo-randomly from the 纟 and the soil delay value is for the entity The antenna is 〇 to τ, and the cyclic cycle delay value is used. This material can be confirmed as (4) Τ Γ Γ υ 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐 隐The method is for the delay value of the ring. The implicit dew ~ heart " antenna derogatory and choose the implicit loop shield delay value can be no longer at all. ^ Time slowly changes 'parent's static value, period, I right η + meditation value may be frequent (for example, each symbol Ή has a plurality of symbol periods - when the #付号周 subframe, etc.) change the dynamic value. The equation shown in equation (1) + 1290l8.doc 5, the equation shown in equation (1)) - 200847706 with large delay The processing of symbols can be expressed as: rv, public, ί 1 〇] Π 0 ... 〇Ί 'yd, 〇W _ 1 1 0 , · · Q - 0 e K q 1 ·: '· : W Ί 〇0 Jink 0 e J h 0 u • dQ(ky di(k) _々τ-丨Π Π .ln(L-\)ky/(*) UU · *. β κ C(k) 0 〇... ey L The processing of the pilot symbols can be expressed as r, Π 〇··· η 1 Equation (17) ' yPAk)" yP, 'W 丄υ ... 〇, κ .·· : : . 0 0 "P〇(k) P'(k) yPj-^k) j _〇ο ... 2;^τ_|々V yP\k) PJK ---- β ^ P(4) C(9) Equation (18) The implicit cyclic delay matrix c can be applied in the frequency domain as shown in equation (1) (the magic and the matrix can be a subcarrier based function. c (the magic is provided between the K subcarriers on each physical antenna) Phase ramp (ie, linear phase shift). The slope of the phase ramp can be different for different antennas, and the antenna 〇 can have a zero phase ramp. Applying the phase ramp in the frequency domain is equivalent to the time The cyclic shift of the useful portion of the OFDM symbol is performed in the domain. Ding Wei 4 shows an example of applying implicit cyclic delay in the daily defensive domain. In this example, T = 4 and each integer antenna is given by an integer number of samples. The useful portion of the OFDM symbol of the antenna 可 can be cyclically shifted by zero samples, and the useful portion of the OFDM symbol of the antenna ί can be Cyclic shift; a sample, the useful portion of the antenna OFDM symbol can be cyclically shifted & samples, and the useful portion of the antenna OFDM symbol can be cyclically shifted. ...2 and may be pseudo-random values or may be M in a certain way. 2 ς 'Cycle delay matrix _ and CW can be used to support various delays, including zero 129018.doc -22- 200847706 Delay, small delay, large delay and the cyclic delay value of different antennas - = 'average-interval. These matrices also reduce evaluation complexity (for selection-delay in possible delays) and signaling additions (for notification of selected delays). This delay can be chosen in a variety of ways.

In a design, Node B may select for each UE - a clear delay and may send the selected delay to the fairy. In another design, Node B may select for all UEs that are served by Point B, which are explicitly delayed and may broadcast or transmit delays to such UEs. In yet another design, node b may limit the set of delays differently for each rank in order to reduce UE computational complexity and feedback additions. For example, t ' can allow zero delay for rank ^, allow zero delay and large delay for rank 2, and so on. In one design, the UE may evaluate different possible = coding matrices and different possible delays based on a performance metric, and may choose to have the best performance, precoding matrix and delay. For each possible combination of precoding matrix % and delay ^, the UE can calculate the effective μιμ channel estimate based on the ΜΙΜΟ channel estimate η (the magic, the precoding matrix w, and the explicit delay ice). The UE can evaluate different hypotheses. Each hypothesis corresponds to a different precoding sub-matrix for different combinations of virtual antennas that can be used for data transmission (ie, different sub-trees). The UE can use the detection technology and the available technology. A uniform distribution of transmission power between all hypothetical virtual antennas is used to estimate a set of sinrs for this hypothesis. Then each SINR can be mapped to capacity based on the capacity function and all virtual antennas for each hypothesis can be accumulated The capacity of the κ subcarriers to obtain the total valley of this hypothesis. After evaluating all the assumptions that the precoding matrix and the explicit cyclic delay value can be combined with 129018.doc -23- 200847706, the UE can select the maximum total capacity. The best assumption of the optimal combination of precoding matrix and delay. The UE can use the precoding submatrix and delay of the best hypothesis as the precoding moment to be used for data transmission. W and delay to transmit. The precoding matrix W may contain L optimal lines for L selected virtual antennas. The UE may also determine S data streams to be transmitted on the L selected virtual antennas. S SINRs may be determined based on SINRs for subcarriers and virtual antennas of each data stream. The UE may also determine S channel quality indicators (CQIs) based on SINRs of the S data streams. The CQI value may include an average SINR, a modulation and coding mechanism (MCS), a packet format, a transmission format, etc. The UE may send S CQI values of the S data streams or may send a basic CQI value and a difference CQI. The basic CQI value may represent the SINR of the first decoded data stream, and the difference CQI value may represent the difference between the SINRs of the two data streams. In one design, the Node B may arbitrarily select each physical antenna. Implicit cyclic delay value. Node B can transmit pilot symbols and data symbols by the same implicit cyclic delay processing, and the UE can estimate the channel response based on the pilot symbols. In this case, the channel estimation will include the actual ΜΙΜΟChannel response The implicit cyclic delay matrix applied by the node 。. The phase shift caused by the implicit cyclic delay matrix can be perceived by the UE as part of the ΜΙΜΟ channel fluctuation, and the UE does not need to know the implicit cyclic delay value of each antenna. The implicit cyclic delay matrix transmits the pilot, and the node 任意 can arbitrarily select and change the implicit cyclic delay value, and the change will be obvious for the UE. 129018.doc -24- 200847706 by the L virtual antennas Using a small number of explicit delays (e.g., zero delay, small delay, and large delay) with a uniform delay interval, the signaling add-on between the Node B and the UE and/or the selection complexity at the UE can be reduced. Node B can select and apply various implicit cyclic delay values without having to notify the UE.

5 shows a block diagram of the design of the RX® processor 260 and the RX data processor 270 at the UE 120 in FIG. The pilot symbols from the demodulation transformer 25乜 to 25 bamboo can be expressed as: Equation (20) rp(^) = H(^)C(A:)Vp(^) » 〜, two... Where: Η(4) It is the RxT MIM channel matrix of subcarrier moxibustion, and %(4) is the Rx丨 vector of R received pilot symbols for R receiving antennas on the subcarrier moxibustion in one symbol period. Equation (a) may be applicable if the pilot symbols are transmitted as shown in equation (2). Equation (2〇) may be applicable if the pilot symbols are transmitted as shown in equation (4). The channel estimator 294 can derive (10) the hall channel estimate based on the received pilot symbols. The ΜΙΜΟ channel estimate can be expressed as: Η^) = Η卿), or Equation (21) H 邮(4)=H(4) C〇t)V, ^ and Equation (22) - is the sub-carrier RxT estimated MIM0 The channel matrix equation is called (9) assuming no channel estimation error. Lancome Channel and Zengtuo Packet (4) are the fine-frequency arrays of the group estimates of all subcarriers transmitted. As shown in equations (21) and (22), the ΜΙΜ〇 channel estimate 129018.doc -25- 200847706 includes the actual ΜΙΜΟ channel H (A 〇 and the implicit cyclic delay matrix and the simple matrix v for the pilot (if Within the RX ΜΙΜΟ processor 260, the computing unit 5 1 ΜΙΜΟ can receive the ΜΙΜΟ channel estimate HJ illusion from the channel estimator 294 and the precoding matrix W and the explicit cyclic delay matrix d(a:) selected for use. If the pilot is transmitted as shown in equation (4), processor 260 may remove the simple matrix V for the pilot as follows: = (9) V" Unit 510 may calculate the effective channel estimate as follows:

He#(8)=Η如(4)D(4)WU, or Equation (23) H,W = HeirWWDWU - Equation (24) where H (4) is the RxL effective ΜΙΜΟ channel matrix of the subcarrier moxibustion. H(8) is the valid MIM0 channel observed by the data symbol and about the L virtual antennas used for data transmission. Equation B (23) can be used if Node B performs precoding and explicit cyclic delay processing as shown in Equation (1). If the node performs the precoding as shown in equation (3) and the explicit cyclic delay is self, then the equation (Μ) can be used. Unit 5H) can then be based on the heart (8) and according to the minimum mean square error (mmse), linear mmsE (LMMSE) Forcing zero (ZF; zer〇f〇rcing) or some and his MI is a technique to calculate the space of the ferrometer matrix for each subcarrier (4). Dry W1 from R demodulation transformers lvi 1 ivi w After a job, the K received data symbol streams are transmitted. The MI(10) detector 512 can be used for each spatial filter matrix M (phantom pair R/f carrier free () to the child R received data symbolsΜΙΜΘ Detecting and providing L Detector 018018.doc • 26 - 200847706 stream of the virtual antenna of the 固 固 。 。 。 层 层 。 。 。 。 。 。 。 。 。 。 。 。 。 。 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层 层The layer mapper 342 performs mapping in a complementary manner to demap the detected symbol streams and provides s demapping symbol streams of the S data streams. The data processor 270 includes the S data streams. s stream processors 520a through 520s. Each stream processor 52 〇 symbol demap, descramble, deinterlace The demapped symbol stream is decoded and the decoded data stream is provided. Cap 6 shows the design of the process for transmitting data in a wireless communication system. Process _ can be performed by a transmitter such as Node B, UE#. For the process 600, the transmitter can perform the first processing (or explicit cyclic delay processing) of the cyclic delay diversity based on the known set-cycle delay values (eg, ^ to ^) of the receiver of the data transmission. Block 612). Transmission of the crying 2 cycle delay diversity - processing pre-coding based on the precoding matrix W before or after processing (block 614). The transmitter may be based on a first set of cyclic delay values unknown to the receiver (eg a second processing (or implicit cyclic delay processing) for performing cyclic delay diversity (block 616). The 卞_transmitter may perform the first processing of the cyclic delay diversity on the data and the (10) eg, as in equation (1) or The pilots shown in (3) are processed in the same frequency as (4). The transmitter can, for example, borrow the delay matrix and perform the carrier moxibustion application in the frequency domain. ) by cyclic shift as shown in Figure 4. The bit useful portion performs a second process of cyclic delay diversity in the knowledge domain. In the design, the transmitter may receive 129018.doc -27-200847706 feedback information indicating one of the plurality of delay commands, the plurality of delays may include Zero delay, small delay, and large delay as shown in equations (1) through (10). The transmitter may determine the first set of cyclic delay values based on the delay indicated by the feedback information. The other design transmitter may be from the complex number A delay is selected among the delays and the selected delay can be sent to the receiver. The transmitter can then determine the Xth and cyclic delay values based on the selected delay. The transmission state may autonomously (e.g., pseudo-randomly) select the cyclic delay values in the second group without having to notify the receiver and may constrain the cyclic delay values to be shorter than the cycle first code length. Round 7 shows the design of the device 7 (8) for transmitting data in a wireless communication system. Apparatus 700 includes means (module 712) for performing a first process of cyclic delay diversity based on a first set of cyclic delay values known to a receiver of data transmission, for use prior to the first processing of cyclic delay diversity or Subsequent base: Pre- ' flat-matrix matrix to perform pre-coded components (module 714) and components (module 716) that perform a second process of cyclic delay diversity based on a second set of cyclic delay values unknown to the receiver.囷8 shows the design of the process for receiving data in a wireless communication system. The process 8 can be performed by a receiver such as a UE, a Node B, or the like. For process 800, the receiver can receive a first set of %-delay values (eg, 〇 to ^ H) known to the receiver and a second set of %-delay values unknown to the receiver (eg, to ?τι The data transmission transmitted in cyclic delay diversity (block 812). The receiver can receive a pilot transmission (block 814) that is transmitted based on the second set of cyclic delay values only by the % delay diversity. The receiver may derive a frame estimate based on the received pilot transmission (block 816). The pilot transmission can be transmitted without a single matrix ν for poor material transmission. In this case, 1290l8.doc -28-200847706 can further derive the ΜΙΜΟ channel estimate based on the unitary matrix V. The ΜΙΜΟ channel estimate may comprise a plurality of ΜΙΜΟ channel matrices of a plurality of subcarriers. The receiver may perform a chirp detection on the received data transmission based on the chirp channel estimate and the first set of cyclic delay values (block 818). In one of the blocks 8 1 8 design, the receiver can determine a plurality of cyclic delay matrices D (moxibustion) of the ridges of the ridges based on the first set of cyclic delay values. The receiver may be based on the plurality of cyclic delay matrices, the plurality of ΜΙΜ〇 channel matrices t (9), and

A precoding matrix w for data transmission derives a plurality of inter-filter matrices M0) of the plurality of subcarriers. The receiver can then perform MIM detection on the received data transmission based on the plurality of spatial filters as a matrix. The recipient can evaluate the performance of the plurality of precoding matrices (eg, total capacity) and can send feedback information about the precoding matrix of the telepresence. The data transmission can be transmitted in precoding based on the selected precoding matrix. The receiver can further perform m_detection on the received (four) transmission based on the selected precoding material. The receiver can also evaluate a plurality of delays (e.g., zero delay, small delay, large delay) and can send feedback information indicating the selected delay. The first set of cyclic delay values can be determined based on the selected delay. The receiver may also jointly evaluate the plurality of precoding matrices and the plurality of delays. The design of the device 9 (8) that is not used to receive data in a wireless communication system includes 900 for receiving a second set of cyclic delay values based on a first set of cyclic L delays known by the receiver and beta receiving $ unknowns. The cyclic delay is divided into four (s) sent components (module 912), means for receiving pilot transmissions based only on the second set of % delay values, and (four) delay diversity transmissions, and 914) Estimating the component (module 916) based on the received pilot transmission to derive the channel 129018.doc -29-200847706 and for receiving the based on the mim〇 channel estimate and the first and subsequent % delay values The data is transmitted to execute the MIM detection component (module 91 8). The modules of Figures 7 and 9 may comprise a processor, an electronic device, a hardware device, an electronic component, a logic circuit, a memory, etc., or any combination thereof. In most of the above descriptions, c (the cyclic delay diversity processing of the magic is implicit, and C (the magic is unknown to the UE. In another design, the cyclic delay diversity is performed by c (〇) The processing is unambiguous, and c(a) is known to the UE for a (eg, signaling to the UE). The data symbols can be handled in the same way in C, regardless of whether the illusion is implicit or explicit. When C(A〇 is the expression, it can be used to process the pilot symbols (as described above), and when C (the illusion is clear, the pilot symbols may or may not be processed by it. The person skilled in the art should understand that Information and signals may be represented using any of a variety of different techniques and techniques. For example, data, pointers, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be Voltage, current, electromagnetic wave, magnetic field or magnetic particle, light field or light particle, or any combination thereof. Those skilled in the art will further appreciate the various illustrative logic blocks, modes described in connection with the disclosure herein. Group, circuit, and algorithm steps can be implemented For electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps are generally described above in terms of functionality. Whether this functionality is implemented as hardware or as software depends on the specific application and design constraints imposed on the overall system. Those skilled in the art can implement this in different ways for each special 129018.doc -30- 200847706 The described functionality is to be construed as a departure from the scope of the disclosure, and various illustrative logic modules and circuits not described in connection with the disclosure herein may be implemented or executed by the following. : General purpose processor, number designed to function as described in the text: (ah, special application integrated circuit (ASIC), field = or other programmable logic device, discrete gate or electric = column discrete hardware A component or any combination thereof. A general purpose processor may be a microprocessor, but in the second generation, the processor may be any conventional processor, controller, micromanager or state machine. The processor may also be implemented A combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, a combination of a core or a plurality of microprocessors, or any other such configuration. The described method or algorithm steps can be directly implemented in a hardware, a software module executed by a processor, or a combination of the two. The software module can be resident in RAM memory, flash memory, ROM memory. Body, EPROM memory, EEpR 〇M memory, scratchpad, disc-removable disc, CD-ROM or any other form of storage medium known in the art. An exemplary storage medium is coupled To the processor, the processor can read information from and write information to the storage medium. Alternatively, the storage medium can be an integral part of the processor. The processor and the storage medium can reside in an ASIC. The ASIC can reside in a user terminal. Alternatively, the processor and the storage medium can reside in a user terminal as discrete components. In one or more exemplary designs, the functions described may be hardware, soft 129018.doc -31 200847706 body, firmware, or any combination thereof, each function may be one or more instructions:: Implemented in software, the body or as one or more instructions or programs: and stored in a computer readable medium. The computer readable medium includes a second computer: a computer readable medium uploading facilitating the transfer of the computer to the media and communication media, including the transfer from the remote location to the storage medium, which may be any medium that can be used by the general purpose. Storage ~ Tian general secondary computer access example description and not limited, Bu Yi + J media. The 4 computer readable medium can include RAM, ROM, EEPR (10), CD_R 〇 M or other optical discs: other magnetic storage devices or components of the desired code that can be used to carry or _ = = and can be used by a general purpose or special purpose computer or Any other media accessed. Also, any connection is properly made as a computer readable medium. For example, if you make a cable, a twisted pair, or a digital subscriber line, you can see, light, or wireless technology such as infrared, helmet, or wave from a website, a feeder, or other remote source: transmission software. 'The coaxial cable, fiber optic I-line, twisted-pair cable, DSL or wireless technologies such as infrared, radio and microwave are included in the definition of the media. As used herein, the disk and the disc include compact discs (CD). , laser discs, optical discs, digital versatile discs (DVD), floppy discs and Blu-ray discs, in which the discs are usually magnetically regenerated, and the discs are optically regenerated with a laser. The combination of the above It is also intended to be included within the scope of the computer-readable medium. The prior description of the present disclosure is provided to enable those skilled in the art to make or use the present disclosure. Those skilled in the art will readily appreciate the various aspects of the disclosure. Modifications, and the general principles defined herein may be applied to other variants without departing from the spirit or scope of the disclosure. 129018.doc • 32-200847706. Therefore, the present disclosure is not intended to be limited to Drawing The examples and designs are most broadly consistent with the scope of the principles and novel features disclosed herein. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows a wireless multiple access communication system. Figure 2 shows a block diagram of Node B and UE. Figures 3A and 3B show two designs of a transmit (TX) MIMO processor. Figure 4 shows the cyclic delay in the time domain. Figure 5 shows the design of a receive (RX) MIMO processor. Figure 6 shows the data used to transmit data. Figure 7. shows a device for transmitting data. Figure 8 shows a process for receiving data. Figure 9 shows a device for receiving data. [Main Symbol Description] 100 Wireless Multiple Access Communication System 110 Node B 120 Use Device 212 Data Source 220 TX Data Processor 230 ΤΧ ΜΙΜΟ Processor 230a ΜΙΜΟ ΜΙΜΟ Processor 230b ΤΧ ΜΙΜΟ Processor 232a-232t Modulator/Demodulation Transducer 234a-234t Antenna 129018.doc -33- 200847706 236 RX ΜΙΜΟ Processor 238 RX Data Processor 240 Controller/Processor 242 Memory 244 Scheduler 252a-252r Antenna 254a-254r Modulator/Demodulation Transducer 260 RX 270 RX data processor 272 data collector 278 data source 280 data processor 282 ΜΙΜΟ processor 290 controller / processor 292 memory 294 channel estimator / channel processor 320a-320s stream processor 332 layer mapping 334 explicit cyclic delay processor 336 precoder 338 implicit cyclic delay processor 342 mapper 344 precoder 346 explicit cyclic delay processor 129018.doc -34- 200847706 348 implicit cyclic delay processor 510 computing unit 512 Detector 514 layer demapper 520a-520s stream processor 700 device 712 for transmitting data in a wireless communication system module 714 module 716 module 900 device 912 for receiving data in a wireless communication system module 914 Group 916 Module 918 Module 129018.doc -35-

Claims (1)

200847706 X. Patent Application Range: 1. A device for wireless communication, comprising: at least one processor configured to: receive a first set of cyclic delay values known to a person based on a data transmission Performing a first process of cyclic delay diversity; and performing a second process of cyclic delay diversity based on a second set of cyclic delay values unknown to the receiver; and a memory coupled to the at least one processor. 2. The device of claim 1, wherein the at least one processor is configured to: perform the first processing and the second processing of cyclic delay diversity on the batten; and perform only the cyclic delay diversity on the pilot Second processing. 3. The device of claim 1, wherein the at least one processor is configured to: perform the first processing of cyclic delay diversity in a frequency domain; and perform the cyclic delay diversity in a frequency domain or a time domain Second processing. 4. The device of the requester, wherein the first set of cyclic delay values corresponds to a cyclic delay longer than the length of the first code of the cycle, and wherein the second set of cyclic delays and late values correspond to a cycle shorter than the first code length of the cycle delay. 5. The device of the requester, wherein the at least one processor is configured to: receive feedback information from the plurality of delays from the connection (4); and = or determine the delay indicated by the feedback information The first-group loop is extended by 6. For example, the device of item 5 is in which the feedback information indicates that there is no delay or a small delay of the length of the first code of the shield ring or a length greater than the length of the first code of the cycle. The at least-processor is configured to select a delay _ A from the plurality of delays of 129018.doc 200847706, send the selected delay to the receiving 〇, ^ 5 1 % # 匈定 the first set of cyclic delay values . 8. The device of claim 1, wherein at least one processor of s σ k, k is configured to select the second group of white ρ π π A without notifying the receiver These are the delay values. 9. The device of claim 1 has an inverse delay value from the receiver. /, the at least one processor is configured to determine the cycles in the second group based on the feeds 10. 11. The first pre-coding of the device ring delay diversity as in claim 1 prior to the first processing of the device ring delay diversity of claim 1. The at least one processor is configured to perform precoding after the processing and after the first precoding matrix of the cyclic delay diversity. Where the at least one processor is configured to perform based on a precoding matrix prior to processing The delta of U term 2 is further prepared, wherein the at least one processor is configured to process the pilot with a unitary matrix not applied to the data. 13. A method for wireless communication, comprising: performing a first process of cyclic delay diversity based on a first set of cyclic delay values known to a receiver of a lean carrier; and based on a delta receiver A second set of cyclic delay values is unknown to perform a second process of cyclic delay diversity. 14. The method of claim 13, further comprising: performing the first processing and the second processing of cyclic delay diversity on the batten; and 129018.doc 200847706 performing only the second processing of the cyclic delay diversity on the pilot. 15. The method of: =: 13, wherein the first -= performing the cyclic delay diversity, the first execution of the cyclic delay diversity in the frequency domain, wherein the execution of the cyclic delay diversity is performed in the second processing packet domain This second processing of delay diversity. </ RTI> 16. The method of claim 13, further comprising: receiving, from the receiver, a plurality of delays indicating that the plurality of delays, and the feedback is based on the delayed delay value of the sneak peek #. The method of claim 13, wherein the method of claim 13 further comprises: autonomously selecting the «Hui cycle delay value in the second group without delaying the receipt of the crying, the completion of the w. 18. The method of claim 13, further comprising: based on a code at the first of the cyclic delay diversity, after eight or after the second processing of the cyclic delay knife set. Pre-, flat-horse matrix to perform pre-programming 19. A device for wireless communication, comprising: - for performing cycle-delay diversity based on a first delay value known by one of a data transmission receiver - The processed component; and a component for performing a second processing of the set of delays based on each delay value based on a number of the first unknowns of the receiver. 2. The device of claim 19, further comprising: means for performing a cyclic delay on the data, and processing the second 129018.doc 200847706; and means for performing only cyclic delay diversity on the pilot The apparatus of the second processing component 19 wherein the means for performing cyclic delay diversity includes means for performing cyclic delay division in the frequency domain, and wherein the means for performing cyclic delay The component of the second=where: contains components for performing cyclic delay diversity in the time domain. 22. The device of claim 19, further comprising: a means for receiving information from the "number of lines (4) late); and for determining the delay based on the feedback information The first set of components of the cyclic delay value. 23. The device of claim 19, further comprising: ; a component that autonomously selects the cyclic delay values of the two if the recipient is not notified. The apparatus of claim 19, further comprising: / performing precoding based on the precoding matrix before or after the first processing of the cyclic delay diversity and prior to the second processing of the % delay diversity member. Kind of machine can be buckled. "Bei media" includes instructions that, when executed by a machine, cause the machine to perform operations including: performing a first set of cyclic delay values based on a first set of cyclic delay values known to one of the poor delivery transmissions Processing; and 129018.doc 200847706 Performing a second process of cyclic delay diversity based on a second set of cyclic delay values unknown to the receiver. 26. The machine readable medium of claim 25, which, when executed by the machine, causes the machine to perform operations further comprising: performing the first process and the second process of cyclic delay diversity on the data; The pilot only performs this second processing of cyclic delay diversity. 27. The machine readable medium of claim 25, which, when executed by the machine, causes the machine to perform operations further comprising: • performing the first processing of cyclic delay diversity in the frequency domain, and This second processing of cyclic delay diversity is performed. 28. An apparatus for wireless communication, comprising: at least one processor configured to perform a first of cyclic delay diversity based on a first set of cyclic delay values known to one of a data transmission receiver Processing and performing a second process of cyclic delay diversity based on a second set of cyclic delay values known to the receiver; and a memory coupled to the at least one processor. 29. The device of claim 28, wherein the at least one processor is configured to perform the first processing and the second processing of cyclic delay diversity on the data, and omitting the first processing of the cyclic delay diversity for the pilot and This second process. 3. A device for wireless communication, comprising: at least one processor configured to: receive a set of cyclic delay values based on a receiver known and a second set of cycles unknown to the receiver The delay value transmits one of the data transmissions in cyclic delay diversity; the reception transmits only one pilot transmission in cyclic delay diversity based on the second set of cyclic delay values based on 129018.doc 200847706; derives a multiple based on the received pilot transmission Inputting a multiple output (ΜΙΜΟ) channel estimate; and performing MIM detection on the received data transmission based on the MIM〇 channel estimate and the first set of cyclic delay values; and a D memory layer that is connected to the at least A processor. 31. The device of claim 30, wherein the at least one processor is configured to: evaluate a performance of the plurality of precoding matrices; and transmit feedback information indicative of a precoding matrix selected from the plurality of precoding matrices; The detection of the received data transmission is further performed based on the selected precoding matrix, and wherein the data transmission is transmitted by precoding based on the selected precoding matrix. 32. The apparatus of claim 3, wherein the at least one processor is configured to: obtain a plurality of ΜΙΜΟ channel matrices of the plurality of subcarriers of the ΜΙΜ〇 channel estimate based on the received pilot transmission; Determining, by the first set of cyclic delay values, a plurality of cyclic delay matrices of the plurality of subcarriers; and deriving a plurality of spatial filter matrices of the plurality of chirp carriers based on the plurality of cyclic delay matrices and the plurality of Μιμ〇 channel matrices And performing M1M detection on the received data transmission based on the plurality of spatial filtering as a matrix. 33. The apparatus of claim 32, wherein the at least one processor is configured to further derive the plurality of spatial filter matrices based on a precoding matrix for the data transmission. 34. The device of claim 3, wherein the at least one processor is configured to evaluate a plurality of delays and send a feedback indicating a delay selected from the plurality of delays 129018.doc 200847706, selected Determining a delay and wherein the first set of cyclic delay values are based on the device of claim 35, wherein the set of cyclic delay values corresponds to a loop delay of the first code length of the loop, and wherein the first The two sets of cyclic delay values correspond to a cyclic delay that is shorter than the length of the first code of the cycle. The device of claim 30, wherein the at least one step is based on a pilot transmission but not used to derive the channel estimate. A processor configured to advance a single moment of the data transmission 37. 38. A method for wireless communication, comprising: receiving a set of cyclic delay values based on a receiver known to be a set of MS And the reception is unknown - the second set of cyclic delay values transmits a data transmission in cyclic delay diversity; the reception transmits only one pilot transmission based on the far second set of cyclic delay values in cyclic delay diversity; The pilot transmission derives a multiple input multiple output (ΜΙΜΟ) channel estimate; and performs detection of the received poor transmission based on the far channel estimate and the first set of cyclic delay values. The method of claim 37, wherein the performing ΜΙΜΟ detection comprises: determining a plurality of uncovering delay matrices of the plurality of subcarriers based on the first set of cyclic delay values, based on the plurality of cyclic delay matrices and the ΜΙΜΟ channel estimation A plurality of ΜΙΜΟ frequency-forcing matrices are used to derive a plurality of spatial filter matrices of the plurality of subcarriers, and ° 129 018 018 47 47 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 129 The method of claim 39, wherein the derivative comprises a gannon- eve 1U inter-chopper chopper matrix bauxite; a precoding matrix for the data transmission to the plurality of spatial filter matrices. The method of claim 37, further comprising: evaluating the performance of the plurality of precoding matrices; and issuing a pre-received information selected from the plurality of precoding matrices, wherein the data transmission system Based on the selected pre-array: the array is transmitted by precoding, and wherein the received resource detection system is further performed based on the pre-coding matrix of the rounds. 41. The method of 37, further comprising: evaluating a performance of the plurality of delays; and transmitting an indication - feedback information selected from the delays in the plurality of delays, and wherein the first set of cyclic delay values are determined based on the selected delay. 42. An apparatus for wireless communication, comprising: receiving one of a first set of cyclic delay values known based on a receiver and the received unknown second set of cyclic delay values to transmit one of cyclic delay diversity a means for transmitting, for receiving a pilot transmission transmitted by cyclic delay diversity based only on the ith set of cyclic delay values; for deriving a multiple input multiple output based on the received pilot transmission (ΜΙΜΟ) a component of channel estimation; and 129018.doc -8 - 200847706 means for performing ΜΙΜΟ detection on the received data transmission based on the ΜΙΜΟ channel estimate and the first set of cyclic delay values. 43. The device, wherein the means for performing ΜΙΜ〇 detection comprises: determining, by the first set of cyclic delay values, a plurality of subcarriers Delay means matrix for estimating, based on the plurality of cyclic delay matrices and the channel ΜΙΜ0 a plurality of frame channels to derive components of the plurality of spatial filter matrices of the plurality of subcarriers, and - means for performing flaw detection on the received resource transmission based on the plurality of spatial filter matrices . The device of claim 43, wherein the means for deriving the plurality of spatial chopping matrix comprises means for further deriving the plurality of spatial filter matrices based on a precoding matrix for the data transmission . 45. The apparatus of claim 42, further comprising: means for evaluating the performance of the plurality of precoding matrices, and for transmitting feedback indicative of a precoding matrix selected from the plurality of precoding matrices And a component, wherein the data transmission is transmitted based on the selected precoding, and wherein the fine detection of the received data is performed based on the selected pre-program. 46. The apparatus of claim 42 for evaluating a plurality of instructions for transmitting, further comprising: a component of L-latency; and a component selected from the delay of the plurality of delays 129018.doc 200847706 And wherein the first set of cyclic delay values is determined based on the selected delay. 129018.doc -10-