KR20090107087A - Apparatus and method for mimo transmission with explicit and implicit cyclic delays - Google Patents

Abstract

Techniques for transmitting data using a combination of explicit cyclic delay and implicit cyclic delay are described. A transmitter may perform first processing for cyclic delay diversity (or explicit cyclic delay processing) based on a first set of cyclic delay values known to a receiver. The transmitter may perform precoding based on a precoding matrix either before or after the explicit cyclic delay processing. The transmitter may perform second processing for cyclic delay diversity (or implicit cyclic delay processing) based on a second set of cyclic delay values unknown to the receiver. The transmitter may perform both explicit and implicit cyclic delay processing for data and may perform only implicit cyclic delay processing for pilot. One entity may select the first set of cyclic delay values and inform the other entity. The transmitter may autonomously select the second set of cyclic delay values without informing the receiver.

Description

APPARATUS AND METHOD FOR MIMO TRANSMISSION WITH EXPLICIT AND IMPLICIT CYCLIC DELAYS

The present invention claims priority to US Provisional Application No. 60 / 888,494, filed February 6, 2007, entitled "EFFICIENT CYCLIC DELAY DIVERSITY BASED PRECODING," which application is assigned to the applicant, which application is incorporated herein by reference. It is incorporated by.

TECHNICAL FIELD The present invention relates generally to communication and, more particularly, to techniques for transmitting data in a wireless communication system.

Wireless communication systems are widely used to provide various communication contents such as voice, video, packet data, messaging, broadcast, and the like. Such wireless systems may be multiple-access systems capable of supporting multiple users by sharing the available system resources. Examples of such multiple-access systems include code division multiple access (CDMA) systems, time division multiple access (TDMA) systems, frequency division multiple access (FDMA) Systems, Orthogonal FDMA (OFDMA) systems, and Single-Carrier FDMA (SC-FDMA) systems.

The wireless communication system can support multiple-input multiple-output (MIMO) transmission. For MIMO, the transmitter may use multiple (T) transmit antennas for data transmission to a receiver having multiple (R) receive antennas. The multiple transmit and receive antennas form a MIMO channel that can be used to increase throughput and / or improve reliability. For example, the transmitter may simultaneously transmit up to T data streams from the T transmit antennas to improve throughput. Alternatively, the transmitter may transmit one data stream from all T transmit antennas to improve reliability. In any case, it is desirable to send MIMO transmissions as a way to achieve good performance.

Techniques for transmitting data using a combination of explicit and implicit circular delays are described herein. By applying a phase ramp across the subcarriers in the frequency domain, or by cyclically shifting the samples in the time domain, a cyclic delay can be generated. For explicit cyclic delay, different phase ramps can be applied across the subcarriers for each antenna, and phase ramps for all antennas are known to the receiver. In order to reveal the explicit cyclic delay, the receiver may perform complementary processing. For implicit cyclic delay, different phase ramps can be applied across the subcarriers for each antenna and the phase ramps for the antennas are unknown to the receiver. The transmitter can transmit the pilot using the same implicit cyclic delay. Based on the channel estimate derived from the pilot, the receiver can reveal the implicit cyclic delay.

In one design, the transmitter may perform first processing (or explicit cyclic delay processing) for cyclic delay diversity based on a first set of cyclic delay values known to the receiver. The transmitter may perform precoding based on a precoding matrix before or after the explicit cyclic delay processing. The transmitter may perform a second processing (or implicit cyclic delay processing) for cyclic delay diversity based on a second set of cyclic delay values unknown to the receiver. The transmitter can perform both explicit and implicit cyclic delay processing on the data, and can only perform implicit cyclic delay processing on the pilot. One entity (eg, a transmitter or receiver) may select one delay from among multiple delays (which may include no delay, small delay, and large delay), and select the selected delay from another entity (eg, receiver). Or transmitter). The first set of cyclic delay values may be determined based on the selected delay. The transmitter may autonomously select (eg, pseudo-random) the second set of cyclic delay values without notifying the receiver.

1 illustrates a wireless multiple-access communication system.

2 shows a block diagram of a Node B and a UE.

3A and 3B show two designs of a transmit (TX) MIMO processor.

4 shows a cyclic delay in the time domain.

5 shows a design of a receive (RX) MIMO processor.

6 shows a process for transmitting data.

7 shows an apparatus for transmitting data.

8 shows a process for receiving data.

9 shows an apparatus for receiving data.

The techniques described herein may be used for various wireless communication systems such as CDMA, TDMA, FDMA, OFDMA, SC-FDMA, and other systems. The terms "system" and "network" are often used interchangeably. CDMA systems may implement radio technologies such as Universal Terrestrial Radio Access (UTRA), cdma2000, and the like. UTRA includes Wideband-CDMA (W-CDMA) and other CDMA variants. cdma2000 covers IS-2000, IS-95 and IS-856 standards. The TDMA system may implement a radio technology such as Global System for Mobile Communications (GSM). The OFDMA system can implement radio technologies such as E-UTRA (Enhanced UTRA), Ultra Mobile Broadcast (UMB), IEEE 802.11 (Wi-Fi), IEEE 802.16 (WiMAX), IEEE 802.20, Flash-OFDM ^®, and the like. Can be. UTRA and E-UTRA are part of the Universal Mobile Telecommunication System (UMTS). 3GPP Long Term Evolution (LTE) is an upcoming release of UMTS that uses E-UTRA. UTRA, E-UTRA, UMTS, LTE and GSM are described in documents from an organization called "3rd Generation Partnership Project (3GPP)." cdma2000 and UMB are described in documents from an organization referred to as “3rd Generation Partnership Project 2 (3GPP2). These various wireless technologies and standards are well known in the art.

1 illustrates a wireless multiple-access communication system 100 having multiple Node Bs 110 and multiple user equipments (UEs). Node B may be a fixed station communicating with the UEs, and may also be referred to as an evolved Node B (eNode B), a base station, an access point, or the like. Each Node B 110 may provide communication coverage for a particular geographic area. UEs 120 may be distributed throughout the system, and each UE may be stationary or mobile. The UE may also be referred to as a mobile station, terminal, access terminal, subscriber unit, station, or the like. The UE may be a cellular phone, a personal digital assistant (PDA), a wireless modem, a wireless communication device, a small device, a laptop computer, a wireless telephone, or the like. The UE may communicate with the Node B via transmissions on the downlink and uplink. The downlink (or forward link) refers to the communication link from the Node Bs to the UEs, and the uplink (or reverse link) refers to the communication link from the UEs to the Node Bs.

FIG. 2 shows a block diagram of the design of Node B 110 and UE 120, which are each one of Node Bs and UEs in FIG. 1. Node B 110 has multiple (T) antennas 234a through 234t. UE 120 is equipped with multiple (R) antennas 252a through 252r. Antennas 234 and 252 may be considered physical antennas.

At Node B 110, TX data processor 220 may receive data from data source 212 and process (eg, encode and symbol map) the data based on one or more modulation and coding schemes. And may provide data symbols. As used herein, a data symbol is a symbol for data, a pilot symbol is a symbol for pilot, and the symbol can be a real or complex value. The data and pilot symbols may be modulation symbols from a modulation scheme such as PSK or QAM. Pilot is data a priori known by both Node B and UE. TX MIMO processor 230 may process the data and pilot symbols as described below, and may provide T output symbol streams to T modulators (MODs) 232a through 232t. To obtain an output sample stream, each modulator 232 may process the output sample stream (eg, for OFDM). Each modulator 232 may further condition (eg, analog convert, filter, amplify, and upconvert) the output sample stream to generate a downlink signal. T downlink signals from modulators 232a through 232t may be transmitted via each of antennas 234a through 234t.

At the UE 120, the R antennas 252a through 252r may receive T downlink signals from the Node B 110, with each antenna 252 associating the received signal with an associated demodulator (DEMOD) 254. ) Can be provided. Each demodulator 254 may condition (eg, filter, amplify, downconvert, and digitize) the received signal and further process the samples (eg, for OFDM) to obtain received symbols. . Each demodulator 254 may provide the received data symbols to the RX MIMO processor 260 and may provide the received pilot symbols to the channel processor 294. Channel processor 294 may estimate the response of the MIMO channel from Node B 110 to UE 120 based on the received pilot symbols and provide MIMO channel estimation to RX MIMO processor 260. can do. An RX MIMO processor 260 may perform MIMO detection on the received data symbols based on the MIMO channel estimate and may provide detected symbols that are estimates of the transmitted data symbols. The RX data processor 270 can process (eg, symbol demap and decode) the detected symbols and provide the decoded data to the data sink 272.

UE 120 may evaluate channel conditions and generate feedback information including various types of information, as described below. The feedback information and data from data source 278 may be processed (eg, encoded and symbol mapped) by TX data processor 280, may be spatially processed by TX MIMO processor 282, It may be further processed by modulators 254a through 254r to generate R uplink signals, which may be transmitted via antennas 252a through 252r. At Node B 110, the R uplink signals from UE 120 may be received by antennas 234a through 234t, processed by demodulators 232a through 232t, and RX MIMO May be spatially processed by processor 236 and further processed (eg, symbol demapping and decoding) by RX data processor 238 to recover the feedback information and data sent by UE 120. Can be. The controller / processor 240 may control data transmission to the UE 120 based on the feedback information.

Controllers / processors 240 and 290 may direct the operation at Node B 110 and UE 120, respectively. The memories 242 and 292 may store data and program codes for each of the Node B 110 and the UE 120. Scheduler 244 may schedule UE 120 and / or other UEs for data transmission on the downlink and / or uplink based on the feedback information received from all UEs.

The techniques described herein may be used for MIMO transmission on the downlink as well as the uplink. For clarity, certain embodiments of the techniques are described below for MIMO transmission on the downlink in LTE. LTE uses orthogonal frequency division multiplexing (OFDM) on the downlink and single-carrier frequency division multiplexing (SC-FDM) on the uplink. OFDM and SC-FDM divide the system bandwidth into multiple (K) orthogonal subcarriers, which are generally referred to as tones, bins, and the like. Each subcarrier can be modulated with data. In general, modulation symbols are sent in the frequency domain using OFDM and in the time domain using SC-FDM.

The Node B 110 may transmit L data symbols simultaneously over L layers on each subcarrier in each symbol period, where L ≧ 1 in general. The layer may correspond to one spatial dimension for each subcarrier used for transmission. The Node B 110 may transmit data using various transmission schemes.

In one embodiment, the MIMO transmission may be sent using a combination of an explicit cyclic delay and an implicit cyclic delay. The MIMO transmission may be further transmitted using precoding. The explicit cyclic delay, the implicit cyclic delay, and the precoding can be performed in a variety of ways.

In one design, Node B 110 may process the data symbols for each subcarrier k as follows:

Here, d (k) is an L × 1 vector including L data symbols transmitted through L layers on subcarrier k in one symbol period,

U is the L × L layer-to-virtual antenna mapping matrix,

D (k) is the L × L explicit cyclic delay matrix for subcarrier k,

W is a T × L precoding matrix,

C (k) is the T × T implicit cyclic delay matrix for subcarrier k, and

y _d (k) is a T × 1 vector containing T output symbols for data for T transmit antennas on subcarrier k in one symbol period.

Node B 110 may process the pilot symbols for each subcarrier k as follows.

Where p (k) is a T × 1 vector containing T pilot symbols transmitted on subcarrier k in one symbol period, and

y _p (k) is a T × 1 vector containing T output symbols for the pilot for the T transmit antennas on subcarrier k in one symbol period.

Equations 1 and 2 are for one subcarrier k. The same processing may be performed for each subcarrier used for transmission. In the description herein, a matrix may have one or multiple columns.

The precoding matrix W may be used to form T virtual antennas using T physical antennas 234a through 234t. Each virtual antenna may be formed in one column of W. The data symbol can be multiplied by one column of W and then transmitted on one virtual antenna and all T physical antennas. W may be based on a Fourier matrix or some other matrix. W may be selected from a set of precoding matrices.

In order to map the data symbols for the L layers to L virtual antennas selected from the T available virtual antennas, a layer to virtual antenna mapping matrix U can be used. Based on the layer to virtual antenna mapping selected for use, U may be defined. U can also be an identity matrix I with 1 on the diagonal and 0 on the rest. The same or different mapping matrices may be used for the K subcarriers.

The explicit cyclic delay matrix D (k) may be used to obtain cyclic delay diversity, wherein the cyclic delay diversity is beamforming gain, frequency selective scheduling gain. scheduling gain) and / or diversity gain. Also, D (k) can be used to obtain layer permutation, which layer substitution can have certain advantages. D (k) may be generated based on a delay selected from the set of delays, which delay may include a delay that is greater than the cyclic prefix length.

In addition, the implicit cyclic delay matrix C (k) may be used to obtain cyclic delay diversity. C (k) can be generated in various ways and can be limited to smaller than the cyclic prefix length.

In the design shown in Equation 1, precoding with W is performed after explicit cyclic delay processing with D (k). Thus, to the virtual antennas formed by the precoding matrix W (instead of physical antennas), the explicit cyclic delay is applied. This design can be used for large delays.

FIG. 3A shows a block diagram of a TX MIMO processor 230a implementing Equations 1 and 2, wherein the TX MIMO processor 230a is one of the TX MIMO processors 230 at Node B 110 of FIG. It is a design. Within TX data processor 220, S stream processors 320a-320s may receive S data streams from data source 212, where S ≧ 1 is generally. Each stream processor 320 may encode, interleave, scrambling, and symbol map the data streams to obtain data symbols. Each data stream may carry one transport block or packet at each transmission time interval (TTI). Each stream processor 320 may process the transport block to obtain a codeword and map the codeword to a block of modulation symbols. The terms "data stream", "delivery block", "packet" and "codeword" may be used interchangeably. Stream processors 320a through 320s may provide S symbol streams.

Within TX MIMO processor 230a, layer mapper 332 may map data symbols for the S data streams to the L virtual antennas selected for use. In one design, mapper 332 may map the data symbols for the S data streams to L layers, and then use the data symbols for the L layers for transmission. Map to subcarriers and virtual antennas. An explicit cyclic delay processor 334 may multiply the mapped symbols for each subcarrier with the explicit cyclic delay matrix D (k). Precoder 336 may multiply the symbols from processor 334 for each subcarrier with the precoding matrix W and provide precoded symbols for that subcarrier. An implicit cyclic delay processor 338 may receive the precoded symbols from a precoder 335 and pilot symbols, and implicit the cyclic delay delay matrix for the symbols for each subcarrier to obtain output symbols. Can be multiplied by C (k). The processor 338 may provide the T output symbol streams to the T modulators 232a through 232t.

Each modulator 232 may perform OFDM modulation on each output symbol stream. In each modulator 232, the K output symbols to be transmitted on the K total subcarriers in one OFDM symbol interval are K-points in order to obtain a useful portion comprising K time-domain samples. It can be transformed using an inverse discrete Fourier transform (IDFT). Each time-domain sample is a complex value transmitted in one sample interval. To form an OFDM symbol containing K + C samples, the last C samples of the useful portion may be copied and added to the front of the useful portion. The copied portion is referred to as cyclic prefix and is used to remove inter-symbol interference (ISI) caused by frequency selective fading. To generate the downlink signal, each modulator 232 may further process the sample stream.

The controller / processor 240 can receive feedback information from the UE 120 and generate controls for the stream processors 320 and the layer mapper 332. In addition, controller / processor 240 may provide the explicit cyclic delay matrix D (k) to processor 334, and may provide the precoding matrix W to precoder 336, which implicitly. The cyclic delay matrix C (k) may be provided to the processor 338.

In another design, Node B 110 may process the data symbols for each subcarrier k as follows:

Where D (k) is the T × T explicit cyclic delay matrix for subcarrier k. Node B 110 may process the pilot symbols for each subcarrier k, as shown in equation (2).

In the design shown in equation (3), the explicit cyclic delay processing with D (k) is performed after precoding with W. Thus, the explicit cyclic delay is applied to the physical antennas on behalf of the virtual antennas. This design can be used for no delays and small delays.

FIG. 3B shows a block diagram of a TX MIMO processor 230b implementing Equations 2 and 3, wherein the TX MIMO processor 230b is a block diagram of the TX MIMO processor 230 at Node B 110 of FIG. Is another design. Within TX MIMO processor 230b, layer mapper 342 may map the data symbols for the S data streams to the L virtual antennas selected for use. Precoder 344 may multiply the mapped symbols for each subcarrier with the precoding matrix W and provide precoded symbols for that subcarrier. An explicit cyclic delay processor 346 may multiply the precoded symbols for each subcarrier by the explicit cyclic delay matrix D (k). The implicit cyclic delay processor 348 may receive symbols from processor 346 and pilot symbols, and the implicit cyclic delay matrix C (k) for the symbols for each subcarrier to obtain output symbols. Can be multiplied by The processor 348 may provide the T output symbol streams to the T modulators 232a through 232t.

In another design, Node B 110 may process the pilot symbols for each subcarrier k as follows:

Where V is a T × T unitary matrix. The unitary matrix V is V ^H V = I and VV ^H = cleared and features of I to the properties, which are orthogonal to each other columns of V are also orthogonal to each other even rows of the V, and each column and each row has unit power (unit power ) Means V may be based on a Fourier matrix or some other type of matrix. The design in Equation 4 may allow a pilot to be transmitted over all T physical antennas. This design may be used for pilot channel (CPICH), synchronization channel (SCH), and / or other channels.

Various types of precoding matrices can be used for the designs shown in equations (1) and (3). In one design, a set of Q precoding matrices may be defined as follows:

, i = 0, ..., Q-1

, i = 0, ..., Q-1

Where F is a Fourier matrix,

∧ _i is the i-th phase shift matrix, and

W _i is the i th precoding matrix.

The elements of the T × T Fourier matrix F can be written as:

, u = 0, ..., T-1 및 v=0, ..., T-1,

, u = 0, ..., T-1 and v = 0, ..., T-1,

Where f _{u and v} are elements in the u th row and the v th column of the Fourier matrix.

In one design, the phase shift matrix ∧ _i can be represented as:

Where λ _{i, v} is the phase for the v-th antenna in the i-th phase shift matrix. Q different phase shift matrices may be defined as different phases λ _{i, v} and / or may be defined by rotating one or more base matrices.

For the design shown in equation (5), can be a Q different T × T s precoding matrix W _i, defined on the basis of the Fourier matrix F and a different phase shift matrices ∧ _i. A set of precoding matrices may also be defined using other Unitary matrices in place of or in addition to the Fourier matrix. In addition, the set of precoding matrices may comprise an identity matrix I , which may be used to transmit each layer on one physical antenna. For selective virtual antenna transmission, different combinations of columns (or submatrices) of the Q precoding matrices can be evaluated and the L columns of the precoding matrix W _i providing the best performance are precoding matrices. It may be provided as W , where generally 1 ≦ L ≦ T.

In one design, a set of explicit cyclic delay matrices may be defined for the set of delays. Each delay may be associated with V phase ramps for the V antennas, where antenna 0 may have a phase ramp of zero. If explicit cyclic delay processing is performed prior to precoding as shown in FIG. 3A, V = L and the V antennas correspond to L selected virtual antennas. If explicit cyclic delay processing is performed after precoding as shown in Fig. 3b, then V = T and the V antennas correspond to T physical antennas. Thus, the dimension of the explicit cyclic delay matrix D (k) may depend on whether the explicit cyclic delay processing is performed before or after the precoding. For clarity, much of the description below assumes that the explicit cyclic delay processing is performed before precoding, as shown in FIG. 3A, and D (k) has a dimension of L × L.

In one design, a set of explicit circular delay matrices can be defined as follows:

,

,

Where _m is the m th delay, which is the delay spacing between successive antennas, and D _m (k) is the explicit cyclic delay matrix for the m th delay.

In the design shown in Equation 8, the cyclic delay values τ _{m, v} and phase ramp θ _{m, v} of each antenna v can be expressed as:

, v = 0, ..., L-1, 및

, v = 0, ..., L-1, and

, v = 0, ..., L-1이다.

, v = 0, ..., L-1.

The designs in (8) use a constant spacing of tau _m for the cyclic delay values of different antennas. Since the cyclic delay values of all L antennas can be defined based on a single τ _m value, the constant delay interval can reduce signal overhead.

In one design, a set of M = 3 delays may be defined to include the following:

, 무 지연에 대하여,

Against delay,

, 작은 지연에 대하여, 그리고

, Against small delays, and

, 큰 지연에 대하여

Against large delay

Small delays may be used to improve beamforming and frequency selective scheduling gains, and may be particularly useful for low mobility channels, low geometry channels, low rank channels, and the like. Large delays can be used to improve the transmit diversity gain, and more in high mobility channels (eg for mobile UEs moving beyond 30 km / hr), high geometry channels, high rank channels, time or frequency. May be suitable for coarse feedback or the like. Large delays can provide performance similar to zero delay in low mobility channels, which can improve the robustness of the system when there is noise in the feedback information. Geometry is related to the signal-to-noise-and-interference ratio (SINR). Low geometry may correspond to low SINRs, and high geometry may correspond to high SINR. The rank refers to the number of virtual antennas selected for use, and is also referred to as spatial multiplexing order. In one design, no delay or small delay may be used for rank-1 transmissions, and large delays may be used for rank-2 or more transmissions. Cyclic delay diversity processing using large delay can equalize the SINRs of the L layers used for data transmission.

In general, explicit cyclic delay matrices may be defined for any number of delays and any particular delay. For example, explicit cyclic delay matrices may be defined for small delays of tau ₁ = 1 or some other delay, large delays below K / L or above K / L. As shown in Equations 8 and 9, the cyclic delay values for different antennas may have a constant interval. In addition, the cyclic delay values for different antennas may have non-uniform spacing. In general, a small delay may be any value less than the cyclic prefix length, and a large delay may be any value greater than the cyclic prefix length.

In one design, the implicit cyclic delay matrix C (k) may be defined as follows:

는 물리적 안테나 t에 대한 암시적 순환 지연 값이다.here,

Is the implicit cyclic delay value for the physical antenna t.

The phase ramp θ _t for each physical antenna t can be expressed as:

, t = 0, ..., T-1

, t = 0, ..., T-1

= 0이다. Where θ ₀ =

= 0.

In general, any set of implicit cyclic delay values can be used for the T physical antennas. The implicit cyclic delay values may be pseudo-random values, or may be values selected to achieve good performance. The implicit cyclic delay values should be shorter than the cyclic prefix length C as follows:

, t = 0, ..., T-1

, t = 0, ..., T-1

The constraint in equation (16) can ensure that pilot-based channel estimates transmitted with an implicit cyclic delay do not degrade too much due to an aliasing effect.

은, 정수 개의 샘플들에 의해 주어질 수 있다. 이러한 설계에서, 후술할 바와 같이, C(k)를 주파수 영역에 적용함으로써 또는 상기 유용한 부분을 시간 영역에서 순환적으로 시프팅함으로써, 상기 암시적 순환 지연이 달성될 수 있다. 다른 설계에서, 각 물리적 안테나에 대한 상기 암시적 순환 지연 값

은, 비-정수 개의 샘플들에 의해서 주어질 수 있다. In one design, the implicit cyclic delay value for each physical antenna

Can be given by integer samples. In this design, as will be described later, by applying C (k) in the frequency domain or by cyclically shifting the useful portion in the time domain, the implicit cyclic delay can be achieved. In another design, the implicit cyclic delay value for each physical antenna

Can be given by non-integer samples.

는, 상기 베이스 세트로부터 의사-랜덤한 방법으로 선택될 수 있다. 이러한 설계는, T 개의 서로 다른 의사-랜덤하게 선택된 순환 지연 값들이 상기 T 개의 물리적 안테나들에 적용되는 것을 보증할 수 있다. In one design, a base set of T different implicit cyclic delay values may be defined. For example, the base set may include cyclic delay values of 0, 1, 2, ..., T-1. The implicit cyclic delay values for physical antennas 0 to T-1, or for t = 0, ..., T-1

Can be selected in a pseudo-random manner from the base set. This design can ensure that T different pseudo-randomly selected cyclic delay values are applied to the T physical antennas.

In addition, the implicit cyclic delay values for the T physical antennas may be defined and selected in other ways. The implicit cyclic delay values may be static values that do not change over time, quasi-static values that change slowly over time, and frequently, for example, every symbol interval, every slot of a plurality of symbol intervals. , May be dynamic values that may change for each subframe of the plurality of slots.

For the design shown in Equation 1, the processing for data symbols using the large delay shown in Equation 13 can be represented as follows:

Processing for the pilot symbols can be represented as follows:

The implicit cyclic delay matrix C (k) may be applied to the frequency domain as shown in Equation 1, and may be a function of subcarrier k. C (k) provides a phase ramp (eg, linear phase shift) across the K subcarriers on each physical antenna. The slope of the phase ramp may be different for different antennas, and antenna 0 may have a phase ramp of zero. Applying the phase ramp to the frequency domain is equivalent to performing a cyclic shift of the useful part of the OFDM symbol in the time domain.

가 정수 개의 샘플들에 의해 주어진다. 안테나 0에 대한 OFDM 심볼의 상기 유용한 부분은 0 샘플들만큼 순환적으로 시프트될 수 있고, 안테나 1에 대한 OFDM 심볼의 상기 유용한 부분은

샘플들만큼 순환적으로 시프트될 수 있으며, 안테나 2에 대한 OFDM 심볼의 상기 유용한 부분은

샘플들만큼 순환적으로 시프트될 수 있고, 안테나 3에 대한 OFDM 심볼의 상기 유용한 부분은

샘플들만큼 순환적으로 시프트될 수 있다.

,

및

은 의사-랜덤 값들일 수 있고, 몇몇 방법들로 관련될 수 있다. 4 shows an example of applying an implicit cyclic delay to the time domain. In this example, T = 4, for each physical antenna

Is given by integer samples. The useful portion of the OFDM symbol for antenna 0 may be cyclically shifted by 0 samples, and the useful portion of the OFDM symbol for antenna 1 may be

Can be cyclically shifted by samples, the useful portion of the OFDM symbol for antenna 2 being

Can be cyclically shifted by samples, and the useful portion of the OFDM symbol for antenna 3 is

Can be cyclically shifted by samples.

,

And

May be pseudo-random values and may be related in several ways.

The cyclic delay matrices D (k) and C (to support various delays, including no delay, small delay, large delay, and constant and non-constant spacing between cyclic delay values for different antennas, k) can be used. In addition, these matrices can reduce evaluation complexity (for selecting delay among all possible delays) and signal overhead (for notification of the selected delay). The delay can be selected in various ways.

In one design, the Node B may select an explicit delay for each UE and send the selected delay to the UE. In another design, the Node B may select an explicit delay for all UEs served by the Node B and may broadcast or transmit the selected delay to these UEs. In another design, in order to reduce the UE computational complexity as well as feedback overhead, the Node B may limit the set of delays for each rank differently from each other. For example, only no delay may be allowed for rank 1, and both no delay and large delay may be allowed for rank 2 and the like.

In one design, the UE may evaluate different possible precoding matrices and different possible delays based on performance metrics, and select the precoding matrix and delay using the best performance indicator. For each possible combination of precoding matrix W _i and delay τ _m , the UE is based on the MIMO channel estimate H (k), precoding matrix W _i , and explicit cyclic delay matrix D _m (k). The effective MIMO channel estimate H _eff (k) can be calculated. The UE may evaluate different hypotheses, each of which may be different for different combinations of virtual antennas that may be used for data transmission (eg, different column subsets of H _eff (k)). Corresponds to other precoding submatrices W _{i , s} . The UE estimates a set of SINRs for each hypothesis, based on H _eff (k), the MIMO detection technique used by the UE, and a constant variance of the available transmit power across all virtual antennas for the hypothesis. can do. Thereafter, the UE may map each SINR to a capacity based on a capacity function, and all K for all virtual antennas for each home to obtain the total capacity for that home. Capacities of subcarriers can be accommodated. After evaluating all assumptions for all possible combinations of precoding matrix and explicit cyclic delay value, the UE can select the best assumption for the best combination of delay and precoding matrix with the largest sum capacity. The UE may transmit a precoding sub-matrix W _{i , s} and delay for the best hypothesis as a precoding matrix W and delay to use for data transmission. The precoding matrix W may include the L highest columns of W _{i for} the L selected virtual antennas.

In addition, the UE may determine S SINRs of S data streams transmitted on the L selected virtual antennas. The SINR of each data stream may be determined based on the SINRs of the subcarriers and the virtual antennas for that data stream. In addition, the UE may determine S channel quality indicator (CQI) values based on SINRs of the S data streams. The CQI value may include an average SINR, a modulation and coding scheme (MCS), a packet format, a delivery format, and the like. The UE may transmit S CQI values for S data streams or may transmit a base CQI value and a differential CQI value. The base CQI value may represent the SINR of the first decoded data stream, and the differential CQI value may represent the difference between the SINRs of the two data streams.

In one design, Node B can arbitrarily select the implicit cyclic delay value of each physical antenna. The Node B may send pilot symbols and data symbols using the same implicit cyclic delay processing, and the UE may estimate the MIMO channel response based on these pilot symbols. In this example, the MIMO channel estimate will include both the actual MIMO channel response and the implicit cyclic delay matrices applied by Node B. The phase shift caused by the implicit cyclic delay matrices can be understood as part of the MIMO channel variation by the UE, and the UE does not need to know the implicit cyclic delay value of each antenna. By transmitting the pilot using the implicit cyclic delay matrices, the UE can arbitrarily select and change the implicit cyclic delay values, and the change will be apparent to the UE.

By using a small number of explicit delays (eg, no delay, small delay, and large delay) with a constant delay interval between the L virtual antennas, signal overhead between the Node B and the UE and / or at the UE Selection complexity can be reduced. The Node B can select and apply various implicit cyclic delay values without notifying the UE.

5 shows a block diagram of a design of an RX MIMO processor 260 and an RX data processor 270 at the UE 120 of FIG. 2. Received pilot symbols from demodulators 254a through 254r may be represented as follows:

, 또는

, or

,

,

Where H (k) is the R × T MIMO channel matrix for subcarrier k,

r _p (k) is an R × 1 vector containing R received pilot symbols for R receive antennas on subcarrier k in one symbol period. If the pilot symbols are sent as shown in equation (2), equation (19) is applicable. If the pilot symbols are sent as shown in equation (4), equation (20) is applicable.

Channel estimator 294 may derive a MIMO channel estimate based on the received pilot symbols. The MIMO channel estimate can be represented as follows:

, 또는

, or

Here, H _est (k) is a MIMO channel matrix estimate for subcarrier k. For simplicity, Equations 21 and 22 assume no channel estimation error. The MIMO channel estimate may comprise a set of estimated MIMO channel matrices for all subcarriers used for transmission. As shown in equations 21 and 22, the MIMO channel estimate H _est (k) is not only the implicit cyclic delay matrix C (k) and the unitary matrix V (if any) used for the pilot, The actual MIMO channel H (k) is included.

와 같이 상기 파일럿에 대해 이용되는 상기 유니타리 행렬 V를 제거할 수 있다. Within RX MIMO processor 260, calculation unit 410 is configured to calculate the MIMO channel estimate H _set (k) from channel estimator 294 and the precoding matrix W and the explicit cyclic delay matrix D ( k) can be received. When the pilot is transmitted as shown in Equation 4, the processor 260,

The unitary matrix V used for the pilot can be removed as follows.

Unit 410 may calculate the effective MIMO channel estimate as follows:

, 또는

, or

,

,

Where H _eff (k) is the R × L effective MIMO channel matrix for subcarrier k. H _eff (k) is the effective MIMO channel observed by the data symbols and is for the L actual antennas used for data transmission.

If Node B performs precoding and explicit cyclic delay processing as shown in Equation 1, Equation 23 may be used. If the Node B performs precoding and explicit cyclic delay processing as shown in equation (3), equation (24) may be used. Thereafter, unit 410 is based on H _eff (k) and has a minimum mean square error (MMSE), linear MMSE (LMMSE), zero-focing (ZF), or some According to another MIMO detection technique, the spatial filter matrix M (k) for each subcarrier k can be calculated.

MIMO detector 412 may obtain R received data symbol streams from R demodulators 254a through 254r. MIMO detector 412 can perform MIMO detection on the R received data symbol streams using the spatial filter matrix M (k) for each subcarrier k and for L selected virtual antennas. L detected symbol streams may be provided. In a manner complementary to the mapping performed by the layer mapper 332 in FIG. 3A or the mapping performed by the layer mapper 342 in FIG. 3B, the layer demapper 414 stores the L detected symbol streams. It can demap and provide S demapped symbol streams for S data streams.

RX data processor 270 includes S stream processors 420a through 420s for S data streams. Each stream processor 420 may symbol demap, descramble, deinterleave, and decode a demapped symbol stream and provide a decoded data stream.

내지

)의 제2 세트에 기초하여, 순환 지연 다이버시티에 대한 제2 프로세싱(또는 암시적 순환 지연 프로세싱)을 수행할 수 있다(블록 616). 6 shows a design of a process 600 for transmitting data in a wireless communication system. Process 600 may be performed by a transmitter such as a Node B, UE, or the like. For process 600, the transmitter is further configured to determine the cyclic delay diversity for cyclic delay diversity based on a first set of cyclic delay values (e.g. τ _{m, 0} to τ _{m, L-1} ) known to the receiver of the data transmission. One processing (or explicit circular delay processing) may be performed (block 612). Before or after the first processing for cyclic delay diversity, the transmitter may perform precoding based on a precoding matrix W (block 614). The transmitter may generate cyclic delay values that are unknown to the receiver (e.g.,

To

Based on the second set of), second processing (or implicit cyclic delay processing) for cyclic delay diversity may be performed (block 616).

The transmitter may perform the first and second processing for cyclic delay diversity on data as shown, for example, in Equations 1 or 3 above. The transmitter may perform only the second processing for cyclic delay diversity for a pilot, for example as shown in equations (2) or (4). The transmitter may process the pilot using a unitary matrix V that is not applied to the data. For example, by applying the explicit cyclic delay matrix D (k) for each subcarrier k, the transmitter can perform the first processing for cyclic delay diversity in the frequency domain. For example, by cyclically shifting samples of the useful portion as shown in FIG. 4, the transmitter can perform the second processing for cyclic delay diversity in the time domain.

In one design, the transmitter may receive feedback information indicative of one of a plurality of delays, wherein the plurality of information may include a no delay, a small delay, and a large delay shown in Equations 11-13. . The transmitter may determine a first set of cyclic delay values based on the delay represented by the feedback information. In another design, the transmitter can select a delay from a plurality of delays and send the selected delay to the receiver. Thereafter, the transmitter may determine the first set of cyclic delay values based on the selected delay. The transmitter may independently select (eg, pseudo-randomly) the cyclic delay values in the second set without notifying the receiver and limit these cyclic delay values to be shorter than the cyclic prefix length. Can be.

7 shows a design of an apparatus 700 for transmitting data in a wireless communication system. Apparatus 700 includes means for performing a first processing for cyclic delay diversity based on a first set of cyclic delay values known to a receiver of a data transmission (module 712), said second for cyclic delay diversity. Means for performing precoding based on a precoding matrix before or after one processing (module 714), and a second for cyclic delay diversity based on a second set of cyclic delay values unknown to the receiver. Means (module 716) for performing processing.

내지

)의 제2 세트에 기초하여, 순환 지연 다이버시티를 이용하여 전송된 데이터 전송을 수신할 수 있다(블록 812). 상기 수신기는, 순환 지연 값들의 상기 제2 세트에만 기초하여 순환 지연 다이버시티를 이용하여 전송된 파일럿 전송을 수신할 수 있다(블록 814). 상기 수신기는, 상기 수신된 파일럿 전송에 기초하여 MIMO 채널 추정을 도출할 수 있다(블록 816). 상기 파일럿 전송은, 데이터 전송에 이용되지 않는 유니타리 행렬 V를 이용하여 전송될 수 있다. 이 경우에, 상기 MIMO 채널 추정이 상기 유니타리 행렬 V를 더 기초로 하여 유도될 수 있다. 상기 MIMO 채널 추정은, 다수의 서브캐리어들에 대한 다수의 MIMO 채널 행렬들 H _est(k)를 포함할 수 있다. 8 shows a design of a process 800 for receiving data in a wireless communication system. Process 800 may be performed by a receiver such as a UE, a Node B, or the like. For process 800, the receiver comprises a first set of cyclic delay values (eg, τ _{m, 0} to τ _{m, L-1} ) known to the receiver and cyclic delay values (eg, unknown to the receiver).

To

Based on the second set of), the transmitted data transmission may be received using cyclic delay diversity (block 812). The receiver may receive a pilot transmission transmitted using cyclic delay diversity based only on the second set of cyclic delay values (block 814). The receiver may derive a MIMO channel estimate based on the received pilot transmission (block 816). The pilot transmission may be transmitted using a unitary matrix V that is not used for data transmission. In this case, the MIMO channel estimate may be derived based on the unitary matrix V further. The MIMO channel estimate may comprise a plurality of MIMO channel matrices H ( _est ) (k) for a plurality of subcarriers.

The receiver may perform MIMO detection for the received data transmission based on the first set of MIMO channel estimation and cyclic delay values (block 818). In one design of block 818, the receiver may determine a plurality of cyclic delay matrices D (k) for a plurality of subcarriers based on the first set of cyclic delay values. Based on a number of cyclic delay matrices D (k), a number of MIMO channel matrices H _est (k), and a precoding matrix W used for data transmission, the receiver receives a plurality of spatial for a plurality of subcarriers. It is possible to derive the filter matrices M (k). Thereafter, the receiver may perform MIMO detection for the received data transmission based on the plurality of spatial filter matrices.

The receiver may evaluate the performance (eg, total capacity) of the plurality of precoding matrices and send feedback information indicative of the selected precoding matrix. Based on the selected precoding matrix, the data transmission may be transmitted using precoding. The receiver may perform MIMO detection for the received data transmission further based on the selected precoding matrix. In addition, the receiver may evaluate multiple delays (eg, no delay, small delay, and large delay) and may send feedback information indicative of the selected delay. The first set of cyclic delay values may be determined based on the selected delay. In addition, the receiver can jointly evaluate multiple precoding matrices and multiple delays.

9 shows a design of an apparatus 900 for receiving data in a wireless communication system. The apparatus 900 includes means for receiving a data transmission transmitted using cyclic delay diversity based on a first set of cyclic delay values known to the receiver and a second set of cyclic delay values unknown to the receiver. (Module 912), means for receiving a pilot transmission transmitted using cyclic delay diversity based only on the second set of cyclic delay values (module 914), and performing a MIMO channel estimate based on the received pilot transmission Means for deriving (module 916) and means for performing MIMO detection for the received data transmission based on the first set of MIMO channel estimation and cyclic delay values (module 918).

The modules of FIGS. 7 and 9 may include processors, electronic circuit devices, hardware devices, electronic circuits, components, logic circuits, memories, and the like, or any combination thereof.

In much of the above description, processing for cyclic delay diversity using C (k) is implicit, and C (k) is unknown to the UE. In another design, processing for cyclic delay diversity using C (k) is explicit and C (k) is known to the UE (eg, a signal is transmitted). Regardless of whether C (k) is implicit or explicit, data symbols can be processed using C (k) in the same way. The pilot symbols may be pilot symbols are to be processed using the C (k) when jeokil suggests, when jeokil pilot symbols stated can not be processed using the C (k).

Those skilled in the art will appreciate that information and signals may be represented using various different arbitrary techniques and techniques. For example, data, instructions, instructions, information, signals, bits, symbols, and chips that may be referenced through the above description may include voltages, currents, electromagnetic waves, magnetic fields or magnetic particles, It can be represented by optical systems and light particles, or any combination thereof.

Those skilled in the art will appreciate that various exemplary logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or a combination of both. . To clearly describe this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

General purpose processor, digital signal processor (DSP), application specific integrated circuit (ASIC), field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or to perform the functions described herein In addition to any combinations designed to be various, the various logic, logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or implemented. A general purpose processor may be a microprocessor, but in the alternative, the processor may be a general processor, controller, microcontroller, or state machine. Also, a processor may be implemented as a combination of computing devices, such as a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other configuration.

The steps of the method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module performed by a processor, or in a combination of the two. The software module may be in the form of RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable memory, CD-ROM, or any storage means well known to those skilled in the art. Exemplary storage means are connected to the processor, where the processor can read information from and write information to the storage means. In the alternative, the storage means may be integral to the processor. Processors and storage means may be present in the ASIC. The ASIC may be present in the user terminal. In the alternative, the processor and the storage means may reside as discrete components in a user terminal.

In one or more example implementations, the functions presented herein may be implemented through hardware, software, firmware, or a combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes computer storage media and communication media including any medium for facilitating the transfer of a computer program from one place to another. A storage medium may be any available medium that can be accessed by a general purpose computer or a special computer. For example, such computer-readable media can be any program code means required in the form of RAM, ROM, EEPROM, CD-ROM or other optical disk storage media, magnetic disk storage media or other magnetic storage devices, or instructions or data structures. Include, but are not limited to, a general purpose computer, special computer, general purpose processor, or any other medium that can be accessed by a particular processor. In addition, any connecting means may be considered a computer readable medium. For example, if the software is transmitted from a website, server, or other remote source via wireless technologies such as coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or infrared radio, and microwave, such coaxial cable, Wireless technologies such as fiber optic cables, twisted pairs, DSL, or infrared radios, and microwaves may be included within the definition of such media. Disks and discs used herein include compact discs (CDs), laser discs (disc), optical discs, DVDs, floppy disks, and Blu-ray discs. Wherein the disk reproduces the data magnetically, while the disk reproduces the data optically through a laser. Combinations of the above should also be included within the scope of computer-readable media.

The description of the presented embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the scope of the invention. Thus, the present invention should not be limited to the embodiments set forth herein but should be construed in the broadest scope consistent with the principles and novel features set forth herein.

Claims (46)

Perform a first processing for cyclic delay diversity based on a first set of cyclic delay values known to the receiver of the data transmission, and based on a second set of cyclic delay values unknown to the receiver At least one processor configured to perform a second processing on; And A memory coupled to the at least one processor, Device for wireless communication. The method of claim 1, The at least one processor is configured to perform the first processing and the second processing on cyclic delay diversity for data, and to perform only the second processing on cyclic delay diversity on a pilot; Device for wireless communication. The method of claim 1, The at least one processor is configured to perform the first processing for cyclic delay diversity in a frequency domain and to perform the second processing for cyclic delay diversity in a frequency domain or a time domain, Device for wireless communication. The method of claim 1, Wherein the first set of cyclic delay values corresponds to a cyclic delay longer than a cyclic prefix length and the second set of cyclic delay values corresponds to a cyclic delay shorter than the cyclic prefix length Device for wireless communication. The method of claim 1, The at least one processor is configured to receive feedback information indicating one of a plurality of delays from the receiver and to determine the first set of cyclic delay values based on the delay indicated by the feedback information. felled, Device for wireless communication. The method of claim 5, The feedback information indicates no delay, a delay shorter than the cyclic prefix length, or a large delay longer than the cyclic prefix length, Device for wireless communication. The method of claim 1, The at least one processor is configured to select one of a plurality of delays, send the selected delay to the receiver, and determine the first set of cyclic delay values based on the selected delay; Device for wireless communication. The method of claim 1, The at least one processor is configured to autonomously select the cyclic delay values in the second set without notifying the receiver; Device for wireless communication. The method of claim 1, The at least one processor is configured to determine the cyclic delay values in the second set based on feedback information from the receiver, Device for wireless communication. The method of claim 1, The at least one processor is configured to perform precoding based on a precoding matrix after the first processing for cyclic delay diversity and before the second processing for cyclic delay diversity, Device for wireless communication. The method of claim 1, The at least one processor is configured to perform precoding based on a precoding matrix prior to the first processing for cyclic delay diversity, Device for wireless communication. The method of claim 2, The at least one processor is configured to process the pilot using a unitary matrix that is not applied to the data, Device for wireless communication. Performing first processing for cyclic delay diversity based on a first set of cyclic delay values known to a receiver of a data transmission; And Performing second processing for cyclic delay diversity based on a second set of cyclic delay values unknown to the receiver, Method for wireless communication. The method of claim 13, Performing the first processing and the second processing on cyclic delay diversity on data; And Further performing only the second processing for cyclic delay diversity for a pilot; Method for wireless communication. The method of claim 13, Performing the first processing for the cyclic delay diversity includes performing the first processing for cyclic delay diversity in the frequency domain, and performing the second processing for the cyclic delay diversity The step of performing the second processing for cyclic delay diversity in a frequency domain or a time domain, Method for wireless communication. The method of claim 13, Receiving feedback information indicative of one of a plurality of delays from the receiver; And Determining the first set of cyclic delay values based on the delay indicated by the feedback information, Method for wireless communication. The method of claim 13, Autonomously selecting the cyclic delay values in the second set without notifying the receiver; Method for wireless communication. The method of claim 13, Performing precoding based on a precoding matrix before or after the first processing for cyclic delay diversity and before the second processing for cyclic delay diversity, Method for wireless communication. Means for performing first processing for cyclic delay diversity based on a first set of cyclic delay values known to a receiver of a data transmission; And Means for performing second processing for cyclic delay diversity based on a second set of cyclic delay values unknown to the receiver; Device for wireless communication. The method of claim 19, Means for performing the first processing and the second processing on cyclic delay diversity on data; And Means for performing only said second processing on cyclic delay diversity for a pilot, Device for wireless communication. The method of claim 19, Means for performing the first processing for the cyclic delay diversity comprises means for performing the first processing for cyclic delay diversity in a frequency domain, and the second processing for the cyclic delay diversity Means for performing the means comprises means for performing the second processing for cyclic delay diversity in a time domain; Device for wireless communication. The method of claim 19, Means for receiving feedback information indicative of one of a plurality of delays from the receiver; And Means for determining the first set of cyclic delay values based on the delay indicated by the feedback information, Device for wireless communication. The method of claim 19, Means for autonomously selecting the cyclic delay values in the second set without notifying the receiver, Device for wireless communication. The method of claim 19, Means for performing precoding based on a precoding matrix before or after the first processing for cyclic delay diversity and before the second processing for cyclic delay diversity, Device for wireless communication. A machine-readable medium containing instructions, When the instructions are executed by a machine, the machine causes Performing first processing for cyclic delay diversity based on a first set of cyclic delay values known to a receiver of a data transmission; And Perform second processing for cyclic delay diversity based on a second set of cyclic delay values unknown to the receiver, To perform operations comprising a, Machine-readable medium. The method of claim 25, When executed by the machine, cause the machine to: Performing the first processing and the second processing on cyclic delay diversity on data; And Perform only the second processing on cyclic delay diversity for a pilot To perform operations further comprising; Machine-readable medium. The method of claim 25, When executed by the machine, cause the machine to: Performing the first processing for cyclic delay diversity in a frequency domain; And Performing the second processing for cyclic delay diversity in a time domain To perform operations further comprising; Machine-readable medium. Perform first processing on cyclic delay diversity based on a first set of cyclic delay values known to the receiver of the data transmission, and perform cyclic delay diversity based on a second set of cyclic delay values known to the receiver. At least one processor configured to perform a second processing on the processor; And A memory coupled to the at least one processor, Device for wireless communication. The method of claim 28, The at least one processor is configured to perform the first processing and the second processing on cyclic delay diversity for data and to omit the first and second processing on cyclic delay diversity for a pilot. , Device for wireless communication. Receive a data transmission sent using cyclic delay diversity based on a first set of cyclic delay values known to the receiver and a second set of cyclic delay values unknown to the receiver, and receiving the second set of cyclic delay values Receive pilot transmissions sent using cyclic delay diversity based only on G, derive multiple-input multiple-output (MIMO) channel estimates based on the received pilot transmissions, At least one processor configured to perform MIMO detection for the received data transmission based on the first set of channel estimation and cyclic delay values; And A memory coupled to the at least one processor, Device for wireless communication. The method of claim 30, The at least one processor evaluates the performance of a plurality of precoding matrices, sends feedback information indicative of one precoding matrix selected from the plurality of precoding matrices, and further receives the received information based on the selected precoding matrix. Configured to perform MIMO detection for the transmitted data transmission, wherein the data transmission is sent using precoding based on the selected precoding matrix, Device for wireless communication. The method of claim 30, The at least one processor obtains a plurality of MIMO channel matrices for a plurality of subcarriers for the MIMO channel estimate based on the received pilot transmission, and the plurality of MIMO based on the first set of cyclic delay values. Determine a plurality of cyclic delay matrices for the subcarriers of, derive a plurality of spatial filter matrices for the plurality of subcarriers based on the plurality of cyclic delay matrices and the plurality of MIMO channel matrices, Configured to perform MIMO detection for the received data transmission based on the plurality of spatial filter matrices, Device for wireless communication. 33. The method of claim 32, The at least one processor is configured to derive the plurality of spatial filter matrices further based on a precoding matrix used for the data transmission, Device for wireless communication. The method of claim 30, The at least one processor is configured to evaluate the performance of the plurality of delays and send feedback information indicative of a delay selected from the plurality of delays, wherein the first set of cyclic delay values is dependent upon the selected delay. Determined based on Device for wireless communication. The method of claim 30, Wherein the first set of cyclic delay values corresponds to a cyclic delay longer than a cyclic prefix length and the second set of cyclic delay values corresponds to a cyclic delay shorter than the cyclic prefix length Device for wireless communication. The method of claim 30, The at least one processor is further configured to derive the MIMO channel estimate further based on a unitary matrix used for the pilot transmission but not for the data transmission. Device for wireless communication. Receiving a data transmission sent using cyclic delay diversity based on a first set of cyclic delay values known to the receiver and a second set of cyclic delay values unknown to the receiver; Receiving a pilot transmission sent using cyclic delay diversity based only on the second set of cyclic delay values; Deriving a multiple-input multiple-output (MIMO) channel estimate based on the received pilot transmission; And Performing MIMO detection for the received data transmission based on the first set of MIMO channel estimation and cyclic delay values; Method for wireless communication. The method of claim 37, The performing of the MIMO detection may include: Determining a plurality of cyclic delay matrices for a plurality of subcarriers based on the first set of cyclic delay values; Deriving a plurality of spatial filter matrices for the plurality of subcarriers based on the plurality of cyclic delay matrices and the plurality of MIMO channel matrices for the MIMO channel estimate; And Performing MIMO detection for the received data transmission based on the plurality of spatial filter matrices; Method for wireless communication. The method of claim 38, Deriving the plurality of spatial filter matrices comprises deriving the plurality of spatial filter matrices further based on a precoding matrix used for the data transmission. Method for wireless communication. The method of claim 37, Evaluating the performance of the plurality of precoding matrices; And Sending feedback information indicating one precoding matrix selected from the plurality of precoding matrices, Wherein the data transmission is sent using precoding based on the selected precoding matrix, and the MIMO detection for the received data transmission is performed further based on the selected precoding matrix, Method for wireless communication. The method of claim 37, Evaluating the performance of the plurality of delays; And Sending feedback information indicative of a delay selected from the plurality of delays, Wherein the first set of cyclic delay values is determined based on the selected delay, Method for wireless communication. Means for receiving a data transmission sent using cyclic delay diversity based on a first set of cyclic delay values known to the receiver and a second set of cyclic delay values unknown to the receiver; Means for receiving a pilot transmission sent using cyclic delay diversity based only on the second set of cyclic delay values; Means for deriving a multiple-input multiple-output (MIMO) channel estimate based on the received pilot transmission; And Means for performing MIMO detection for the received data transmission based on the first set of MIMO channel estimation and cyclic delay values; Device for wireless communication. The method of claim 42, wherein Means for performing the MIMO detection, Means for determining a plurality of cyclic delay matrices for a plurality of subcarriers based on the first set of cyclic delay values; Means for deriving a plurality of spatial filter matrices for the plurality of subcarriers based on the plurality of cyclic delay matrices and the plurality of MIMO channel matrices for the MIMO channel estimate; And Means for performing MIMO detection for the received data transmission based on the plurality of spatial filter matrices; Device for wireless communication. The method of claim 43, Means for deriving the plurality of spatial filter matrices comprises means for deriving the plurality of spatial filter matrices further based on a precoding matrix used for the data transmission; Device for wireless communication. The method of claim 42, wherein Means for evaluating the performance of the plurality of precoding matrices; And Means for sending feedback information indicating one precoding matrix selected from the plurality of precoding matrices, Here, the data transmission is sent using precoding based on the selected precoding matrix, and the MIMO detection for the received data transmission is further performed based on the selected precoding matrix. Device for wireless communication. The method of claim 42, wherein Means for evaluating the performance of the plurality of delays; And Means for sending feedback information indicative of a delay selected from the plurality of delays, Wherein the first set of cyclic delay values is determined based on the selected delay, Device for wireless communication.

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