TW200847495A - Memory cell with sidewall contacting side electrode - Google Patents

Abstract

A memory cell includes a memory cell layer over a memory cell access layer. The memory cell access layer comprises a bottom electrode. The memory cell layer comprises a dielectric layer and a side electrode at least partially defining a void with a memory element therein. The memory element comprises a memory material switchable between electrical property states by the application of energy. The memory element is in electrical contact with the side electrode and with the bottom electrode. In some examples the memory element has a pillar shape with a generally constant lateral dimension with the side electrode and the dielectric layer surrounding and in contact with first and second portions of the memory element.

Description

200847495tw3378pa • IX. Description of the Invention: [Technical Field] The present invention relates to a high-density memory device based on a memory material and a method of manufacturing the same, and the high-density memory device is, for example, a resistive random access memory (resist random Access memory, RRAM) device. Recall that materials are converted to electrical properties by the applied energy. Memory materials can be phase change memory materials or other materials. Phase change memory materials include chalcogenide materials. [Prior Art] Phase change memory materials are widely used in readable and writable optical discs. These materials have at least two solid phases, for example, including a generally solid amorphous phase and a generally solid crystalline phase. The readable and writable optical disc produces phase changes using laser pulses and reads the optical properties of the memory material after phase changes. Phase change memory materials, such as chalc〇genide and similar materials, can also undergo phase change in the integrated circuit by applying a certain degree of current. Generally, the resistance value of the amorphous state is higher than that of the crystalline state, and the difference in the resistance value can be immediately detected to represent the data. These properties make it interesting to apply programmable resistance materials to form non-volatile memory loops that can be randomly read and written. ^Operational currents in which amorphous cancers change to a crystalline state are generally low, and the operating current from crystallization to non-crystalline state, also known as reset (tetra) et), is often high. The current change process during reset includes a brief high current density pulse to melt or collapse the crystalline structure, followed by a bonfire phase change process.

200847495rW3378pA The phase change material is rapidly cooled, and at least a portion of the phase change structure is stabilized in the non-crystalline state. The weight of the phase change material from the crystalline state to the non-crystalline state is as low as possible, and the size of the 4 currents required for resetting is reduced by the size of the material component of the memory cell. It is reduced by reducing the contact area between the cladding and the phase change material. In this way, a higher current density can be achieved with relatively small current values through the phase change material elements. The use of a small amount of programmable resistance material, especially in small holes, has been developed. Patent Description for the production of small holes including: Ovshinsky's "Multi-bit single memory cell elements have tapered contacts" (Mutibit Single Cell Memory Element Having Tapered)

Contact), U.S. Pat. Ν0·5,687,112, issued on November 11, 1997; Zahorik et al., "Method for manufacturing sulfide memory devices" (Meth〇d 〇f

Making Chalogenide Memory Device), US Pat. Ν 0·5, 789, 277, released on August 4, 1998; D〇an et al., "Controlled Bidirectional Phase Change Semiconductor Memory Devices and Their Applications" (Controllable Ovonic Phase) -Change Semiconductor Memory

Device and Methods), U.S. Pat·Ν0·6,150,253, released on November 21, 2000. In a phase change memory device, data is stored by causing a phase change material to be converted between an amorphous state and a crystalline state, and the current heats the material and causes a transition between the two states. The operating current from the amorphous state to the crystalline state is generally low, changing from a crystalline state to an amorphous state, also known as a reset, and the operating current is generally higher. The phase change material is converted from the crystalline state to 6 200847495TW3378pa. The reset current of the amorphous state is reduced to the smaller the better, and the magnitude of the current set in the reset process can be reduced by reducing the size of the memory cell phase change material element. Since the magnitude of the current required for the reset process depends on the volume of the phase change material that must be changed to form a phase change memory device, the memory cell produced by standard semiconductor fabrication technology is the smallest size condition of the semiconductor device. Restricted, so technology must be developed to provide a range of memory sub-sublithographic sizes.

Surgery and sub-lithography still lack reproducibility and reliability in large-scale high-density memory devices. Designing very small electrodes to transfer current to the phase change material body is a method of controlling the phase change memory intracellular reaction area. This small electrical structure includes a phase change at a small area of the junction within the phase change material. This small area is like the top of a mushroom. Please refer to U S. pat. Ν0·6,429,064 ’ on August 6, 2002, by Wicker, “Reduced Contact Areas of Reduced Contact Areas” (Reduced Contact Areas of

"Method of Fabricating a Small Area of Contact Between Electrodes"; US· Pat· Ν 0·6, 462, 353, published on August 8, 2002 by Gilgen, "Method of Fabricating a Small Area of Contact Between Electrodes"; Pat·Ν0·6,501,111, “Three-Dimensional (3D) Programmable Device” published by Lowrey on December 31, 2002; US Pat. Ν0·6,563, 156, "Memory Element and Methods for Making Same" published by Harshfied on July 1, 2003. 〇200847495TM High-reliability manufacturing street, the memory cell of the resistive material As described above, the use of reproducibility and design can form an opportunity to have small reaction zone programmable methods and structures. SUMMARY OF THE INVENTION In summary, the present invention relates to an electrical characteristic (IV) memory cell by applying a memory material, and the special replacement

: phase change random access accumulated on the surface of the phase change material;;: electric Yang: the material of change is, for example, germanium (Ge_Sb_Te, GST) '^^ 2, for example, titanium nitride (TiN) has a higher coefficient of thermal expansion Large, and make the upper eight = poor. Since the phase change material is deposited on the bottom electrode, it is opposite to the interface layer between the material and the bottom electrode. The invention solves the problem of "9" = simultaneous deposition on the bottom electrode and the side electrode to help the 9-plane surface. According to one aspect of the invention, the invention provides a memory cell, the electrical property state of the memory material. Included: Take:: The cladding is located above the memory cell access layer. Memory cell: layer and pole. The memory cell layer includes a dielectric layer and side electrodes at the bottom of the dielectric layer and at least part of the dielectric layer The opening is defined, and the memory element (9) is electrically connected to the inner side. The memory element includes a memory material, and the memory material is converted by the opening; the opening is converted into an electrical characteristic state. The memory element is connected to the side electrode and the bottom electrode ♦ In the example, the memory element has a columnar shape with a lateral direction: a constant value, and the side electrode and the dielectric layer surround and contact the memory element = degree % and the second area.

TW3378PA 200847495 According to another aspect of the invention, the method of the invention comprises the electrical property state of the τ U 科 U 科 藉 藉 藉 藉 藉 施加 施加 施加 施加 施加 施加 施加 施加 施加 施加 。 。 。 。 。 。 。 。 。 。 The method a includes the steps of: providing a layer system comprising a bottom electrode; depositing a first dielectric reed: a fiber access., a ^7 τ memory cell access layer; a deposition side turtle material in the first dielectric The layer is formed by the opening of the side electrode to expose the bottom electrode, thereby generating a side electrode element memory element and electrically connecting the side electrode element with the bottom electrode. The material element comprises a memory material, and the conversion e material The lanthanide is transferred by the applied energy: 屯 characteristic state. In some examples, forming an opening: a column of steps: depositing an auxiliary layer over the side electrode material; :, a 'hole material in the lower layer, aligning the bottom; sinking the material channel 7 in the auxiliary shrinkage hole; Hole::=: Cow·, remove the auxiliary layer. The main side of the present invention is to make the above-mentioned contents of the present invention more obvious and easy to understand. The following is only a target example, and the following description will be described in detail with reference to the following:: Niu and soil [Embodiment] The description of the present invention is made below. The social == method of the preferred embodiment will be specifically described. Those skilled in the art will recognize that the 'exposed preferred embodiment' is used to limit the invention, and the present invention can be defined by other technical means: the application of the invention is defined by the scope of protection of the invention. Those skilled in the art will appreciate that there are many equals (four) in the following two cases. The description of the town is not particularly changed, and the same sections in the respective embodiments will be referred to by the same reference numerals. 9 200847495 - Referring to Figure 1, there is shown a block diagram of a bulk circuit 10 in accordance with a preferred embodiment of the present invention. Circuit 10 includes a memory array 12 that is implemented by placing phase change memory cells (not shown) on a semiconductor substrate. The word line deciphering 14 is electrically connected to a plurality of word lines 16. Bit line. The decoder (bit line —) 18 is electrically connected to the plurality of bit lines 2〇, and the bit line 20 is used for reading or writing data to the phase change memory of the memory array 12 (not shown). . The address is passed via bus bar 22 to word_yuan line decoding and driver 14 and bit line decoder 18. The sense amplifier and input data structures in block 24 are coupled via data bus 26 to bit line decoder 18' data in data input/output/output on integrated circuit 10, or Other data sources internal or external to the integrated circuit 1 are passed to the data input structure of block 24. Other circuitry 30 may include integrated circuitry 10, such as a general purpose processor or a special application circuit, or a combination of modules that support rain-system-on-a-chip functionality via array 12. The data out is supplied from the sense amplifier of block 24 to the input/output port on the integrated circuit 10 via the data output line 32, or the data may be supplied to other data sources inside or outside the integrated circuit 10. Ground. The controller 34 used in this embodiment controls the operation of the bias configuration supply voltage 36 by means of a bias configuration device, such as reading, programming, clearing, viewing clearing and viewing the stylized voltage. The controller 34 can use the special purpose logic (Upurp〇 Se logical circuitry) well known in the art. In another embodiment, the controller 34 includes a general 2008-47495 general-purpose process, which can be applied to the same integrated circuit to perform computer programming to control the operation of the device. In other embodiments, the special purpose logic circuit and the general purpose processor are combined to implement the controller 34. As shown in FIG. 2, each of the memory cells of the record column 12 includes an access transistor (or other access device such as a diode) 38, 4, 42 and a material and phase change elements 46, 48, 50 and 52. The source terminals of the respective access transistors %, 40, 42 and 44 are commonly connected to the source line 54, and the source line μ terminates at the source terminal H 55. In other implementations, the secret lines are not electrically connected to each other' but are independently controlled. The strip line 16 includes word lines 56 and 58 extending in parallel in a first direction, and word lines 56 and 58 are electrically coupled to a word τ line decoder 14. Access transistor %

And the gate of the gate is connected to a common word line, for example, the word line $6. The gates of the access transistors 4 G and 44 are connected in common to a word line, such as word line 58. The plurality of bit lines 2A include bit lines 6A and 62, and the end of the phase change element 46A 48 is connected to the bit line 6A. In particular, phase change element 46 is coupled to the access pen transistor 38 and to the extreme and bit lines, and phase change element 48 is coupled to access transistor 40 and terminal and bit line 60. Similarly, the phase change element 50 is connected to the access transistor 42 without the extreme bit line 62, and the phase change element 52 is connected to the access terminal f of the f(4) 44 and the bit line 62. It should be noted that the above four memory cells are convenient for describing the memory array 12, and the memory_12 may include tens of millions to several million similar memory cells. Of course, other array structures can also be implemented, for example, by connecting phase change elements to the source terminals. 11 200847495TW3378pa ^ Please refer to FIG. 3, which is an explanatory diagram of a memory device 64 according to an embodiment of the present invention. The memory device 64 includes a memory cell access layer 66 (shown in Figure 5) and a memory cell layer 68 on the memory cell access layer 66. The electrically conductive buffer layer 70 is disposed between the bit line 72 and the memory cell layer 68. Memory cell access layer 66 has an upper surface 67, and memory cell access layer 66 includes a dielectric fill layer 74, which is preferably comprised of a dioxide dioxide layer. The memory cell access layer 66 also includes a stacked layer 76 that includes a dam 78 and a bottom electrode 80 that extends to the upper surface 67. The dam 78 is preferably tungsten (tungsten, W), and the bottom electrode 80 is preferably The electrically conductive material composition is, for example, titanium nitride (TiN), tungsten nitride (WN), titanium aluminum nitride (TiAIN) or tantalum nitride (TaN) for increasing contact with the memory element 82 of the memory cell layer 68. Note that the component 82 includes the memory material by the applied energy conversion electrical property. The heart is a phase change material such as; G: GST, which will be described in more detail later. The memory cell layer 68 has a top layer of y..., y has an upper surface 84, and the memory layer 68 includes a dielectric reed = and =: a member 88, a side electrode member 88 and a dielectric layer (four)' as shown in FIG. Having the memory element 82 side electrode element 88 both 圯k'7 element 82 and

Dioxin rm,: Extension surface 84. The dielectric layer % can be an oxide of B (Α10χ), dielectric: * compound (wind) or a rim body. In this configuration, the bottom or: is, the electric % of the expansion coefficient is regarded as a thermal insulator, and the heater and the dielectric layer "the conversion block 90 of the dielectric chamber 2 in the component U is located at the portion surrounded by the 包 续 %.丨义' Please refer to Figure 4, which shows the memory device 64 on the third figure.

TW3378PA 200847495 The figure, the element 82 and the bottom electrode are indicated by dashed lines. Please refer to Figures 5 to 15, which are (iv) a flow chart according to the present invention - an embodiment of the memory device 64. In Fig. 5, the memory cell access layer 66 includes a stacked layer 76 and a common source (four) between the first and the word line 94. In this embodiment, the electric = body reduction is a device, and the other devices such as the second and the like are also in the embodiment. Figure 6 shows that the deposited dielectric layer 86 is in the center of the side electrode material layer, and the electrode material layer 96 is deposited for the subsequent formation of the side electrode element = upper = the electric layer % is generally non-fourth formed in the electrode material layer 7th The figure shows the result of forming the opening (10) in the auxiliary dielectric layer %, and the opening is usually placed on the center of the bottom electrode 8 。. In Fig. 8, the material layer 102 (usually non-(iv)) is deposited on the structure of Fig. 7, so that the material 102 is deposited on the side electrode material layer 96 and the auxiliary meso layer 98 defining the opening ι" A shrinkage hole 1〇4 having a small radius is formed. The bond used to deposit the material Re 102 is, for example, an atomic layer deposition 1 & ah (10), ALD ALD) process. Figure 9 shows the results of the micro-diameter hole dumping step. This step removes most of the material layer 102 and forms a micro-diameter hole 1〇6 through which the micro-diameter hole 1〇6 passes and passes through the side electrode material layer% and the dielectric layer 86' until the bottom electrode 8〇 Stop after exposure. As shown in Figure 1() / after removing the remaining amorphous 8-layer auxiliary dielectric layer 98 and material layer 1〇2 by means of potassium hydroxide (KO·(四), leaving the electrode material layer % and dielectric The opening 86 defined by layer 86. 曰13

W3378PA 200847495

A memory material (e.g., a phase change material such as GST) is deposited within the opening. This step is followed by a planarization step, such as chemical machine bamboo polishing, to form memory element 82 and upper surface material of memory cell layer 68. Referring to Fig. 11, each memory element 82 includes a first region 1〇7, the first region 107 has a first outer surface layer, and the side electrode member 88 surrounds and contacts the first outer surface layer of the memory device 82. In addition, each memory element includes a second region 1G9' wherein the second region has a second outer surface layer and a dielectric 86 surrounds and contacts the second outer surface layer of memory element 82. " In some embodiments, the electrically conductive buffer layer 70 is deposited on the upper surface material, an electrically conductive buffer layer 7G, such as a titanium nitride (TiN) electrically contacted with a bit line layer 110' deposited on the electrically conductive buffer layer 70. The electrically conductive buffer layer is used to increase contact between the memory element 82 and the bit line layer 11 . The a is shown in the upper view of Fig. 12, and the memory element 82 is shown by the dotted line to describe the position and space of the memory element 82. f 14 and 15 illustrate the trench 112 extending through the bit line layer 11G, the electrically conductive buffer layer 7 () and the side electrode material layer 96' and ending at the top of the dielectric layer 86 to form a memory device. The memory device has a bit line 72 and side electrode elements 88. Figure 16 illustrates a memory device material of another embodiment. The memory element 82 of the memory module 64 defines the illusion of the upper line by the side electrode element δδ: the cross-section is larger than the lower block defined by the dielectric layer 86 of the memory element 82. In other embodiments, the side electrode element 88 is connected to the bit line in a different manner. For example, the side electrode element 88 is connected to the bit line by a dielectric layer of (4) 4. The t-type insulator including the dielectric layers 74 and 86 may include an electrical insulator 14 200847495TW337spa • one or more elements selected from the group consisting of bismuth (Si), titanium (butadiene, button (Ta), nitrogen) (State, Oxygen (0) and Carbon (〇). In this embodiment, the dielectric layer 86 has a lower coefficient of thermal expansion, less than about 0.014 J/cm*K*sec. In other embodiments, when the memory element When the 82 series is composed of a phase change material, the thermal expansion coefficient of the dielectric layer 86 is lower than the amorphous thermal expansion coefficient of the phase change material. When the phase change material includes GST, the thermal expansion coefficient of the dielectric layer % is less than about 0.003 J/ Cm*K*sec, a typical thermal insulating material comprising a combination of elements such as bismuth (Si), carbon (C), oxygen (0), fluorine (F) and hydrogen (H). Spring suitable thermal insulation materials include Cerium oxide (SiO 2 ), bismuth carbon oxide (SiCOH), polyiinide, polyamide, and fluorocarbon polymers. Other examples of suitable thermally insulating dielectric materials are more examples. Including fluorinated cerium oxide (fluorinated SiO 2 ), silsesquioxane, polyaryl ester (p〇lyar Yieneethers), Parylene, fluoro-polymers, fluorinated amorphous carbon, diamond like Carb〇n, porous sulphur dioxide 01*0113 311^), mesoporous silica, porous sesquioxane material (p〇r〇us silsesquioxane), porous polyaluminum (p〇r〇us p〇lyamide) and porous Porous polyarylene ethers. In other embodiments, the thermal insulation structure includes a gas-filled hole for thermal insulation. The dielectric layer may be combined by one or more layers to provide heat and electricity. Insulation. Useful features of a memory material (e.g., a phase change material) having a programmable resistance form feature include a material having a programmable resistance, preferably a reversible process, such as a material having at least two solid phases and passing current With 15 200847495τ δ ΡΑ , ^ reaction. Reversible process at least two solid phases including amorphous phase and crystallization However, during operation, the programmable resistance material may not be completely non-junction phase or complete 妓 crystal phase, transition Manifold mixed phase may not be detected having an intrinsic difference in the two solid phases should typically be stable for the respectively phase and piece goods having different electrical characteristics. The programmable resistive material may be a chalcogenide material, and the chalcogenide material may include. In the sections disclosed below, phase changes or other memory materials are known as GST, and it is well known to those skilled in the art that other forms of phase change materials can be employed. The material used to implement the memory cell is illustrated herein by the compound 锗锑碲Ge2Sb2Te5. The memory device 64 described herein is fabricated through standard lithography and thin film deposition processes. 'No special sub-lithographic patterning steps are required, and a very small size memory cell can be made, which is controlled during the process. There will be actual changes. In an embodiment of the invention, the memory material may be a moldable material such as a phase change material of 锗锑碲GQSb2!^ or other materials of the following. The phase change in memory element 82 is a block of cells, so the value of the reset current applied for phase change is also very small. The memory device 64 of the present embodiment includes a phase change memory material including a chalcogen compound and other materials to constitute the memory element 82. Chalcogens include any of the following four elements of oxygen (〇), sulfur (S), strontium (Se) and strontium (Te), all of which belong to the sixth group of elements of the periodic table, and the chalcogenides include A compound produced by a metal of a genus and a positively charged element or a radical. The chalcogenide alloy (chalcogenide all〇y) includes a combination of a chalcogenide compound and other materials such as transition metals.

200847495TW3378PA — The chalcogenide alloy typically contains one or more elements of the sixth group of the periodic table, such as germanium (Ge) and tin (Sn). Generally, the chalcogenide alloy includes one or more combinations of metals such as bismuth (Sb), gallium (Ga), indium (In), and silver (Ag). Many phase change memory materials have been described in detail in the scientific literature, including the following alloys: gallium germanium (Ga/Sb), indium germanium (In/Sb), indium selenide (In/Se), germanium (Sb/Te),锗碲(Ge/Te), 锗锑碲(〇6/85/丁6), Indium/Sb/Te, Ga/Se/Te, Tin/Sb /Te), Indium/Sb/Ge, Ag/In/Sb/Te, 锗锡锑碲• (Ge/Sn/Sb/Te), 锗锑Selenium (Ge) /Sb/Se/Te) and bismuth sulphur (Te/Ge/Sb/S). In the family of germanium (Ge/Sb/Te) alloys, most of the alloy compositions are applicable. The alloy composition is represented by TeaGebSb1G (Ka+b), where a and b represent atomic percentages, and the sum of the atomic ratios of the compounds is 100%. The survey found that the average proportion of the most commonly used alloys, the concentration of hoof (Te) in the deposited material is less than 70%, usually less than about 60% and between 23% and 58%, preferably between Between about 48% and 58%. The concentration of germanium (Ge) is above about 5%, preferably the average range is between about 8 10% and 30%, and usually less than 50%, and the optimum concentration range of germanium (Ge) is approximately Between 8% and 40%. The study found that the remaining main component of the compound is bismuth (Sb) (Ovshinsky, f112 patent lines 1 and 11). The specific alloys identified by other researchers include Ge2Sb2Te5, GeSb2Te4, and GeSb4Te7 (NoboruYamada's "Ge-Sb-Te phase change available for high data rate recording discs" (p〇|;ential Of Ge-Sb- Te Phase-Change Optical Disks for High-Data-Rate

Recording), 1997 SPIE No. 3109, pp. 28-37). More often 17

TW3378PA 200847495 See ground, chromium (Cr), iron (1^), nickel (see), 铌 (仙), palladium (? 幻, platinum (? 〇 and other transition metal alloys or mixtures can be combined with 锗锑碲 (Ge / Sb /Te) mixing to form a phase change alloy having a programmable resistance property. In the case of Ovshinsky, 112 lines 11 to 13, the memory material is preferably greatly assisted by the combination of the reference material. The first structural state is generally a non-crystalline solid phase of the material, and the second structural state is usually a crystalline solid phase of the material that causes the memory cell to be localized in the active channel region. Ordered 'these phase change materials are at least two-phase steady state. "Amorphous" refers to a relatively unordered structure (less order than a single crystal), and its detectable 4 inch is more than the crystalline phase. High resistance. "Crystal phase" refers to a more ordered structure (more ordered than an amorphous structure), which is detectable to have a lower electrical resistance than an amorphous phase. Generally, phase change materials Can be generated between different local order states Sexual transformation, and the convertible game. The 卩-human sequence hunting system spans the completely amorphous state and the completely crystalline state. Other materials that are affected by the change of the crystalline phase and the amorphous phase include atomic ordering and freedom. The electron density and activation energy. By combining the gray-scale state of the complete one-day phase/70 king crystal phase, the phase change material can change correspondingly in the electrical properties of the phase change material of the two-phase change material. Another force, the electric pulse from the -phase continent tends to make the phase change material change = 砚: pulse to the shorter and larger amplitude of the pulse heart tends to change the phase change material to 18

rW3378PA 200847495 - The general crystalline state ' is called a control pulse. The shorter and more energetic enough is sufficient for the bond of the crystalline structure to be _, and the atoms of the yarn are rearranged to the crystalline state. Choosing the appropriate pulse amplitude wave rule of thumb to judge, does not require excessive experimentation, especially the phase change material and the structure. The following brief description and finishing of four forms of resistive memory materials 1 · Chalcogenide materials

GexSbyTez

x:y:z=2:2:5 or other composition 'x:0~5, y:〇~5 and ζ:〇~ι〇一▲ GeSbTe is for example nickel-based (Ni_), sulfhydryl ( The doping of Si_) and titanium (Ti_), or the doping of other elements, can also be used. Forming method: by a physical vapor deposition (PVD) sputtering method or a magnetron sputtering method, a reaction gas such as helium argon (Ar), nitrogen (N2), or helium (He), etc. The chalcogenide is controlled to have a pressure in the range of ImTorr~l〇〇mT〇rr, and the deposition process is usually completed at a temperature. The depth-to-width ratio controlled by the collimator can be used to increase the fill-in perf〇mance between i and 5. The direct current (DC) bias can be applied to tens to hundreds of volts. The additive effect is enhanced, in other words, the collimator and the DC bias can be combined at the same time. After deposition, it is sometimes necessary to anneal in a vacuum or nitrogen (N2) environment to promote the crystalline state of the chalcogenide material. The annealing treatment is usually performed at a temperature ranging from 100 ° C to 400 ° C with an annealing time of less than 30 minutes. Conditions are carried out. 19

200847495TW3378PA • The thickness of the 4-member compound material depends on the design of the memory cell structure. In the general case, the thickness of the chalcogenide material may have a phase change characteristic above about 8 Xinjiang, so that the material can exhibit at least two stable and different resistance states. 2. Giant magnetoresistance (CMR) material PrxCayMn03 x:y=0.5:0.5 or other composition, x:0~1 and y:〇~1 with $a giant magnetoresistive material Oxides including short (Μη) may also be used, forming methods. By physical vapor deposition sputtering or magnetron plating: the reactive gases such as nitrogen (four), (four), oxygen (four) and or It is 氦 (He) and so on, and the pressure range is controlled between imt〇rr~i〇〇mt〇rr, and the deposition temperature can be from room temperature to 6〇〇. 〇, the scope depends on the processing conditions after deposition. The depth-to-width ratio controlled by the collimator can be increased between the 5 and the filling effect. The DC bias can be applied tens to hundreds of watts. You can also use the 乂~ plus fill effect. In other words, the collimator and DC bias can be used in combination at the same time. Applying tens of Gauss to ι〇, the Gaussian magnetic field can increase the magnetic crystalline phase. ^, after deposition, in the vacuum, gas (team) or nitrogen oxide (02 / N2) mixed atmosphere, the annealing process has a daily maintenance to improve the crystal state of the giant magnetoresistive material, the annealing process is usually in the temperature range arm C to It was carried out with conditions of annealing time below 2 hours. The thickness of the giant magnetoresistive material depends on the design of the memory cell structure. 20

200847495rW3378PA • The thickness of the giant magnetoresistive material can be regarded as the core material from 1 Onm to 200nm. The buffer layer bismuth copper oxide YBC0 (YBaCu03, which is a high temperature superconductor material) is commonly used to increase the crystalline state of the giant magnetoresistive material, and the thickness of YBCC^YBCO deposited before depositing the giant magnetoresistive material ranges from 30 nm to 200 nm 〇3·two Elemental compound nickel oxide (NixOy), titanium oxide (Tix〇y), aluminum oxide (Alx〇y),

Tungsten oxide (wxoy), zinc oxide (Znx〇y), yttrium oxide (Zrx〇y) and copper oxide (CuxOy), etc. x:y=0.5:0.5 or other composition, X:〇~1 and yAq form Method: deposition, sputtering by physical vapor deposition or magnetron sputtering, 'transmission of reactive gases such as argon (Ar), nitrogen (D, oxygen (〇2) and or helium (He), etc. 'Control pressure range between lmT〇rr~i〇〇mT〇rr and use - metal oxide dry material, such as see, Ding Bing, AX, WxOy, Znx〇y, Zrx〇y or CUx〇y Etc., the deposition process is completed at room temperature. The depth-to-width ratio controlled by the collimator between 1 and 5 can be used to apply tens of tens to hundreds of watts to the human wire 'money bias. _, the quasi-wire jet bias is an environmentally retractable atmosphere, and, in order to enhance the elemental oxygen in the oxidized metal IU, &chemistry; in the temperature range of 400 ° C to 600 ° C Interval and low 21 2〇〇847495TW3378pa • Performed under the conditions of 2 hours annealing time. 2. Reactive deposition: by physical vapor deposition sputtering or reactive magnetron sputtering, by reaction The gas is, for example, argon oxygen (Αγ/〇2), argon nitrogen oxygen (Αγ/Ν^Ο2), pure oxygen (〇2), helium oxygen (He/〇2), or helium nitrogen oxide (He/N/O2). Etc., the control pressure range is between lmT 〇rr~1〇〇mT〇rr, and a metal target such as nickel (Ni), titanium (Ti), aluminum (A1), tungsten (W), zinc (for example) is used. Zn), junction (Zr) or copper (cu), etc., the deposition process is usually completed at room temperature. The aspect ratio of 1 to 5 controlled by the collimator can be used to increase the filling effect, DC bias Pressure application of tens to hundreds of watts can also be used to increase the filling effect. If necessary, the collimator and DC bias can be used simultaneously. Sometimes it is necessary to vacuum, nitrogen (N2) or nitrogen oxide after deposition. (N2/〇2) Mixed gas ί The annealing treatment of 丨衣丨 is used to promote the diffusion of elemental oxygen in the oxidized metal. Annealing is usually carried out at temperatures ranging from 400 ° C to 600 ° C and less than 2 hours annealing time. The conditions are carried out. 3 · Oxidation · Fine emulsification system from the South Temperature, such as the rapid thermal process (RTP) furnace system, the temperature range from 200 ° 〇 to 700 ° C, and the use of pure oxygen (〇 2) or Nitrogen Oxygen (Wan/〇2) The atmosphere is controlled at a pressure between several microtorres (mtorr) and one atmosphere. The time range of the process can range from a few minutes to several hours. Another oxidation method is plasma oxidation, radio frequency (RF) or DC. Source plasma, mixed with pure oxygen (〇2), nitrogen (N2/〇2) or argon nitrogen (Ar/N2/〇2), and controlled to oxidize metal between 1 mtorr and 1 00 mtorr The surface layer, for example, nickel (Ni), titanium (Ti), Ming (A1), tungsten (W), hexadium (Zn), recorded (Zr) or copper (Cu) 22 200847495TW3378pa _ etc. 'oxidation time range can be From a few seconds to a few minutes, the oxidation temperature ranges from room temperature to 300 ° C depending on the degree of plasma oxidation. 4. Polymer material Tetrazyanoguinodimethane (TCNQ) is doped with copper (cu), copper 60 (Cu60) or silver (Ag), and the like. PCBM-TCNQ mixed polymer of [6,6]_phenyl-C61-butyric acid methyl ester, PCBM) • Formation method: 1. Evaporation: by thermal evaporation, for example It is an electron beam evaporation (e-beam evaporation) or a molecular beam epitaxy (MBE) system. The solid TCNQ and the doped particles are evaporated together in a single cavity, and the solid TCNQ and the doped particles are first placed on a tungsten plating source (W-boat), a group plating source (Ta-boat) or a ceramic clock source (ceramic boat). And through a high current or electron beam application to melt the material so that the material is mixed and deposited on the wafer, there is no chemical reaction or reaction gas, and the pressure at the end of the deposition is between 1 (T4torr to l〇- Between 1Qt〇rr and controlling the wafer temperature range from room temperature to 200 ° C. After deposition, it is sometimes necessary to anneal in a vacuum or nitrogen (N 2 ) atmosphere to promote the diffusion of the composition of the polymer material. Annealing is usually The temperature range is from room temperature to 300 ° C and the annealing time is less than 1 hour. 2. Spin coating: the spin-coated coater is placed at a lower speed than the TCNQ solution. 23 thousand revolutions per minute (i〇〇〇rpm)

200847495rW3378PA on the turntable. After spin coating, the wafer is placed at room temperature or waited to form a solid in an environment at a temperature below 20 CTC, and the waiting time depends on temperature and forming conditions, ranging from minutes to days. For the rest of the materials used in manufacturing, composition, and phase-change random access, please refer to the US Application Patent ,·, published on July 17, 2005, entitled “Thin Film Melting Phase Change Random Access” "Thin Film Fuse Phase Change Ram And Manufacturing" Attorney Docket No. MXIC • 1621-1 〇 preferably the bottom electrode 80 and the side electrode element (10) all or part of the block contact with the memory element π includes a The electrode material, for example, titanium nitride (TiN) or other conductors suitable for phase change materials of the memory element 82. In the embodiment of Fig. 3, when the plug 7 8 includes tungsten (w), the side electrode member 88 and the bottom electrode 80 are both formed of titanium nitride (TiN). Other different types of conductors can be utilized for the damming structure, the upper electrode, and the lower electrode structure. These include, for example, Ming (A1) or Ming alloy, TiN, NiN, TiAlN or TaAIN. Other conductors may use one or more elements selected from the following groups: titanium (butadiene), tungsten (w), molybdenum (M〇), Ming (A1), group (Ta), copper (Cu), (Pt), silver (ir), (Ι^), nickel (Ni), ruthenium (Ru), and oxygen (Ο). Titanium nitride (TiN) is a preferred choice because of good connectivity with GST (previously discussed) in memory element 82, and tantalum nitride (TiN) is a commonly used material in semiconductor fabrication processes. Titanium nitride (TiN) is converted at high temperatures in GST, for example at a temperature of 6 〇〇 to 7 〇〇. A good diffusion buffer is provided in the range of 〇. twenty four

200847495 [W3378PA Although other electrical connection materials such as aluminum nitride tantalum (TaA1N), aluminum nitride tantalum (WalN) or titanium aluminum nitride (TiAIN) may be used, the electrically conductive buffer layer 70 is preferably nitrogen. Titanium (TiN). The terms used in the above embodiments of the present invention are, for example, top, bottom, top, bottom, over, under, or center. These names are used to help the invention but not to limit the invention. In view of the above, the present invention has been disclosed in a preferred embodiment, and is not intended to limit the present invention. It will be appreciated by those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. Any and all of the above patents, patent applications, and publications are incorporated by reference. 25

200847495rw3378PA 'A Brief Description of the Drawings FIG. 1 is a block diagram of an integrated circuit 10 according to a preferred embodiment of the present invention, and FIG. 2 is a partial schematic view of a typical memory array of FIG. 1; 1 is a cross-sectional view of a memory device according to an embodiment of the present invention; and FIG. 4 is a view showing a memory device of FIG. 3 with a broken line indicating a top view of the memory element and the bottom electrode; • FIGS. 5-15, which are illustrated A flowchart of a manufacturing process of a memory device in accordance with a third embodiment of the present invention. Figure 16 is a cross-sectional view showing the memory device of the third embodiment.

26

TW3378PA 200847495 ' [Main component symbol description] 10 : Integrated circuit 12 : Memory array 14 : Word line encoder 16 , 56 , 58 , 94 : Word line 18 : Bit line coder 20 , 60 , 62 , 72 · bit line 22, 26: bus bar 10 24: block 28, 32: data output line 30: other circuit 34: controller 36: voltage 38, 40, 42, 44: access transistors 46, 48, 50, 52: phase change element 54: source line® 55: source line terminator 64: memory device 66: memory cell access layer 67, 84: upper surface 68: memory cell layer 70: electrically conductive buffer layer 74: Dielectric fill layer 76: stack 27 200847495TW3378pa 拴 bottom electrode memory element dielectric layer side electrode element conversion block common source line electrode material layer auxiliary dielectric layer, 108: opening: material layer: shrinkage hole: micro-diameter hole : Zone 1: Zone 2: Bitline Layer: Trench

Claims (1)

2〇〇847495TMα • X. Patent application scope: 1. A memory cell comprising: a memory cell access layer including a bottom electrode; and a memory cell layer located above the memory cell access layer, the memory The cell layer includes: a dielectric layer; one side electrode is located above the dielectric layer; the side electrode and the dielectric layer at least partially define an opening 10; and a memory component is located within the opening The memory component includes a memory material that is electrically coupled to the side electrode and the bottom electrode by an applied energy conversion electrical property state. 2. The memory cell of claim 1, wherein the memory element is in direct contact with an upper surface of the bottom electrode. 3. The memory cell of claim 1, wherein the side electrode at least partially surrounds and contacts a first region of the memory element. 4. The memory cell of claim 3, wherein the first region of the memory element comprises a first outer surface layer that surrounds and contacts the first outer surface layer of the memory element. 5. The memory cell of claim 1, wherein the dielectric layer at least partially surrounds and contacts a second region of the memory element. 6. The memory cell of claim 5, wherein the second region of the memory element comprises a second outer surface layer that surrounds and contacts the second outer surface layer of the memory element. The memory cell of claim 6, wherein the second region of the memory element comprises a phase change material having a phase change block in the second region. 8. The memory cell of claim 1, wherein the memory element has a columnar shape with a lateral width maintained at a constant value. A memory device comprising: one of the memory cells according to claim 1; and a one-dimensional wire electrically connected to the side electrode. 10. The memory device of claim 9, further comprising: an electrical conduction buffer electrically connecting the side electrode to the bit line. 11. A memory cell, comprising: a memory cell access layer comprising a bottom electrode; and a memory cell layer overlying the memory cell access layer, the memory cell layer comprising: a dielectric layer; Above the dielectric layer; the side electrode and the dielectric layer at least partially define an opening; and a memory component is located within the opening, the memory component includes a memory material, the memory material is applied by The energy conversion electrical characteristic state, the memory element has a columnar shape maintaining a lateral width and is electrically connected to the side electrode and the bottom electrode; the side electrode surrounds and contacts one of the first regions of the memory element The dielectric layer surrounds and contacts a second region of the memory element; and 30 200847495 FW3378PA The second region includes a phase change material having a phase change block in the second region. 12. A method of fabricating a memory cell, comprising: providing a memory cell access layer, the memory cell access layer comprising a bottom electrode; depositing a first dielectric layer to deposit a layer over the memory cell access layer a side electrode material over the first dielectric layer; forming an opening through the side electrode material and the first dielectric layer to expose the bottom electrode, thereby generating a side electrode element; and generating a The memory element is electrically connected to the side electrode element and the bottom electrode, and the memory element includes a memory material that converts an electrical property state by the applied energy. 13. The method of manufacture of claim 12, wherein the forming and the generating step are completed such that the memory element includes an outer surface layer that surrounds and contacts the outer surface layer of the memory element. 14. The method of claim 12, wherein the step of forming the opening further comprises: depositing an auxiliary layer over the side electrode material; forming a via in the auxiliary layer, the channel alignment a bottom electrode; a material is deposited in the tunnel to create a shrinkage hole in the tunnel; a micro-hole is formed to align with the shrink-hole, the micro-hole extends to the side electrode member; and 31 200847495 W3378PA Remove the auxiliary layer. A method of manufacturing a memory device, comprising: the method of manufacturing according to claim 12; and forming a one-dimensional line above the side electrode member and electrically connected to the side electrode member. 16. The method of manufacturing of claim 15 further comprising forming an electrical conduction buffer between the side electrode element and the bit line. 32