TW200847381A - Integrated circuits and interconnect structure for integrated circuits - Google Patents

Integrated circuits and interconnect structure for integrated circuits Download PDF

Info

Publication number
TW200847381A
TW200847381A TW097109386A TW97109386A TW200847381A TW 200847381 A TW200847381 A TW 200847381A TW 097109386 A TW097109386 A TW 097109386A TW 97109386 A TW97109386 A TW 97109386A TW 200847381 A TW200847381 A TW 200847381A
Authority
TW
Taiwan
Prior art keywords
contact point
region
integrated circuit
contact
source
Prior art date
Application number
TW097109386A
Other languages
Chinese (zh)
Other versions
TWI479634B (en
Inventor
Sehat Sutardja
Original Assignee
Marvell World Trade Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Marvell World Trade Ltd filed Critical Marvell World Trade Ltd
Publication of TW200847381A publication Critical patent/TW200847381A/en
Application granted granted Critical
Publication of TWI479634B publication Critical patent/TWI479634B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4918—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142—Metallic substrates having insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Geometry (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

An integrated circuit comprises N plane-like metal layers, where N is an integer greater than one. A first plane-like metal layer includes M contact portions that communicate with the N plane-like metal layers, respectively, where M is an integer greater than one. A first plane-like metal layer and the N plane-like metal layers are located in separate planes. At least two of a first source, a first drain and a second source communicate with at least two of the N plane-like metal layers. A first gate is arranged between the first source and the first drain. A second gate is arranged between the first drain and the second source. The first and second gates define alternating first and second regions in the first drain, and wherein the first and second gates are arranged farther apart in the first regions than in the second regions.

Description

200847381 九、發明說明： 【發明所屬之技術領域】 本發明涉及積體電路’尤其係涉及積體電路和積體電路的互查 結構。 、 ^ 【先前技術】 功率積體電路（ICs)或功率ICs可用於在多種不同的應用中提 供電力。例如，功率ICs可用於在脈寬調變電路中提供電力:一驅動 ic可用於向功率IC提供輸入電壓和控制信號。因此，驅動ic和功 I/C必須被連接在一起。但是，驅動IC和功率IC可以用不同的汇 =來貝鈀。例如，功率ic可以用金氧半場效電晶體（m〇sfet) ^ 3動IC可使用鮮IC技術。因此，功率 裝可能造成問題。 ^ 一般來說，積體電路（1C)被設計有焊盤，這4b 外部連接。IC -織安置在織上，簡裝可^ 路連接到其他電子元件的引腳。封裝的⑽树科、、'、电200847381 IX. Description of the Invention: [Technical Field] The present invention relates to an integrated circuit', and particularly relates to an inter-check structure of an integrated circuit and an integrated circuit. , ^ [Prior Art] Power integrated circuits (ICs) or power ICs can be used to provide power in a variety of different applications. For example, power ICs can be used to provide power in a pulse width modulation circuit: a drive ic can be used to provide input voltage and control signals to the power IC. Therefore, the drive ic and the work I/C must be connected together. However, the driver IC and power IC can be used with different sinks. For example, the power ic can be used with a gold oxide half field effect transistor (m〇sfet) ^ 3 moving IC can use fresh IC technology. Therefore, power packs can cause problems. ^ In general, the integrated circuit (1C) is designed with pads, which are 4b external connections. The IC-weaving is placed on the weave, and the simple connector can be connected to the pins of other electronic components. Packaged (10) tree branch, ', electric

線的結合電阻增加使得IC的功率耗散。因此，當IC 連接的焊盤時，烊線不能是一種可接受的方法。士里而要 ;:置連 導線及/或軌跡也具有高到不能接受地寄生==且求大里連接的ic， 式互===在電二和/， 最高的。在處理之後，左曰H 们曰曰片製造多個1c是效率 定的1C尺寸，晶片可“固;量白被封裝。對於指 尺寸可幫助減小1C的整體尺寸。铁 ' 件在各=的各個電晶體的 1C數量以降低IC的成本。，、、、允序在母個晶片上製作更多的 5 200847381 【發明内容】 《欲解決之技術問題》 一種積體電路包括N個板狀金屬層，其中N是大於1的整數。 一第一板狀金屬層包括分別與N個板狀金屬層通信的Μ個接觸點部 分，其中Μ是大於1的整數。第一板狀金屬層和ν個板狀金屬層位於 分開的平面中。一第一源極、一第一汲極和一第二源極中的至少兩個 與I個板狀金屬層中的至少兩個通信。一第一閘極被配置在第一源極 和第二汲極之間。一第二閘極被配置在第一汲極和第二源極之間^ 一和，二閘極在第一汲極中限定交替第一和第二區域。第一和第二 極在第一區域中被配置在比第二區域更遠的距離。 《解決問題之技術手段》 特欲中，一井區基板接觸點被配置在第一區域中。R個與 =士小於7的整數。積體電路包括複數個電晶體。電晶體g括^^ 电曰曰體。R個井區基板接觸與各自R個電晶體相關聯。 極和第二^=。置在第二源 第三閘極在第三區域中被配μ比第:區域di:區，第 ^金屬層條分^ n個板 點部分中的-第三接觸點部分被1C'基二随伸的翼。Μ *Μ之間。μ個接觸點部分ΐ的贮Γί 2 —積體電路所;-施接-:心^ 6 200847381 ;中:一Ic提供-第-電壓電勢’Μ個接觸點部 接觸點部分中一的第。二f功率1C提供一第二電壓電勢，並且“個 -種系統包括^部分接收功率IC的輸出電壓。 該導線架包括與M 電路’進—步地包括—雜架（leadframe) ’ 路和分中的至少兩個聽的傳輸線。積體電 無接腳（QFN)封裝。'匕裝。導線架和積體電路實施一四邊扁平 個接觸點進一步地包括一第一傳輸線’其與μ 中的第三接觸；部以;，通；。一第三傳輸線，與卿接觸點部分 J了傳輸線祕1-電壓電勢，並且第三傳輸線提供-第二電壓電 重用於提供積體電路的方法，包括··提供N個板狀金屬層， 入於1的整數；提供一第一板狀金屬層，其包括分別與N個 板狀孟屬層通_ Μ健_部分，其巾M是大於丨的整數；將第 一板狀金屬層和N個板狀金屬層配置在分開的平面中；提供一第一源 極、-第-祕和-第二源極；將第—祕、第—酿和第二源極中' 的至少兩個配置成與N個板狀金屬層中的至少兩個通信；將一第一閘 ，配置在第一源極和第一汲極之間；將一第二閘極配置在第一汲極和 第二源極之間；利用第一和第二閘極在第一汲極中限定交替第一和第 一區域，以及將第一和第二閘極在第一區域中配置比在第二區 遠的距離。 一The increased combined resistance of the lines causes the power dissipation of the IC. Therefore, when the IC is connected to the pad, the twisted wire cannot be an acceptable method. It is necessary to set up the wire and/or the trajectory to have an unacceptable parasitic == and to find the ic connected to the large, the mutual === in the electric two and /, the highest. After processing, the left 曰H 曰曰 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 制造 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片The number of 1C of each transistor is to reduce the cost of the IC.,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, a metal layer, wherein N is an integer greater than 1. A first plate metal layer includes a plurality of contact points respectively communicating with the N plate metal layers, wherein Μ is an integer greater than 1. The first slab metal layer and ν plate-shaped metal layers are located in separate planes. At least two of a first source, a first drain and a second source communicate with at least two of the one sheet metal layers. A gate is disposed between the first source and the second drain. A second gate is disposed between the first drain and the second source, and the second gate is in the first drain Defining alternating first and second regions. The first and second poles are disposed in the first region more than the second region Far distance. "Technical means to solve the problem" In particular, the substrate contact point of a well area is arranged in the first area. R and = integers less than 7. The integrated circuit includes a plurality of transistors. g includes ^^ electric 。 body. R well area substrate contacts are associated with respective R transistors. The pole and the second ^= are placed in the second source and the third gate is matched in the third region. : area di: zone, the ^th metal layer is divided into ^n plate point part - the third contact point part is 1C' base two extending wing. Μ *Μ. μ contact point part ΐ storage Γί 2 — integrated circuit; - connection -: heart ^ 6 200847381 ; medium: an Ic provides - the first - voltage potential 'one of the contact points of the contact point part of the first. Two f power 1C provides a second The voltage potential, and "the system" includes the output voltage of the portion of the received power IC. The leadframe includes at least two listening transmission lines that include, in turn, a "lead frame" and a portion of the M circuit. Integrated body without pin (QFN) package. '匕装. The lead frame and the integrated circuit implement a four-sided flat contact point further comprising a first transmission line 'which is in contact with the third of the μ; a portion; a third transmission line, a contact point portion J with a transmission line secret 1 voltage potential, and a third transmission line providing - a second voltage electric weight for providing an integrated circuit method, including · providing N plate-shaped metal layers, An integer of 1; providing a first plate-shaped metal layer comprising a portion of N-plate-like layer, respectively, wherein the towel M is an integer greater than 丨; the first plate-like metal layer and the N The plate-like metal layers are disposed in separate planes; providing a first source, - a first secret, and a second source; and configuring at least two of the first secret, the first brew, and the second source Communicating with at least two of the N plate metal layers; arranging a first gate between the first source and the first drain; and arranging a second gate at the first drain and the second Between the sources; defining alternating first and first regions in the first drain with the first and second gates, and arranging the first and second gates in the first region further than in the second region distance. One

在其他特徵中，邊方法包括將一井區基板接觸點配置在第一區域 中。該方法包括將R個井區基板接觸點配置在第一區域中，其中&是 大於1的整數。R是大於3且小於7的整數。積體電路包括^复數個$ 晶體。電晶體包括PMOS電晶體。R個井區基板接觸點與r個電晶體 中相應的電晶體相關聯。 M 在其他特徵中，該方法包括將一第三閘極配置在第二源極和第二 200847381 二和第三閘第四區域;並且將第 的第三區域。第一和第三區域句括將弟一區域配置在相鄰 將N個板狀金屬層中J少====。該方法包括In other features, the edge method includes disposing a well substrate contact point in the first region. The method includes disposing R well substrate contact points in a first region, wherein & is an integer greater than one. R is an integer greater than 3 and less than 7. The integrated circuit includes a plurality of $ crystals. The transistor includes a PMOS transistor. The R well substrate contact points are associated with corresponding transistors in the r transistors. M. In other features, the method includes disposing a third gate at the second source and the second 200847381 second and third gate fourth regions; and placing the third region. The first and third regional sentences include a region in which the brothers are disposed adjacent to each other. N of the N plate-shaped metal layers is less ====. The method includes

個板狀金屬層配置在分開的平面中。嗲中。该方法包括將N 極以及第一汲極通信的複數個局部互連!第一和第二源 個是橢圓形的。 qIM M個接觸點部分中的至少一 在其他特徵中’ M個接觸點部分 # 一 基部延伸的翼，並且M個接觸點部分中:二ί觸ΪΓ分具 刀被接收在Μ個接觸點部分中的第一 中的—弟二接觸點部 ，觸點部分㈣—和第二接觸部分的翼之間。Μ ^分中的—第三接觸點部分被配置在μ C =狀。Μ個接觸 弟一接觸點部分之間。 接觸2部分中的第一和 K lV/r ^其他特徵中，該方法包括利用該積體雷脱者# =μ個接觸點部分中的第一接觸點部分向解Ic ;利 ί壓個接觸點部分中的第二接觸點部分向電壓電 包墊私勢，以及在Μ個接觸點部分中的第二 力率1c提供一第二The plate metal layers are arranged in separate planes. In the middle. The method includes interconnecting a plurality of N poles and a plurality of first dipoles in communication! The first and second sources are elliptical. At least one of the qIM M contact point portions in the other features 'M contact point portions # a base extended wing, and in the M contact point portions: the two touch contact tool is received at one of the contact points The first of the first two, the contact point (four) - and the wing of the second contact portion. The third contact point portion of the Μ ^ point is arranged in the μ C = shape. One contact is between the younger part of the contact point. In the first and K lV/r ^ other features in the contact 2 portion, the method includes utilizing the first contact point portion of the integrator portion #=μ contact point portion to solve the solution Ic; The second contact point portion in the dot portion provides a second to the voltage pad and the second force rate 1c in the contact portion

的輸出電壓。 弟—接觸點部分處接收功率IC 在其他特徵中，該方法包括提供一上、 固接觸點部分中的至少兩個通信的傳輸、、、:’/亥導線架包括與M 包封。該方法包括利用導線架i積和傳輪線被—成 ^ 封裝。該方法包括：提供f -四邊扁平無 二，第-接觸點部分通信；提供_第二傳 =、’/、Μ個接觸點部 的弟二接觸點部分通信；提供一第二 Μ個接觸點部 ί接=分通“及提供-電部分中的第 ί電ί電中r傳輸線提供-第-辑勢，：=¾ 一種積體電路包括N個板狀金屬層，其中N是大於 ;1的整數。 200847381 一第一板狀金屬層包括分別與N個板狀金屬層中相應的板狀金屬層通 信的Μ個接觸點部分，其中M是大於丨的整數。第一板狀金屬層和 巧個板狀金屬層位於分開的平面中。第一汲極區域一般為矩形。第一、 第二、第三和第四源極區域一般為矩形並且配置在相鄰第一汲極區域 的側邊。一第一汲極區域和第一、第二、第三和第四源極區域盥^^個 ，狀金，層中的至少兩個通信。一第一閘極區域被配置在第一、第二、 苐二和苐四源極區域和第一沒極區域之間。第一、第二、第三和第四 基板接觸點區域被配置在相鄰第一汲極區域的角落。 在其他特徵中，第…第二、第三和第四源極區域的長 ”長度。第…第二、第三和第四源極區域的寬 的寬度大岐第-赌區域喊度的―半弟和相雜區域 他riifj徵極11域—般為矩職她置在相鄰第一 五、弟，、和弟七源極區域和第二汲極區域之間。 ^ 點區域被配置在相鄰第二汲極區域的角落 (MOSFET) ，的每-個之中提供Β個源極接觸點，其中G大 ;及極區域具有面積D並且B個源極接觸點且有面1」整，。弟 積D大於鱗於2*b*a。 恢娜料Φ積A ’並且其中面 他槪巾，她狀金顧巾的至 亡金屬層位於分開辭面中。複數個局部互連”，個板 f四源極區域以及第—沒極區域通信 ^ ^、弟二和 是姻形的。第一、第二、第三 部分中的至少一個 的第-板狀金屬層通信，並且第—没極區===狀金屬層中 =板狀金屬層通信。Μ個接觸點部分中^^^，金屬層中的第 從基部延伸的翼，並且Μ個_ 彳=接^部分具有 接收在Μ個概晴巾㈣，：編^ 9 200847381 觸點部分中的第一和第二Output voltage. - Receiving power IC at the contact point portion In other features, the method includes providing a transmission of at least two communications in an upper and a solid contact portion, :: /H lead frame including and M encapsulation. The method includes encapsulation using a lead frame i product and a transfer line. The method comprises: providing f - quadrilateral flat no, first - contact point partial communication; providing _ second pass =, '/, contact point portion of the second touch point portion communication; providing a second contact point Department 接 = 分 分 分 分 分 分 分 分 分 分 分 分 分 分 分 分 分 分 分 分 分 分 分 分 分 分 分 分 分 分 分 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及200847381 A first slab metal layer includes a contact point portion respectively communicating with a corresponding one of the N slab metal layers, wherein M is an integer greater than 丨. The first slab metal layer and A slab of metal is located in a separate plane. The first drain region is generally rectangular. The first, second, third and fourth source regions are generally rectangular and are disposed on the side of the adjacent first drain region a first drain region and first, second, third, and fourth source regions, at least two of the layers, and a first gate region is disposed at the first , the second, the second and the fourth source region and the first non-polar region. The first, second, third and Four contact points of the substrate is arranged in a corner region adjacent to the first drain region. In other features, the long "... the length of the second, third and fourth source regions. The width of the second, third, and fourth source regions is greater than that of the first-gambling region, and the riifj sign is the same as the domain. One, five, brother, and between the seven source regions and the second bungee region. ^ The dot area is arranged at each corner of the adjacent second drain region (MOSFET), providing one source contact point, where G is large; and the pole region has area D and B source contact points And there is a face 1". The product D is larger than the scale at 2*b*a. The material of the material is Φ A 'and the surface of the 槪 槪 槪 , , , , , , , , , , , , , , , , , , 。 。 。 。 a plurality of local interconnects, the four-source region of the board f and the first-dipole region communication ^^, the second two are the marriage-shaped. The first-plate shape of at least one of the first, second, and third portions The metal layer communicates, and the first-nothing region ===-like metal layer = plate-like metal layer communication. In one contact point portion, ^^^, the metal-layered wing extending from the base, and one _ 彳= The first part of the contact part has the first and second in the contact part of the general wipe (4): edited ^ 9 200847381

分中的一第三接觸點部 =刀一般是“σ’形狀。M 鋪點部分之間。 置在Μ轉觸點部分㈣第Μ 在其他特徵中，積㈣带告 〜 :二=部分向功率Ic ;供==^個接觸點部分中的一 師刀中的-第三接觸點部功^勢，並且M個接 一種系統包括該積體雷二的輪出·。 ^與二個接觸點部分中的至少兩工二導線架’該導線架包 . - Μ 部分中的第二接觸點部分通传。—^傳輸線與Μ個接觸點 第三接觸點部分通信。一電i 個接觸點部分中的 3 = =!：板狀金屬層和N個板狀金屬層配置在^的ΐ J中，t供-般地為矩形的第—祕區域；將—般地為矩形的第一、 罘一、弟二和第四源極區域配置在相鄰第一沒極區域的側邊，1 區域和第-、第二、第三和第四源極區域與㈣板狀金g層中 ，至乂兩個通信；將第一閘極區域配置在第一、第二、第三和第四源 =區域和第—汲極區域之間；以及將第―、第二、第三和第四基板接 觸點區域配置在相鄰第一汲極區域的角落。 ^ 在其他特徵中，第一、第二、第三和第四源極區域的長度具有實 貝上與第一〉及極區域相等的長度。第一、第二、第三和第四源極區域 具有比第一沒極區域的寬度小的寬度。第一、第二、第三和第四源極 200847381 區域的寬度大約是第一汲極區域的寬度的一半。 在其他特徵中，該方法包括提供一般為矩形的第二汲極區域；將 第二汲極區域的一侧配置在相鄰第一源極區域；提供一般為矩形的第 ^、第六和第七源極區域；將第五、第六和第七源極區域配置在相鄰 ，二汲，區域的其他側邊。該方法包括將第二閘極區域配置在第一、 第五、第六和第七源極區域和第二汲極區域之間。該方法包括將第五 區域配置在轉第"汲極區_祕。積體電路包 擴放减半場效電晶體（Μ⑽ΕΤ)電晶體。該方法包括在 'i中玆大源極接觸點， 點具有面積A，ίΓί/面B悔極接觸 置在同在—fN __种較少兩個配 * 2 方=提 極區域通信的多個局部 3及第一沒 ίΐ屬!通信’並且第一汲極區域與ί個中的第一板 屬运通仏。Μ個接觸點部分中的第_ €中的弟一板狀金 '伸的翼，並且Μ健觸鱗分有基部和從 ::第-和第二二==的翼二。Μ個接觸點部分 個接觸點部分中的第-技^ 、 ^供一苐一電壓電 在-接觸二心 在其他特徵中，_括提供—導線架，該軸包括與^ 觸點部分之間。 彳口接觸點部分中的第一和第二接 Μ 勢 電壓 的輪出 11 200847381 至少兩個通㈣傳輸線。該方法包括將積體電路和 一四邊一成形材料中。該方法包括利用導線架和積體電路實施 Μ個接觸點裝。該方法包括：提供—第—傳輸線與 接_^分通信；提供—第二傳輸線與M個 部及ί供一電容與第二傳輸線和第 線提供_第二電傳輸線祕一弟一電壓電勢，並且第三傳輸 第體Λ路包括1^個板狀金屬層，其中Ν是大於1的整數。 其中Μ是別^她狀金屬層通信的職接觸點部分， 的平面中。第一、、及反狀金屬層和n個板狀金屬層位於分開 具有對稱形狀。域的第-形狀。第二汲極區域 極區域、第二閘域m極區域配置在相鄰於第一間 屬層中至少兩域、弟一沒極區域和第二汲極區域與Ν個板狀金 漸成錐ΐ他第 (Μ〇δΡΒΤΓΪθΪί^ 邊形。沐域疋橢_。對稱形狀是多邊形。對稱形狀是六 在其他特徵中，Μ個板狀金屬層中的 0 200847381 部分中在的和第二接觸點部分的置之間。A third contact point in the subsection = the knives are generally "σ" shape. Between the M punctuation parts. Placed in the 触点 触点 contact part (4) Μ 其他 In other features, the product (4) is 〜 ~ : 2 = partial Power Ic; for the ==^ contact point portion of the -the third contact point part of the tool, and M one system including the integrated body of the second round of the wheel. ^ and two contacts At least two of the two lead frames in the point portion 'the lead frame package. - The second contact point portion of the Μ portion is transmitted. - The transmission line communicates with the third contact point portion of the contact point. One electrical contact point 3 = =! in the section: the plate-like metal layer and the N plate-like metal layers are arranged in the ΐ J, t is generally the rectangular first-secret region; the first is generally rectangular The first, second and fourth source regions are arranged on the side of the adjacent first infinite region, the first region and the first, second, third and fourth source regions and (iv) the plate-shaped gold g layer. For the two communications; arranging the first gate region between the first, second, third, and fourth source=regions and the first-thole region; and the first, second, third, and The four substrate contact point regions are disposed at corners of adjacent first drain regions. ^ In other features, the lengths of the first, second, third, and fourth source regions have a first and a second region Equal lengths. The first, second, third, and fourth source regions have a width smaller than a width of the first non-polar region. The widths of the first, second, third, and fourth source 200847381 regions are approximately In other features, the method includes providing a generally rectangular second drain region; disposing one side of the second drain region in the adjacent first source region; providing a general The second, sixth, and seventh source regions of the rectangle; the fifth, sixth, and seventh source regions are disposed adjacent to each other, the other sides of the region. The method includes the second gate region The method is disposed between the first, fifth, sixth, and seventh source regions and the second drain region. The method includes configuring the fifth region to be in the "bath" region. Halving the field effect transistor (Μ(10)ΕΤ) transistor. This method is included in 'i The source contact point, the point has the area A, ίΓί/face B repentance contact is placed in the same -fN __ kind less two match * 2 side = the part of the regional communication 3 and the first no ΐ ! 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信 通信Divided into base and from:: - and second two == wing two. One contact point part of the contact point part of the first - technique ^, ^ for a voltage of one in the contact two core in other features The _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The method includes integrating the integrated circuit and a four-sided shaped material. The method includes performing one contact point mounting using a lead frame and an integrated circuit. The method includes: providing - a transmission line and a connection communication; providing - a second transmission line and M parts and providing a capacitance and a second transmission line and a line providing a second voltage transmission line And the third transmission body circuit includes 1^ plate metal layers, wherein Ν is an integer greater than 1. Among them, the Μ is in the plane of the contact point of the metal-layer communication. The first, and the reverse metal layer and the n plate metal layers are separated to have a symmetrical shape. The first shape of the field. The second drain region polar region and the second gate region m pole region are disposed adjacent to at least two domains in the first sub-layer, the first-polar region and the second drain region, and one plate-shaped gold tapered cone ΐ 第 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( Part of the placement between.

觸點部分巾㈣—和第 2的^接T部分被岐在M ，觸點部分中的第二接觸點部分 &弟-電屋電勢州固 個接觸二點部分中的第三接觸點部g ，並且Μ 括與Μ個兩二_，該導線架包 S形材•战。料私躺 nmLt^S'm u 壓;J==:f三傳輸線通』:第Ξ 中N ;=4路的：= 狀八l ^ I數’提供—第—板狀金屬層，其包括分別心個板 通信的M個接觸點部分，其巾Μ是大於i的整 =至屬層和N個板狀金屬層配置在分賴平面七提供具有水 垂直的中^少-條對獅狀的第—汲祕域；提供具有g繞 5區ϊίίΐίί·的第—閘極區域；提供具有對稱形狀第二極區 ί二具ΐ圍繞弟二汲極區域的第一形狀的第二閘極區域；利用連 接區域連接和第二閘極區域；將第—源極區域配置在相鄰於第一 閘極區域、^二閘麵域和連接區域的—侧；以及將第二源極區域配 置在，鄰的第-閘極區域、第二閘極區域和連接區域的側邊的一側， 中弟源極Q域、弟一源極區域、第一沒極區域和第二汲極區域與 Ν個板狀金屬層中的至少兩個通信。 在其他特徵中，對稱形狀隨著與對稱形狀的中心距離增大而逐漸 13 200847381 成錐形。邊方法包括將第一和第二基^一… 赌嶋錢伟編細伟ΐίΐ 置在同在Μ她_射_、兩個配 中。該方法包括提供與第金屬f配置在分開的平面 通信的複數個局部互連。以個接觸點、部= 極區域 有基部和從基部延伸的翼，並^ 接觸點部分具 被接收在μ個接觸點部分中的第 接接觸點部分 2點部分中的第，二接的翼之間。難 個接觸點部分中的第三接鎇戥卹八L形狀，並且其中Μ -和第二接觸點部分之間。…刀I己Μ個接觸點部分中的第 在/、他特徵中，该方法包括利用該藉辦雷炊途^ 個，觸點部分中的第一接觸點部分向功^ Ic 1C，·利用The contact portion towel (4) - and the second portion of the T portion are clamped at M, the second contact point portion of the contact portion is the third contact point portion of the second contact portion of the state g, and Μ Μ 两 两 , , , 该 , , , , , , , , , , , , , The material is privately laid nmLt^S'm u pressure; J==:f three transmission line through: Ξ Ξ N; = 4 way: = 八八 l ^ I number 'provide - the first - sheet metal layer, which includes The M contact points of the heart-to-board communication are respectively larger than the i-to-genus layer and the N-plate metal layers are arranged in the plane 7 to provide a water-vertical medium-to-strip-to-lion-like shape. a first gate region having a g-circle 5 region ; ΐ ΐ ΐ ; ;; a second gate region having a first shape having a symmetrical shape and a second polar region surrounding the second dipole region Connecting the second source region with the connection region and the second gate region; arranging the first source region adjacent to the first gate region, the second gate region, and the connection region; and arranging the second source region , the adjacent first-gate region, the second gate region, and the side of the side of the connection region, the source source Q domain, the brother-source region, the first gate region, and the second gate region At least two of the plate metal layers communicate. In other features, the symmetrical shape tapers as the center distance from the symmetrical shape increases. The side method includes placing the first and second bases... gambling 嶋 伟 编 编 ΐ ΐ ΐ ΐ ΐ ΐ ΐ _ _ 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 The method includes providing a plurality of local interconnects in communication with the first metal f in separate planes. a contact point, a portion=pole region having a base portion and a wing extending from the base portion, and a contact point portion having a second and second wing portions of the second contact portion of the first contact point portion received in the μ contact point portion between. It is difficult to have a third contact in the contact point portion of the eight-L shape, and between the Μ- and the second contact point portion. ...the knife I has the first part of the contact point part, and the method includes the use of the borrowed Thunder way, and the first contact point part of the contact part is used for the work Ic 1C,

=電勢;並且在^提供-第二 ，輸出電壓。該方法包括提供 =處接收功率IC ϊγϊ至少兩個通信的傳輪線。該方法包括固接觸點 σ ，、中第一傳輸線提供一第一電壓電勢，in、、和第二傳輪線通 二電壓電勢。 电植电勢亚且弟三傳輪線提供一第 -種積體電路包_個板狀金屬層’其中N是大於丨的餐數。 200847381 板狀金顧包括分_ N做狀金屬層通信的M健觸點部分， ^平數。第一板狀金屬層和N個板狀金屬層位於分開 sms二沒極區域-般為矩形。第―、第二和第三源極 弟：獅域被配置在第一和第二沒極區域的第- 置第在二二 :域;==&置在;鄰第二汲極區域的第四側。‘ 、、及炼卩代夕„ 一 fz弟―、弟四和弟五源極區域和第一和第二 中的至少兩個糾個板狀金屬層中;：少通;四和弟五源極區域 第一和第二沒極 八一弟^弟五源極區域具有大於或等於 比第第第原極區域的寬度具有 =極=;極度接的觸二 規，^ 在其他特徵中，此極區域包括源極接觸點。 第三源極區域被配置在第丄歹;^且^域和第一、第二和 中的至少一列的沒極區域共用^^^= 員外的列 間。M個接觸點部分中的第一和第二接觸點部翼 15 200847381 亚且其中]V[個接觸立κ % 部分中的^和第二接觸觸點部分被配置在Μ個接觸點 在/、他特徵中，藉興 一接觸點部分向功率 ' 路^施功率1C，Μ個接觸點部分中 第二接觸點部分向功率Ic提、^電勢，Μ個接觸點部分中的 分中的^三接觸點部分接收並錢個接觸點部 括與Μ個^===進—步地包括-導線架，該導線架包 u形，。‘二信電 部分中的第二接觸點部分通ρ。傳輸線與Μ個接觸點 第三接觸點部分通信。一“弟輸線與Μ個接觸點部分中的 傳輸線提供第-賴電勢5日、輸線和第三傳輸線通信。第二 -種用於提供積妒带败沾弟：傳輸線提供-第二電壓電勢。 其中N是大於丨的整數^j =··提供N她狀金屬層， - 丄 弟—和弟二源極區域配置在第一和第络 ^及極區域之間；將第—和第 l妨/和弟 ，。第-和第二沒極區域和第—、if :占口在二 域中的至少兩個與_板狀金屬層中的至少=‘四和弟五源極區 在其他特徵中，第一、第二和第三源極區域的長度實質上與第一 200847381 汲極區域的長度相等。第四和第五源極區域的長度具有大於或等於第 二和第二汲極區域的長度。第一、第二和第三源極區域的寬度具有比 第^汲極區域的寬度小。第―、第二和第三雜區域的寬度大約是第 -沒極區域的寬度的-半。第四和第五源極區域是從其側邊被驅動 的H第二祕接_的尺寸具有比最核極接繼尺寸大。沒 點具有規^形狀和不規則形狀之—。汲極接觸點為方形、矩形 σ子形之一。第一、第二和第三源極區域包括源極接觸點。= potential; and at ^ provide - second, the output voltage. The method includes providing a pass line at which the received power IC ϊ ϊ ϊ at least two communications. The method includes a solid contact point σ, wherein the first transmission line provides a first voltage potential, the in, and the second transmission line pass two voltage potentials. The electro-planting potential sub- and the three-passenger wheel line provide a first-integrated circuit package _ a plate-like metal layer where N is the number of meals larger than 丨. 200847381 The slab-shaped gold gull consists of the M-join contact part of the _N-shaped metal layer communication, ^ flat number. The first plate metal layer and the N plate metal layers are generally rectangular in a region separated by two sms. The first, second, and third source brothers: the lion domain is placed in the first and second immersive regions - the second in the second: domain; == &; placed in; adjacent to the second bungee region The fourth side. ',, and 卩 卩 „ 一 一 f 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一The first and second poles of the polar region have a greater than or equal to the width of the first polar region and have a polarity== extreme contact, ^ in other features, The polar region includes a source contact point. The third source region is disposed between the first and second regions, and the non-polar region of at least one of the first and second sums is shared between the columns outside the ^^^= member. The first and second contact point flaps 15 in the contact point portion, and wherein the V and the second contact contact portion are disposed at the contact point at /, In the feature, the power of the touch point is applied to the power section 1C, and the second contact point portion of the contact point portion of the contact point is raised to the power Ic, and the potential of the contact point is the contact of the contact point. The point part receives and the money contact points are included and the ^^== step-by-step includes a lead frame, the lead frame is u-shaped, and the 'two-signal part The second contact point is partially connected to ρ. The transmission line is in communication with the third contact point of the contact point. The transmission line in the "different line and the contact point portion provides the first-difference potential 5th, the transmission line and the third transmission line communication . The second type is used to provide the accumulation of the smashed dip: the transmission line provides - the second voltage potential. Where N is an integer greater than 丨^j =·· provides N her metal layer, - 丄弟- and brother 2 source regions are arranged between the first and the first ^ and the polar regions; the first and the third /And brother,. The first and second non-polar regions and the first, if: account at least two of the two domains and the _ plate-like metal layer at least = 'four and five source regions in other features, first, The lengths of the second and third source regions are substantially equal to the length of the first 200847381 drain region. The lengths of the fourth and fifth source regions have lengths greater than or equal to the second and second drain regions. The widths of the first, second and third source regions are smaller than the width of the first drain region. The width of the first, second and third miscellaneous regions is approximately - half of the width of the first - non-polar region. The fourth and fifth source regions are driven from their sides, and the size of the second second interface is larger than the most nuclear terminal successor size. There are no points with regular shapes and irregular shapes. The bungee contact point is one of a square, rectangular σ subshape. The first, second, and third source regions include source contact points.

一其他特徵中，該方法包括··將第一和第二汲極區域和第-、第 二祕區域配置在第—列中；並且提供N個額外的列，盆中N ’ 少一列的沒極區域共用第四和第五源極區域二。 括將Ν個板狀金屬層中的至少兩個配 的二; 觸點部分中的第—和第 ^ 形的。Μ個接 ;，接觸點部分中的第三接觸接翼’並 的弟-和第二接觸點部分的翼之間。Μϋ倾觸點部分中 接觸點部分一般是“c”形狀，並且 :、Μ中的第一和第二 ，點部分被配置在Μ個接觸點部分中、吩中的第三接觸 、—在其他特徵中，積體電路實施功1-接觸點部分之間。 接觸點部分向功率IC提供一第一 個接觸點部分中的第 第二接觸點部分向功率IC提供 Μ個接觸點部分中的 ^中的第三接槪部分接收功率.’並且Μ個接觸點部 2^_架包括賴個接^=中出電塵。該方法包括提供-導 路和傳輸線被-成形材料所包封。義通信的傳輸線。 邊扁平無接腳（QFN)封裝。 、泠線未和積體電路實施一四 在其他特徵中，該方法包括· > ^的第一接觸點部一第將傳二連接龍個接觸 中的―分;將-第三傳輪 17 200847381 二撕難傳輸線。第二 Θ 1、包勢 第三傳輸線提供第二電壓電勢。 _ /1、，提供的詳細描述可“清楚本發日月的其他應用領域。應當理 和具體例子儘管表明了本發明的錢實施例，但僅意圖用 於_目的，而不是要限制本發_範圍。 【實施方式】 使處以v下對優先實施例的描述只是範例性的，絕不意圖限制本發明、 - Ϊ使用。出於清晰目的，在附圖中將使用相同的標號來標識類 W ^見一考目1A ’ 一功率IC 1〇包括第一和第二功率電晶體12和 :巧顯示為第-和第二功率電晶體12和14，但也可用於額外的 =曰^“實施功率1C。在—種實施方式中，功率IC 1G被用於脈寬調 、交（Plus Width Modulation)電路中。第一電晶體12的源極連接到第 ^電晶體14的汲極。電源電壓Vdd連接到第一電晶體12的沒極。參 考電勢ν'此範圍被連接到第二電晶體M的源極。在第一電晶體12 的源極和第一電晶體14的汲極之間取得輸出電壓Vx。電晶體12是 NMOS電晶體以及電晶體η是nm〇s電晶體，但也可以使用盆他類 型的電晶體。 a ' 現在簽考圖1B，功率1C 20另一結構包括第一和第二功率電晶 體22和24。雖然顯示為第一和第二功率電晶體22和24，但也可以用 額外的電晶體來實施功率1C。第一電晶體22的汲極連接到第二電晶 體24的沒極。電源電壓Vdd連接到第一電晶體22的源極。參考電g Vss此範圍被連接到弟二電晶體24的源極。電晶體22是pm〇S電晶 體以及電晶體24是NMOS電晶體，但也可以制其賴獅電晶^ 在第一和第二電晶體22和24的沒極之間取得輸出電壓％。 現在參考圖2，功率電晶體10和20可連接到驅動Ι(〕Χ。用於功 1C 10及/或20的技術可能不同於用於驅動IC 3〇的技術。例如，功 1C 10及/或20可利用金氧半場效電晶體（M〇SFE丁）技術來實施，反 18 200847381 ，的1C技術。雖然公開了金氧半場效電晶體 個元件26,該—個或多個元件可包括串聯ί感 瓶-’顯卿金屬層13G的範例性平面圖。雖然 顯不為與弟-和弟二功率電晶體的連接， ooT^rsfs^ ° ^ ^ 3(Π、130_2和130-3疋橢圓形的。在此實施方式中 分130-1連接到Vss’第二細點部分13〇_2連接 觸: 部分ί連制Vdd。第四接觸點部分·_4與諸‘閘 類的控制信號相關聯。經由額外的接觸點部分13〇_ 的° :J分絕緣材料m被·在接觸點部分⑽之間以電氣以= 現在爹考圖4A ’進-步地詳細顯示出與圖丨 〇的-種範例性實施方式。第一電晶體12包括一汲極/2應 =-閘極76。第二電晶體14包括—沒極82、一祕84和極 黾晶體12和14是NM0S電晶體，但也可使用立他雷日。 ，了第-和第二功率電晶體12和===== 只加功率1C 10，下文將對此進行描述。第—電晶體^ 曰曰，來 590連接5局部互連98:鱗互連98提供諸如標準線之類22 。14裏使用的術語“過孔，，是指將電阻最小化到期望水準所二 目的過孔。第二電晶體14的閘極88通過過孔94連^= 第一電晶體12的源極74和第二電晶體14的沒極82分別、虽π & 部互連98和過孔励和1〇4連接到-板狀金屬層m 過局 語“板狀金屬層，，是指堅固互連平面，而不是像標準線那= ^連（例如標準架線〕的情況那樣只在單做向（例如^微，局 流動。 a y〕上 19 200847381 到點ίί觀 觸織點A流 於矩形或方形或者具有非相同相同的形狀減^ 狀金屬m1^及極72通過局部互連98和過孔114連接到板 孔120 弟一板狀部分124_2。源極84通過局部互連98和過 =第屬層124的一第一板狀部分购。板狀金屬層 板狀部分以·1和124·2互相被電氣絕緣的。 員卞孟屬層130優先地厚於板狀金屬層兇、11〇和124。可以竞 或多個絕緣層134提供例如金屬層11G、124和13〇之間的 在電氣隔離層110、124和130。頂部金屬層130限定互 Γ 觸點部分 13(M、13G_2、13G_3、13G_4、···以及 130-N。 狀部八ιίίΐ1^1通過過孔14G連接到板狀金屬層124的第二板 1 -。弟一接觸點部分130_2通過過孔144連接到板狀金屬層 一^弟二接觸點部分跡3通過過孔150絲到板狀金屬層124的第 =狀部分124_1。第四接觸點部分13〇_4通過過孔16〇連接到金屬互 。板狀金屬層110和124提供堅固平面互連，而互連98提供微 弱/局部互連。 来本領域的技術人員可以意識到，功率IC2〇對應於圖圯有一些 ^似的佈局顯示在圖4A。現在參考圖4B，電晶體22包括-閘極162、 :源極163和一汲極164。電晶體24包括一閘極166、一汲極167和 帝，極168。在一種實施方式中，電晶體22和24分別是pM〇^NM〇s 包晶體’但也可使用其他電晶體類型。源極163通過過孔114連接到 板狀金屬層124的第二板狀部份124-2、汲極164和167分別通過過孔 100和104連接到板狀金屬層110、源極168通過過孔120連接到板狀 20 200847381 金屬層124的第一板狀部份124_1。 雖然圖4A和4B中的板狀金屬層124是共用的，本領域的技術 人員將意識到可以共用的是板狀金屬層11〇而不是板狀金屬層124。 ，外’雖然第一電晶體12的源極74和第二電晶體14的沒極82被顯 示為連接到圖4A (以及圖4B中的汲極164和167)，但也有其他可能 ίΐίί1的連接實财式。神1c可顧焊球和崎膜、例如各向異 十黏σ诏之類的黏合劑及/或任何其他適當的附接方法連接到其他電In one other feature, the method includes: arranging the first and second drain regions and the first and second secret regions in the first column; and providing N additional columns, wherein the N' is less than one column in the basin The polar regions share the fourth and fifth source regions two. Included in at least two of the slab-shaped metal layers; the first and the second in the contact portion. One contact; the third contact in the contact portion is between the brother-and the wing of the second contact portion. The contact point portion of the slanted contact portion is generally "c" shaped, and:, the first and second of the Μ, the point portion is disposed in the contact point portion, the third contact in the phenule, - in other In the feature, the integrated circuit performs between the work 1 - contact point portions. The contact point portion provides a second contact point portion of a first contact point portion to the power IC to the power IC to provide a third interface portion of the contact point portion of the power IC to receive power. 'and a contact point The 2^_ frame includes a battery that is connected to the power supply. The method includes providing a guide and a transmission line encased by a forming material. The communication line of the communication. Side flat, pinless (QFN) package. , the 泠 line is not integrated with the integrated circuit. In other features, the method includes the first contact point of the > ^ 200847381 Two tearing transmission lines. Second Θ 1. The third potential transmission line provides a second voltage potential. _ / 1, the detailed description provided can be "clear of the other fields of application of the present day. It should be understood that the specific examples, although indicating the embodiment of the invention, are intended for purposes only, and are not intended to limit the present invention. The description of the preferred embodiments is merely exemplary and is not intended to limit the invention, and is used for the sake of clarity. For the sake of clarity, the same reference numerals will be used in the drawings to identify the classes. W ^ see an exam 1A ' A power IC 1 〇 includes first and second power transistors 12 and: is shown as first and second power transistors 12 and 14, but can also be used for additional = 曰 ^ " Implement power 1C. In one embodiment, the power IC 1G is used in a Pulse Width Modulation circuit. The source of the first transistor 12 is connected to the drain of the ^ transistor 14. The power supply voltage Vdd is connected to the pole of the first transistor 12. The reference potential ν' is connected to the source of the second transistor M. An output voltage Vx is taken between the source of the first transistor 12 and the drain of the first transistor 14. The transistor 12 is an NMOS transistor and the transistor η is an nm〇s transistor, but a pot-type transistor can also be used. a ' Now with reference to Figure 1B, another configuration of power 1C 20 includes first and second power transistors 22 and 24. Although shown as first and second power transistors 22 and 24, power 1C can also be implemented with an additional transistor. The drain of the first transistor 22 is connected to the pole of the second transistor 24. The power supply voltage Vdd is connected to the source of the first transistor 22. This range of reference power g Vss is connected to the source of the second transistor 24. The transistor 22 is a pm〇S electromorph and the transistor 24 is an NMOS transistor, but it is also possible to make a ray crystal to obtain an output voltage % between the first and second transistors 22 and 24. Referring now to Figure 2, power transistors 10 and 20 can be connected to a drive Ι. The technique for work 1C 10 and/or 20 may be different from the technique used to drive IC 3 。. For example, work 1C 10 and / Or 20 may be implemented using a gold oxide half field effect transistor (M〇SFE) technology, 1C technology of 18 200847381. Although a gold oxide half field effect transistor element 26 is disclosed, the one or more components may include Tandem sensible bottle - 'Improved metal layer 13G's exemplary plan. Although not connected to the brother-and brother's two power transistors, ooT^rsfs^ ° ^ ^ 3 (Π, 130_2 and 130-3疋 ellipse In this embodiment, the sub-130-1 is connected to the Vss' second fine-point portion 13〇_2 connection contact: the part is connected to Vdd. The fourth contact point portion·_4 is associated with the control signals of the 'gates' Through the additional contact point portion 13〇_°: J is the insulation material m being electrically connected between the contact point portions (10) = now in Fig. 4A 'step-by-step detailed display with the figure- An exemplary embodiment. The first transistor 12 includes a drain 2 / 2 = a gate 76. The second transistor 14 includes - a pole 82, a secret 8 4 and the crucible crystals 12 and 14 are NM0S transistors, but it is also possible to use Ritalie. The first and second power transistors 12 and ===== only power 1C 10, which will be described below Description: TEM- 曰曰, 590 CONNECT 5 Local Interconnect 98: Scale interconnect 98 provides a term such as a standard line. The term "via" is used to minimize resistance to a desired level. The via of the second transistor 14 is connected through the via 94 to the source 74 of the first transistor 12 and the gate 82 of the second transistor 14, respectively, although the π & 98 and via excitation and 1〇4 are connected to the -plate metal layer m. The phrase "plate metal layer" refers to a solid interconnect plane, rather than the case of a standard line = ^ (eg standard wire) That is only in the direction of the single (for example, ^ micro, local flow. ay) on 19 200847381 to point ί ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ Interconnect 98 and via 114 are connected to plate aperture 120, a plate portion 124_2. Source 84 passes through local interconnect 98 and a first plate of over = first layer 124 The slab-shaped metal layer plate-like parts are electrically insulated from each other by ·1 and 124·2. The 卞 卞 属 130 layer 130 is preferentially thicker than the slab-shaped metal layer, 11 〇 and 124. It can compete or multiple insulation Layer 134 provides, for example, electrical isolation layers 110, 124, and 130 between metal layers 11G, 124, and 13 。. Top metal layer 130 defines mutual contact portions 13 (M, 13G_2, 13G_3, 13G_4, ..., and 130) -N. The portion ι ί ΐ 1 ^ 1 is connected to the second plate 1 - of the slab metal layer 124 through the via 14G. The contact point portion 130_2 is connected to the plate-like metal layer through the via hole 144. The second contact point portion trace 3 is passed through the via hole 150 to the first portion 124_1 of the plate-like metal layer 124. The fourth contact point portion 13〇_4 is connected to the metal through the via hole 16〇. The plate metal layers 110 and 124 provide a solid planar interconnect while the interconnect 98 provides a weak/local interconnect. Those skilled in the art will appreciate that power IC2(R) corresponding to the figure has some similar layouts shown in Figure 4A. Referring now to FIG. 4B, transistor 22 includes a gate 162, a source 163, and a drain 164. The transistor 24 includes a gate 166, a drain 167, and a pole 168. In one embodiment, transistors 22 and 24 are respectively pM〇^NM〇s encapsulated crystals' but other transistor types may also be used. The source 163 is connected to the second plate portion 124-2 of the plate metal layer 124 through the via 114, and the drain electrodes 164 and 167 are respectively connected to the plate metal layer 110 through the via holes 100 and 104, and the source 168 passes through The hole 120 is connected to the first plate portion 124_1 of the plate-like 20 200847381 metal layer 124. Although the plate-like metal layers 124 in Figures 4A and 4B are common, those skilled in the art will appreciate that a plate-like metal layer 11 can be used instead of the plate-like metal layer 124. , although 'the source 74 of the first transistor 12 and the pole 82 of the second transistor 14 are shown as being connected to FIG. 4A (and the drains 164 and 167 in FIG. 4B), there are other connections that may be ίΐίί1 Real money. God 1c can connect to other batteries with the help of solder balls and smears, such as adhesives such as inotropic viscous 及 and/or any other suitable attachment method.

IC ^見在I考® 4C’圖1A和4A對應的佈局提供了額外的板狀金屬 二為第—和第二功率電晶體，但—般也可使用額外的 ιΙΓι體功率1C。板狀金屬層124不再被共用。第一接觸點部分 72連接到板狀金屬層⑺。過孔140將沒極72連接 至Ϊ ^。源極％和沒極82分別通過過孔議和104連接 4Β對應的佈曰局添加技術人貝將會意識到，也可向與圖⑴和 12 i. 二功率電曰，14二-其中母一個具有源極S和沒極D。第 m p羊顯不為包料個電㈣lm、m_2、以及 層s和絲D。嫌金麟11G和板狀金屬 部互連。在圖5A所示ί實施票準線之類的微弱局 體，但也可使用其他電晶體類^⑽體12和14是励S電晶IC ^ See the layout of Figure 1A and 4A in Figure 1A and 4A provides additional plate-like metal. The second and second power transistors, but generally can also use an additional ι ΙΓ body power 1C. The plate metal layer 124 is no longer shared. The first contact point portion 72 is connected to the plate-like metal layer (7). The via 140 connects the poleless 72 to Ϊ ^. The source % and the immersion 82 are respectively connected through the via hole and 104. The corresponding 的 添加 添加 添加 添加 添加 将会 将会 将会 将会 将会 将会 将会 将会 将会 将会 将会 将会 将会 将会 将会 将会 将会 将会 将会 将会 将会 将会 将会 将会 将会 将会 将会 将会One has a source S and a poleless D. The m p sheep is not a packet of electricity (four) lm, m_2, and layer s and wire D. The suspected Jinlin 11G is interconnected with the plate metal. In Fig. 5A, the weak body such as the ticket line is implemented, but other transistor types can be used. (10) The bodies 12 and 14 are excited S-electrons.

14 ° M =到板狀金顧124料二^ 頂部板狀金朗13G的第—接觸點部分13(m連接到第二板狀部 21 200847381 t124·2。頂部板狀金屬層130的第二接觸點部分13〇_2連接到板狀全 層13G的第三魏畴分⑽錢接到第一板 f2 Γ00%。板狀金屬層110覆蓋在下面的電晶體 12 和 14 的大約 80% 一 1〇〇%。 186-卜tf、考圖5Β ’第一功率電晶體22被示為包括多個電晶體 祕雷^ w :以及186·Ρ ’其中每一個具有源極S和沒極D。第二 Ϊ皮示為包括多個電晶體购、船、…以及·R， 有曰源極s和沒極D。在圖5Β所示的實施方式中，第一 os電晶體，第二功率電晶體24是麗0s電晶體， ί雷了電晶體類型。第—功率電晶體22 極d和第二功 極1連接到板狀金屬層124。第一功率電晶體22的 連接到板狀金屬層110的第一板狀部分11(M。 一板狀α卩分110-1和HQ。是被電氣隔離的。 頂部=金屬層酬的第一接觸點部分刪連接到板狀金屬層 130-2、查二3部分蔵110-2。頂部板狀金屬層130的第二接觸點部分 、蛊垃5U “丨入^狀金屬層124。板狀金屬層130的第三接觸點部分13αθ 連接到板狀金屬層110的第一板狀部分11(Μ。 m 茶考圖6Α，其顯示為頂部金屬層130的優先實施例的平面 =ϋ己置在頂部板狀金屬層130中的一第一接觸點部分200包括從基 出一複數個翼202。在一種實施方式中，第一接觸點部分 dd相關聯，並且翼202在垂直方向上從一基部204延伸。 頂部板狀金屬層130中的第二接觸點部分21()也包括從一基部 延，出複數個翼212。在一種實施方式中，第二接觸點部分別 與vdd或Vss相關聯，並且翼212在垂直方向上從基部214延伸。 9m ^ 〃個或多個第三接觸點部分220位於第一接觸點部分200的翼 接網It接觸點部分21G的翼212之間。在一種實施方式中，第三 …邛为220與vx相關聯，並且第三接觸點部分22〇具有一般圓角 22 200847381 和翼212減小了連接阻抗並增大了熱的散失。額外 積。這裏使ΐ的美i基本覆蓋在下面的電晶體面 邮自磁術面面積“ 施例中在= 二 ，物組合減小連接的阻抗並且增大了熱的 ϊγ參的考=接f互連結構並進一步減小了14 ° M = to the plate shape of the gold material 124 material 2 ^ the top plate-shaped metal Lang 13G of the first contact point portion 13 (m is connected to the second plate portion 21 200847381 t124 · 2. The top plate metal layer 130 of the second The third Wei domain (10) of the contact point portion 13〇_2 connected to the plate-like full layer 13G is connected to the first plate f2 Γ00%. The plate-like metal layer 110 covers about 80% of the underlying transistors 12 and 14 1〇〇%。 186-卜tf, 考图5Β 'The first power transistor 22 is shown to include a plurality of transistor secrets ^ w : and 186 · Ρ ' each of which has a source S and a pole D. The second suede is shown to include a plurality of transistor purchases, ships, ..., and R, having a source s and a immersion D. In the embodiment shown in FIG. 5A, the first os transistor, the second power The crystal 24 is a NMOS transistor, and the GaN is of a transistor type. The first power transistor 22 pole d and the second power pole 1 are connected to the slab metal layer 124. The first power transistor 22 is connected to the slab metal layer The first plate portion 11 of the 110 (M. a plate-shaped α-portion 110-1 and HQ. is electrically isolated. The top portion of the first contact point of the metal layer is connected to the plate-like metal layer 130-2, check the second part 蔵110-2. The second contact point portion of the top plate-shaped metal layer 130, the 5 5 5U "into the ^-shaped metal layer 124. The third contact point portion 13α θ of the slab-shaped metal layer 130 The first plate-like portion 11 is connected to the plate-like metal layer 110. The plane of the preferred embodiment of the top metal layer 130 is shown as one of the top plate-shaped metal layers 130. The first contact point portion 200 includes a plurality of wings 202 from the base. In one embodiment, the first contact point portion dd is associated and the wings 202 extend from a base portion 204 in a vertical direction. The top plate metal layer 130 The second contact point portion 21() also includes a plurality of wings 212 extending from a base. In one embodiment, the second contact point portions are associated with vdd or Vss, respectively, and the wings 212 are vertically oriented The base portion 214 extends. 9m ^ one or more third contact point portions 220 are located between the wings 212 of the wing contact network It contact point portion 21G of the first contact point portion 200. In one embodiment, the third ... 220 is associated with vx, and the third contact point portion 22 has a generally rounded corner 22 200847381 and Wing 212 reduce the connection impedance and increase the heat loss. The extra product here. The beauty of the ΐ 基本 基本 基本 基本 基本 基本 基本 基本 基本 基本 基本 基本 基本 基本 基本 基本 基本 基本 基本 基本 基本 基本 基本 基本 基本 基本 基本 基本 基本 基本 基本 基本 基本 基本 基本 基本 基本Reducing the impedance of the connection and increasing the thermal ϊ 参 的 = 接 互连 互连 互连 互连 互连 互连 互连 互连 互连 互连 互连 并

TvMxt 如上述圖6A關聯。 X ss 17 Vdd被以交錯的方式配置， 現在參考圖6C，顯示出頂部金屬層的祛 板狀金屬層130的面積大約1/3以非交曰配° 了士所述頂部 每-個。這種實施方式適合於較小以:^义、乂找中的 屬層/3〇二顯示為出頂部板狀金 交錯方式分配給Vx、、二V3 :非 適於當Vss和Vdd連接被开彡__ 局尤其合 率ic的相反-側時。雖然圖6A_6D是結合電晶體m形成於功 但也^“㈣,描述的， 236。互連結構236可^t fr互連= 可用於連接外部元件’例如輪出電路、電容ΐϊ器個電;= 23 200847381 結構。例如，互連結構236可用於將功率iC 運接到圖2中的驅動1C。 /或軌或ΐ積全€屬=2=$侧配置有第二金屬層及 r乐飞详檟屬層250被堆積在電介質層244的相反一 :ί=。過孔，1、2… ϋϊΓ田，膜252被配置在第二金屬層242上。焊球254被 ΐ他電子ΞΓΐ=ΐΓί=ί5。0及/或242的-些部分綱 t屬層130上的真202及/或212相對齊的形狀和 270^ 27： ttk ^ 尺、莫 翼2D具有允許與配置在功率ic 54的全屬# 130上的翼202及域212對齊的形狀和尺寸。半 的至屬層 1屬堆積層250亦包括位於第一板狀接觸點 的/、272之間的-個或卿三 的全not觸點部*280也具有允許與配置在功率1c 54 的金屬層13〇上的弟三板狀接觸點部分22〇對齊的形狀和 金麟制25G還包括提供控制信號互連的—個TvMxt is associated as shown in Figure 6A above. The X ss 17 Vdd is configured in a staggered manner. Referring now to Figure 6C, the area of the slab-shaped metal layer 130 of the top metal layer is shown to be approximately 1/3 of the area of the top of the slab. This embodiment is suitable for smaller ones: 义 乂, 乂 中 的 / / / / / 显示 显示 显示 显示 显示 显示 显示 显示 顶部 顶部 顶部 顶部 顶部 顶部 顶部 顶部 顶部 顶部 顶部 顶部 顶部 顶部 顶部 顶部 顶部 顶部 顶部 顶部 顶部 顶部 顶部 顶部 顶部 顶部 顶部 顶部 顶部The 彡__ board especially coincides with the opposite side of the ic-side. Although FIGS. 6A-6D are formed in conjunction with the transistor m, but also described in (4), 236. The interconnect structure 236 can be used to connect external components such as a turn-off circuit, a capacitor, and the like; = 23 200847381 Structure. For example, interconnect structure 236 can be used to transfer power iC to drive 1C in Figure 2. / or rail or hoard all = 2 = $ side configured with second metal layer and r The detailed germanium layer 250 is deposited on the opposite side of the dielectric layer 244: ί=. vias, 1, 2... ϋϊΓ田, the film 252 is disposed on the second metal layer 242. The solder balls 254 are ΐ ΞΓΐ ΞΓΐ ΐΓ = ΐΓ ΐΓ = ί 5. 0 and / or 242 - some parts of the genus layer 130 on the true 202 and / or 212 aligned shape and 270 ^ 27: ttk ^ 尺, Mo Wing 2D has allowed and configured in the power ic 54 The shape and size of the wings 202 and the field 212 on the entire genus 130 are aligned. The half-to-one layer 1 genus stacking layer 250 also includes the - or 272 of the first plate-shaped contact point. The not contact portion *280 also has a shape that allows alignment with the three-plate contact point portion 22〇 disposed on the metal layer 13〇 of the power 1c 54 and the Jinlin 25G also includes The control signal interconnection - a

部分284。額外接觸點部分284中的—個或多個^閘H 一個範例性實施方式中，堆積層250是通。如5 ^卜电材料，鑛到電介質層上來配置的。本領域的技術人員將合咅Part 284. One or more of the additional contact point portions 284 In one exemplary embodiment, the buildup layer 250 is open. Such as 5 ^ Bu electrical material, the mineral is placed on the dielectric layer to configure. Those skilled in the art will merge

^ ^ί材料和方法°在―個實施例中’堆積層250'具G 卿的平均厚度’但也可朗其他厚度。 田夕3250。可以意識到’這兩個結構基本上互相ϊΐ 重$。,、、、、而，孟屬堆積層25〇可延伸到超出功率汇 130以減小電阻並增大熱的散失。 貝h屬層 24 200847381 現在參考® 9，更詳細顯示出電介質層252。電介質> % f弟-部分260的域264對齊的—組過孔3〇4 〆 = ί 部* 270的基部274對齊的一組過孔3〇i。電3 80 二該組過孔3〇6酉己置成列並且第三板狀接觸點t分 I中的母孔306 t的-列。提供了額外的過孔 分284-卜·284-2、 214匕在金屬堆積層，中的額外的部 · ^4·8對背。在一個範例性實施方式中，核心雷 w貝層252^的過孔是57μιη實心銅過孔（s〇lidc〇ppervias)。 現在翏考圖10 ’更詳細顯示為金屬層242的範例性 孟屬層242包括與該組過孔3〇8電接觸的一第一板狀導 $。 包括與該組過孔3〇4電接觸的第二板狀導電部^24。全 層 254 包括與過孔 31(M、31〇_2、31M、、3iq_8 ^ 6 2 匕卜的板狀導電部分33〇 一般是梨形的形狀，但也可使^ ^f 術語“一般，，是指大致，並且可包括圓角和其他开嫌變化。ί i〇中的板狀導電部分互相被電氣隔離的。 圖 340 2現在11 ’―電介質層形成阻焊膜252，並且包括孔燦1、 性實施方式中，孔具有一⑼義的球節 現在簽考圖12 ’顯示為金屬堆積層25〇相對於圖9的 244、圖1〇的金屬層242和圖n的阻焊膜252的對齊。 、运 入見在參5圖13，互連結構236可被輯為具有額外的金屬和電 援及/或防止由於熱膨脹和收縮造成的翹曲。圖 的互連結構包括結合圖7_12顯示出和描述的層，但是在第二 242和阻焊膜252之間提供了額外的層。 、，萄層 互連結構236包括具有鍍通孔（PTH) 35〇的一基板348，所述 25 200847381 鍍通孔提供從金屬層242到金屬層370的連接。金屬層37〇被配置在 基板348的相反一側。電介質層374被配置在金屬層37〇相鄰以及包 括過孔375，這些過孔提供了從金屬層370到金屬層376的連接。金 屬層376被配置在電介質層374的相反一側。在一種實施方式中，金 屬層370具有與圖10所示的金屬層242類似的結構。阻焊層被配置在 金屬層376的相反一侧。阻焊層252中的孔378允許焊球254提供盥 其他電子元件的連接。 金屬層250、242、370和376更好地是用銅、銘或任何其他適當 的導電材料來形成。金屬層354及/或350可以是蝕刻及/或以其他方^ 形成在基板348上的軌跡。金屬層250和376可以是通過電鍍形成的 堆積層。 現在參考圖14和15，在一個範例性實施方式中，基板348包括 第一組PTH 350，該組PTH電連接到圖1〇中的第一板狀導電部分並 與之對齊。一第二組PTH 354電連接到圖1〇中的第二板狀導電部分 324並與之對齊。一第三組PTH356電連接到圖1〇中的第三板狀導電 部分326並與之對齊。基板348還包括其他PTH 36(M、360-2、…和 360-8，這些PTH電連接到額外的板狀部分33(M、33(K2、 、33〜8 並與之對背。在一優先實施例中，PTH具有200 μηι的直徑以及最小 15μηι和平均18μηι的電鍍壁厚度。在圖15中，顯示出基板348 (底 部）與金屬層242 (頂部）的對齊。 一 現在參考圖16,其顯示出電介質層374(頂部）和金屬層370(底 部）的對齊和定向。該對齊和定向與圖12所示的電介質層244和全屬 層242類似。由於電介質層244和374是類似的用二= 號後跟“ ”。一類似的方法將用於金屬層242和370。 現在參考圖17，更詳細顯示出底部金屬層376以及包括第一、 第二和第三板狀導電部分4〇〇、404和406。在一優先的實施例中，板 狀導電部分400、404和406具有一個一般矩形的形狀，但也可使用其 他形狀。還提供了額外的板狀導電部分410-1、410-2、410-3、...、410-8'。 名員外的導電部分410-1、410-2、410_3、…、410_8具有一個一般梨狀 26 200847381 的截面，但也可使用其他形狀。 出電^見質在目對於金屬層376 (底部）的板狀部分顯示 ，二貝層 374(頂 )上的過孔 3〇4,、3〇6,、3〇8，和 31〇4,、31〇々，、 和互連。導電部分優先地具有15吨的最小厚度和18 導接金屬層370的第一部分320,和金屬層376的板狀 的=二^ 。之孔3〇4’連接金屬層370的第二部分324,和金屬層376 牙入严分4〇4。過孔3〇6,連接金屬堆積層370的第三部分326, ί 0 RH6的板狀導電部分搬。額外的過孔遍_1,、3财 屬層376==^分33W，、、··.、爾連接到金 焊芦2m r在金屬層376和電介質層374的頂部顯示出阻 ===和術、聊、…、鑛相對於金屬層- 從图圖2時2卜顯不出頂部金屬堆積層25G的額外佈局。 屬層’以減小阻抗並增大熱的散失。 t w 丨孟 分414相^ /門垃艇、匕一般地“C”形狀配置一第二外侧接觸點部 ======位於第—和第二外侧接觸點 卩分412和414之間可以配置—個或多個額外的接觸 上Ρ刀419以供給控制信號，例如閘極控制信號。 且有圖顯示出頂部金屬堆積層^°的另一佈局。％與 地—外側部分422關聯的。^與具有一般 也矩祕狀配置-弟二外側部分424關聯的。中間部分428位於第一 27 200847381 ^第二外侧部分422和424之間。沿著堆積層42〇的一側或多側或一 端或多端可以配置一個或多個額外的部分430以供給控制信铲，例如 閘極控制信號。 現在苓考圖22，除了 1C 444之外，解耦電容器440也可附屬到 Vdd和Vss之間的互連結構236，該1C 444安放在互連結構236的金屬 ，積層250上。解搞電容器440包括被絕緣材料456分隔開的第一和 第二導電板450和452。板450和452分別通過導電臂46〇和462連 接到互連結構236。在一種實施方式中，導電臂46〇和462連接到v 和Vss。臂460和462的末端連接到互連結構236的堆積層25〇。= $積層250相對的薄，因此它具有相對較高的阻抗。在一個實施: 臂460和462具有一般地“L”形狀的配置。 、 拉^現在參考目23，IC 472通過焊球474 _到互連結構236的堆 ，250。T的金屬層4’和48〇-2或者金屬條形成在堆積層的⑽ 士如以力日大八強度並減小其阻抗。在一優先實施例中，金屬層480是 的。短路寄生電阻和482_2將電容器484連接到互連 互連職配置在 接=連結構236。在圖24Α中，散熱器潘i 向外突出的鰭狀物5G4的基部5G2。基部％ 層25〇。鰭狀物5〇4提供增大的表面面積以 堆知 在圖24B中，1C 501的一個表面連接到互遠么士 、， 2通過焊球栅陣列5〇9連接到一散熱器帶51〇的^ =相= 的另-端也可例如利用焊球連接到互連結構二:， 強化條金屬堆積層的接觸點部分之一以^力= 在圖24C中，散熱器帶52〇的一端 統方法連接到互連結構。強化條514提供了加 28 200847381 散熱器帶520的相反端。 現在夢考® 25A和2犯，替換的互連結構_包含一圖案 核：。銘核心被用一系列掩蔽步驟圖案化，並且其一侧或兩側 ^曝路到夕孔及域密集的陽極處理（_dizatiGn)中的至少一種 是f兩ί進行的，則_心優先具有這樣的厚度，該厚度允 终在執仃兩側®案化時能夠通過銘核心完全執行陽極處理。 圖25Α中的铭核心被圖案化，分別限定 、 ΪΓ^606 ^ 608 ^ 610 〇 5 600 在 ， 614由電财雜处的娜成。^ k孔及/或堆積層 接616被應用在倒轉過孔614之間，以提供額外的結構支 ，。強化材料616優先是不導電的。在一個實 f t ^ 堆積層 或局於過孔及/或堆積層614的平面處。焊玻 /Hr倒轉的過孔及/或堆積層614連接到積體電路^如功率id /或驅動魏。類似地結構也可簡在互連結構的相反側。 608和1參m6 ’替換的互連結構630包括形成在區域604、606、 纟4上的烊益634。諸如環氧樹脂之類的強化材料616包封焊般 634和紹核=的外表面，以提供絕緣並增加剛性。 ^协孤 現在茶考圖27A和27B，顯示為具有鋁核心的互遠纟士 化材料_ ί, %、Vx和％區域652、654和656的紹核心。強 $材枓660被施加在區域652、654和656之間，以 j =二倒轉過孔及/f_ 664優先地利“鑛^形成，但 體％路（例如功率1C及/或驅動電路）的連接。〆貝g ,J矛貝 額外心的互連結構的 互連、、、。構7GG包括具有圖案化的Vss、％、％和閘極_ 29 200847381 Γί 708的紹核心。如習知技術_所示，強化材料710 ^ Ιΐΐΐϊ ^及/或堆積層714優統電鍍銅形 和ff。谭球620提供從過孔及/或堆積層714 到積體電路的連接，例如功率IC及/或驅動電路。 現在參考圖29A和29B，顯示為Ic _例如—功率IC， il 81ff t架810限定了使寄生電感最小化的傳輸線或 ίίϊ或平面812和1C _部金屬層之_連接二 "⑽包括封裝傳輪線812和IC 8GG的-成形材料 局。雖缺^ 800優先具有與圖lB和4B所示類似的一佈 體，但i‘其他==和汲極D的PMOS*應0s電晶 ^ ^ ΐ 子以及第-和第二端子。導後加Q2、Q3和Q4包括控制端 =分=收第-简和仏以及第二對 ml °ic 818^ ^ί材料和方法° In an embodiment, the buildup layer 250' has an average thickness of G ing but can also be sized to other thicknesses. Tian Xi 3250. It can be appreciated that the two structures basically balance each other with $. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The shell layer 24 200847381 Referring now to the ® 9, the dielectric layer 252 is shown in more detail. Dielectric > % f - part 260 of field 264 aligned - set of vias 3 〇 4 〆 = ί part * 270 of the base 274 aligned with a set of vias 3 〇 i. The electricity 3 80 two sets of vias 3 〇 6 酉 have been placed in columns and the third plate contact point t is the column of the mother holes 306 t in I. Additional vias are provided 284-b·284-2, 214匕 in the metal buildup layer, the additional part of the ^4·8 pairs of back. In an exemplary embodiment, the vias of the core rib layer 252 are 57 μm solid copper vias (s〇lidc〇ppervias). Referring now to Figure 10, an exemplary embodiment of the metal layer 242 is shown in more detail as a first plate-like guide that is in electrical contact with the set of vias 3〇8. A second plate-shaped conductive portion 24 is provided in electrical contact with the set of vias 3〇4. The full layer 254 includes a plate-like conductive portion 33 与 with a via 31 (M, 31 〇 2, 31 M, 3iq_8 ^ 6 2 ), generally in the shape of a pear, but can also be used to make the term "general, , means roughly, and may include rounded corners and other open-ended variations. The plate-shaped conductive portions in the 〇i〇 are electrically isolated from each other. Figure 340 2 Now 11'- dielectric layer forms a solder mask 252, and includes holes 1. In a preferred embodiment, the hole has a (9) sensed ball joint. Figure 12 is shown as a metal buildup layer 25 〇 relative to 244 of FIG. 9, the metal layer 242 of FIG. 1A, and the solder mask 252 of FIG. The alignment of the interconnect structure 236 can be tailored to have additional metal and electrical assistance and/or prevent warpage due to thermal expansion and contraction. The interconnect structure of the figure includes the combination of Figure 7_12. The layers are shown and described, but with an additional layer provided between the second 242 and the solder mask 252. The layer interconnect structure 236 includes a substrate 348 having plated through holes (PTH) 35 turns, 25 200847381 Plated through holes provide a connection from metal layer 242 to metal layer 370. Metal layer 37 is configured on the base The opposite side of the board 348. The dielectric layer 374 is disposed adjacent to the metal layer 37 and includes vias 375 that provide connections from the metal layer 370 to the metal layer 376. The metal layer 376 is disposed on the dielectric layer 374. The opposite side. In one embodiment, the metal layer 370 has a similar structure to the metal layer 242 shown in Figure 10. The solder resist layer is disposed on the opposite side of the metal layer 376. The holes 378 in the solder resist layer 252. The solder balls 254 are allowed to provide connections to other electronic components. The metal layers 250, 242, 370, and 376 are preferably formed of copper, metal, or any other suitable conductive material. The metal layers 354 and/or 350 may be etched and / or trajectories formed on the substrate 348. The metal layers 250 and 376 may be stacked layers formed by electroplating. Referring now to Figures 14 and 15, in an exemplary embodiment, the substrate 348 includes a first set of PTHs. 350. The set of PTHs is electrically coupled to and aligned with the first plate-shaped conductive portion of Figure 1A. A second set of PTHs 354 is electrically coupled to and aligned with the second plate-like conductive portion 324 of Figure 1A. A third set of PTH356 is electrically connected to Figure 1〇 The third plate-shaped conductive portion 326 is aligned therewith. The substrate 348 also includes other PTHs 36 (M, 360-2, ..., and 360-8, which are electrically connected to the additional plate portion 33 (M, 33 (K2) And 33 to 8 and opposite thereto. In a preferred embodiment, the PTH has a diameter of 200 μm and a plating wall thickness of at least 15 μm and an average of 18 μm. In Fig. 15, the substrate 348 (bottom) and the metal layer are shown. Alignment of 242 (top). Referring now to Figure 16, there is shown the alignment and orientation of dielectric layer 374 (top) and metal layer 370 (bottom). This alignment and orientation is similar to dielectric layer 244 and full layer 242 shown in FIG. Since dielectric layers 244 and 374 are similar, the second = is followed by " ". A similar method will be used for metal layers 242 and 370. Referring now to Figure 17, the bottom metal layer 376 is shown in more detail and includes first, second and third plate-like conductive portions 4, 404 and 406. In a preferred embodiment, the plate-like conductive portions 400, 404, and 406 have a generally rectangular shape, although other shapes may be used. Additional plate-like conductive portions 410-1, 410-2, 410-3, ..., 410-8' are also provided. The conductive portions 410-1, 410-2, 410_3, ..., 410_8 outside the celebrity have a cross section of a general pear shape 26 200847381, but other shapes may be used. The output of the electricity is shown in the plate-like portion of the metal layer 376 (bottom), and the via holes 3〇4, 3〇6, 3〇8, and 31〇4 on the second shell layer 374 (top), , 31〇々, , and interconnection. The conductive portion preferentially has a minimum thickness of 15 tons and a first portion 320 of the 18-contact metal layer 370, and a plate-like shape of the metal layer 376. The hole 3〇4' connects the second portion 324 of the metal layer 370, and the metal layer 376 is severely divided into 4〇4. The via hole 3〇6 is connected to the third portion 326 of the metal buildup layer 370, and the plate-shaped conductive portion of the ί 0 RH6 is transferred. The additional vias _1, 3 fiscal layers 376 == ^ minutes 33W, , ···, are connected to the gold solder 2m r at the top of the metal layer 376 and the dielectric layer 374 show resistance === And surgery, chat, ..., mine relative to the metal layer - from Figure 2, 2 2 shows the extra layout of the top metal stack 25G. The genus layer ' reduces impedance and increases heat loss. Tw 丨 Meng points 414 phase ^ / door boat, 匕 generally "C" shape configuration a second outer contact point ====== located between the first and second outer contact points 412 and 414 One or more additional contact upper boring tools 419 are configured to supply control signals, such as gate control signals. And there is a diagram showing another layout of the top metal build-up layer ^°. % is associated with the ground-outside portion 422. ^ is associated with the outer portion 424 having a general also secret configuration. The intermediate portion 428 is located between the first 27 200847381 ^ second outer portions 422 and 424. One or more additional portions 430 may be disposed along one or more sides or one or more ends of the buildup layer 42A to supply a control shovel, such as a gate control signal. Referring now to Figure 22, in addition to 1C 444, decoupling capacitor 440 can also be attached to interconnect structure 236 between Vdd and Vss, which is placed over metal, build-up 250 of interconnect structure 236. The unwinding capacitor 440 includes first and second conductive plates 450 and 452 separated by an insulating material 456. Plates 450 and 452 are coupled to interconnect structure 236 by conductive arms 46A and 462, respectively. In one embodiment, conductive arms 46A and 462 are coupled to v and Vss. The ends of the arms 460 and 462 are connected to the buildup layer 25 of the interconnect structure 236. = $The layer 250 is relatively thin, so it has a relatively high impedance. In one implementation: Arms 460 and 462 have a generally "L" shaped configuration. Referring now to item 23, IC 472 passes through solder balls 474_ to the stack of interconnect structures 236, 250. The metal layers 4' and 48〇-2 of T or the metal strips formed at the (10) layer of the build-up layer are as strong as eight strengths and reduce their impedance. In a preferred embodiment, metal layer 480 is . The short-circuit parasitic resistance and 482_2 connect capacitor 484 to the interconnect interconnect configuration. In Fig. 24A, the heat sink Pan i protrudes outward from the base 5G2 of the fin 5G4. Base % layer 25〇. The fins 5〇4 provide an increased surface area to be known in Fig. 24B, one surface of the 1C 501 is connected to each other, and 2 is connected to a heat sink belt 51 by the solder ball grid array 5〇9. The other end of the ^ = phase = can also be connected to the interconnect structure 2, for example, by solder balls: one of the contact point portions of the reinforcing strip metal stack is pressed = in Fig. 24C, one end of the heat sink strip 52〇 The method is connected to the interconnect structure. Reinforcing strip 514 provides the opposite end of the heat sink strip 520 of 28 200847381. Now Dream Test® 25A and 2 commit, replace the interconnect structure _ contains a pattern core:. The core of the Ming is patterned with a series of masking steps, and at least one of the one or both sides of the exposed surface and the densely packed anode treatment (_dizatiGn) is performed by f ί, then _ heart has priority The thickness, which allows the anode to be completely performed through the Ming core when the two sides of the handle are finished. The core of the Ming in Figure 25 is patterned, respectively, ΪΓ ^ 606 ^ 608 ^ 610 〇 5 600 in , 614 by the electricity and wealth of the Nacheng. ^K holes and/or buildup layers 616 are applied between the inverted vias 614 to provide additional structural support. Reinforcing material 616 is preferably non-conductive. At a real f t ^ buildup layer or at the plane of the via and/or buildup layer 614. The solder glass/Hr inverted via and/or buildup layer 614 is connected to the integrated circuit ^ such as power id / or drive Wei. A similar structure can also be simplified on the opposite side of the interconnect structure. The interconnect structure 630, which is replaced by 608 and 1 reference m6', includes benefits 634 formed on regions 604, 606, 纟4. A reinforcing material 616, such as an epoxy resin, encapsulates the outer surface of the solder 634 and the core to provide insulation and increase rigidity. ^ 协孤 Now tea test Figures 27A and 27B, shown as the center of the distant gents material _ ί, %, Vx and % areas 652, 654 and 656 with aluminum core. A strong material 660 is applied between regions 652, 654, and 656, with j = two inverted vias and /f_664 preferentially forming "mines, but body % channels (eg, power 1C and/or drive circuitry) The interconnection of the interconnect structure of the mussel g, J spears, and the structure 7GG includes a core having a patterned Vss, %, %, and gate _ 29 200847381 Γί 708. As shown, the reinforcing material 710 ^ Ιΐΐΐϊ ^ and/or the buildup layer 714 is preferably plated with copper and ff. The Tan ball 620 provides connections from the via and/or buildup layer 714 to the integrated circuit, such as power ICs and/or Referring now to Figures 29A and 29B, shown as Ic_, for example, a power IC, the il 81ff frame 810 defines a transmission line that minimizes parasitic inductance or a connection between the Ø or 812 and the 1C _ metal layer. (10) A forming material bureau including a package transfer line 812 and an IC 8GG. Although the absence of 800 has a cloth body similar to that shown in Figs. 1B and 4B, the PMOS* of i' other == and the drain D should be 0s. Electro-crystal ^ ^ ΐ sub and the first and second terminals. Add Q2, Q3 and Q4 after the guide including control terminal = minute = receive first - Jane and 仏 and To ml ° ic 818

電晶體，但也可使用其=的和難〇的_…S 功率ifim其顯示為具有額外的多對電晶體的ic (例如一 平面购（例^應=^導=7\置了輸人傳輸線或 配置了輸__._如^導赫 30 200847381 ° _域職傳輸線或平面 晶體對Qla、Q2a、Qlb、〇率^)被廣泛顯示為900。IC 900包括電 括控制端子以及第-和第二^。:么以及Qld和Q2d ’其中每一對包 極D的PMOS和NM〇S ^濟° f=顯=為具有閉極、源極S和沒 電曰曰體對的連接的端子之間取得輸出 兩= 的剩餘的端子連接到Vdd#lJ %。 a Vxj Vxd㈣體對 ，似IC 9GG触部金勒優先财與® 8B所顯示 二此相鄰地配置。互連結構908包括配置在第 和二二包曰曰體對輸送Vss、Vdd和Vss的傳輸線働-1、910·*2 I對的幹出ϋ9()8ν還包括配置在第二層*並且分別接收來自電晶 子巧出域vxa、vxb、Vxc和vxd的傳輸線912心912_2、9 和 912-4 〇 於绩^^3气圖互連結構95G包括配置在第一和第二層中的傳 tit °， 951提供電源及/或接地連接。在圖33中的 只也式中，第一層包括一傳輸線或平面954_1和954-2。第一声包括 =傳輸，或平面954·3。電容H 960連接在傳輸線Mu和954_2日之間。 層用於電源及/或接地，餘11 _可在低電感的情況下連 ^到1C 951。連接結構950可以被實施使用一 PCB或使用一堆積基板 使用-PCB材料。在-種實施方式中，第一層位於『951和第二層 之間。本領域的技術人員將會意識到實施連接結構的其他方式。 ~圖29-33中的傳輸線或平面之間的間距優先地被最小化以減小寄 生電容並增大遮罩。例如，小於12密爾（mil)的間距是合適的。優 先地，使用小於8密爾的間距。圖29-31中為顯示出的導線架中的一 些實施為四邊扁平無接腳（QFN)封裝。 現在芩考圖34A和34B，依據本發明的電晶體1〇5〇被顯示為包 括一個或多個源極1054和一個或多個汲極1〇56。源極1〇54和汲極 31 200847381 1056包括η區域。雖然顯示出NMOS電晶體，但本領域的技術人員 將會意識到本發明也可應用到其他類型的電晶體，例如PM〇s電晶 體。閘極1058位於1054和汲極1〇56的相鄰對之間。在一種實施 中，位於源極1054的相反兩側的閘極1058連接在一起，如1〇64所示\ 但是，在其他配置中，閘極1058不需要連接在一起。 包括P+區域的主體1066被配置在内部並且被源極1〇54包圍。 主體1066優先具有-隨著主體祕的正中央與相鄰閉極之間的距離 減小而逐漸變尖細的形狀。在圖34A和34B的平面圖中，主體1〇66 可觸及閘極1G58也可不觸及閑極1058。換言之，主體祕的一個或 兩個邊緣在平面圖中可以與閘極1058間隔開（如圖34A所示），及/ 或在平面圖中基本與閘極對齊（如圖34B所示）。通過將源極1〇54的 二些區域用於主體1066，與傳統電晶體相比電晶體1〇5〇的整體尺寸 得以減小。在圖34A和34B所示的範例性實施方式中，主體1〇66是 一菱形的。 現在參考圖35和36，其中顯示出了主體1〇66的其他範例性形 狀。在圖35中，主體1〇66是六邊形的。在圖36中，主體ι〇66是一 般橄欖球形狀的。本領域的技術人員將會意識到有許多種直他適各形 37中示為出了圓形主體1〇66。其他適當形狀包括橢^ 現在參考圖37和38A，閘極1058可以配置成在沒有接觸分接頭 jcontacttap)時靠近在—起，而在有接觸分_時雜遠的距離。在 圖37中，二源極接觸分接頭1〇7〇，不位於主體1〇66中，位於相鄰閘 極1058區域中有較遠的距離。在圖38A中，一主體接觸分接頭麵， 位於主體1066中，位於源極1054中相鄰閘極1〇58位於較遠的距離。 現在參考圖，如Sii所述，圖34A_38A中的電晶體佈局中的 壬何種可經由絕緣/過孔/局部互連層（insuiating/Vias/L〇cal ntenx>nnects)與板狀金屬層（p)和外侧接觸點層（〇)通信。如前 所述，外側接觸點層（0)可與互連結構通信及/或可配置在封裝中。 僅作為示例，圖4A-4D中的絕緣/過孔/局部互連層（j/v/jj)可 32 200847381 用於k供下面的電晶體佈局（例如電晶體佈局1 )和 ;間的連接，如上述糊格4D巾所述。板狀金顧 ，觸點層⑼通信，也如目4A_4D中所述。外側細點層⑼可! =連結構通信，如圖7所示。這種配置可減小電阻損耗並減小 曰日片面積，如上述更詳細所述。 除上述之外，電晶體佈局可在圖2所示的功率Ic中連接和 也可使用圖20-33所顯示的其他配置。The transistor, but can also use its = and difficult _...S power ifim which is shown as an ic with additional pairs of transistors (eg a plane purchase (example ^ should = ^ guide = 7 \ set the input) The transmission line or configuration is __._如^导赫30 200847381 ° _ domain transmission line or plane crystal pair Qla, Q2a, Qlb, ^ rate ^) is widely displayed as 900. IC 900 includes the electric control terminal and the first - And the second ^:: and Qld and Q2d 'the PMOS and NM 〇S of each pair of the package D are f = display = for the connection with the closed pole, the source S and the no-electric pair The remaining terminals that take the output between the two terminals are connected to Vdd#lJ %. a Vxj Vxd (four) body pair, like the IC 9GG contact, the Golder priority and the 8B are displayed adjacent to each other. The interconnection structure 908 includes The dry-out ϋ9()8 ν of the pair of transmission lines 働-1, 910·*2 I disposed in the first and second packets of the transport body for Vss, Vdd, and Vss also includes the second layer* and is received from the electron crystal The transmission lines 912 912_2, 9 and 912-4 of the domain vxa, vxb, Vxc and vxd are in a state of view. The gas grid interconnection structure 95G includes the transmission tap °, 95 arranged in the first and second layers. 1 Providing a power and/or ground connection. In the Figure only, the first layer includes a transmission line or planes 954_1 and 954-2. The first sound includes = transmission, or plane 954. 3. Capacitance H 960 connection Between the transmission line Mu and 954_2. The layer is for power and/or ground, and the remaining 11 _ can be connected to 1C 951 with low inductance. The connection structure 950 can be implemented using a PCB or using a stacked substrate - PCB material. In an embodiment, the first layer is located between "951 and the second layer. Those skilled in the art will recognize other ways of implementing the connection structure. ~ Transmission lines or planes in Figures 29-33 The spacing between the spaces is preferentially minimized to reduce parasitic capacitance and increase the mask. For example, a pitch of less than 12 mils is suitable. Preferably, a pitch of less than 8 mils is used. Figure 29-31 Some of the leadframes shown are implemented as four-sided flat no-pin (QFN) packages. Referring now to Figures 34A and 34B, a transistor 1〇5〇 in accordance with the present invention is shown to include one or more sources 1054. And one or more bungee 1〇56. Source 1〇54 and bungee 31 20084738 1 1056 includes an η region. Although an NMOS transistor is shown, those skilled in the art will appreciate that the invention is also applicable to other types of transistors, such as PM〇s transistors. Gate 1058 is located at 1054 and bungee Between adjacent pairs of 1 〇 56. In one implementation, the gates 1058 on opposite sides of the source 1054 are connected together, as shown by 1 〇 64. However, in other configurations, the gate 1058 does not need to be connected. The body 1066 including the P+ region is disposed inside and surrounded by the source 1〇54. The body 1066 preferably has a shape that tapers as the distance between the center of the body and the adjacent closed pole decreases. In the plan views of FIGS. 34A and 34B, the main body 1 〇 66 may touch the gate 1G58 or may not touch the idle pole 1058. In other words, one or both edges of the subject may be spaced apart from the gate 1058 in plan view (as shown in Figure 34A), and/or substantially aligned with the gate in plan view (as shown in Figure 34B). By using two regions of the source 1 〇 54 for the body 1066, the overall size of the transistor 1 〇 5 相比 is reduced as compared with the conventional transistor. In the exemplary embodiment illustrated in Figures 34A and 34B, body 1 〇 66 is a diamond. Referring now to Figures 35 and 36, other exemplary shapes of the body 1 〇 66 are shown. In Fig. 35, the main body 1〇66 is hexagonal. In Fig. 36, the main body 〇 66 is generally rugby-shaped. Those skilled in the art will recognize that there are many types of straight shapes 37 that are shown as circular bodies 1〇66. Other suitable shapes include ellipses. Referring now to Figures 37 and 38A, the gate 1058 can be configured to be close to the in-line when there is no contact tap jcontacttap) and a farther distance when there is a contact. In Fig. 37, the two source contact taps 1〇7〇 are not located in the main body 1〇66 and are located at a relatively long distance in the area of the adjacent gate 1058. In Fig. 38A, a body contact tap face, located in body 1066, is located at a greater distance from adjacent gate 1 58 in source 1054. Referring now to the drawings, as described in Sii, what of the transistors in the transistor layout of Figures 34A-38A can be via an insulating/via/local interconnect layer (insuiating/Vias/L〇cal ntenx>nnects) and a platy metal layer ( p) Communication with the outer contact layer (〇). As mentioned previously, the outer contact layer (0) can be in communication with the interconnect structure and/or can be configured in a package. By way of example only, the insulating/via/local interconnect layer (j/v/jj) of Figures 4A-4D may be used for the following transistor layout (e.g., transistor layout 1) and the connection between , as described above for the 4D towel. The plate is in contact with the contact layer (9), as described in item 4A_4D. The outer fine layer (9) can be! = connected structure communication, as shown in Figure 7. This configuration reduces resistive losses and reduces the area of the day, as described in more detail above. In addition to the above, the transistor layout can be connected in the power Ic shown in Fig. 2 and other configurations shown in Figs. 20-33 can also be used.

現在參考圖39，其顯示出一 pm〇s電晶體112〇。電晶體112〇 包，-閘極接觸點II22、一源極接觸點脳、一沒極接觸點⑽和 一負極的（N)井區接觸點113〇。源極接觸點1126提供與形 N 型基板層1138中的-p*區域n34的連接型層1138依次形成在 P型基板1140中。p*區域1134形成源極。沒極接觸點1128提供與形 成在N型基板層1138巾的卩科區域咖的連接。ρ·Η·區域脱形 極。Ν井區接觸點1130提供與區域1141或Ν井區的一連接。 現在參考圖40，其顯示出第六範例性電晶體佈局1198的一平面 圖。對於諸如PMOS及/或NM〇S電晶體之類的一些電晶體設計，靜 電放電（Electrostatic Discharge, ESD)比其它設計標準較不重要。因此， 可以使N井區接觸點面積最小化。對於pM〇s電晶體，N井區接觸點 面積可以是NM0S電晶體巾的面積的約2·5至3倍。祕跡電阻可 以不太重要。因此’圖40中的佈局最小化了 Ν井區接觸點面積和源 極-汲極區域。本領域的技術人員將會意識到，雖然以上描述涉及 PM0S電晶體，但類似的原理也適用於_〇8電晶體。 在圖40所示的電晶體佈局中，閘極區域12〇(Μ、12〇〇_2、和 1200-G (共同地為閘極_或閘極㈣）被限絲源極區域、 1224-2、"·和1224_S (共同地為源極區域1224)和汲極區域1220-1、 1220-2、…和1220-D (共同地為汲極區域122〇)之間。相鄰的閑極 1200-1和1200-2限定區域1210,具有一比相鄰區域1212更寬的寬度。 汲極區域1220和源極區域1224被交替限定在相鄰閘極12〇〇之間。 電晶體群組1230-11、1230·12、和123〇-55 (共同地為電晶體 33 200847381 群組1230)被配置成彼此相鄰。雖然顯示為5χ5 乘Υ陣列，X和Υ是大於！的整數。相鄰的電 用R個N井區接觸點126G，其中R是大於丨的整數。ς ^ 1260 1230 ^fa1, 12〇〇 此佈局使源極·汲極區域最小化。例如，每個群組可包括4_6個 2體。為相鄰群組在垂直和水平方向上都提供了 R個N井區接觸點 。=此，無R個N井區接觸點126〇的相鄰群組 於閘糾m·的區域⑵2巾。齡之，_丨細可 以使無R個N井區接觸點126G的區域1212的面積最小化。代狄 月ιοί回參4〇的電晶體佈局1198可用來取代電晶體佈 電晶體佈局1198可經由絕緣7過孔/局部互連層 (I/V/LI)與板狀金屬層（P)和外側接觸點層⑼通信。如前， 外侧接觸點層〃⑼可與互連結魏健且/或者可被配置在封裝斤中。 僅作為範例，圖4A-4D中的絕緣/過孔/局部互連層（I/V/U)可 用來提供T面的電晶體佈局和板狀金屬層（p )之間的連接，如圖格仍 ^述之。板狀金屬層（p)可與外侧接繼層⑼通信，也如圖4a_4d 中所述。外側細點層⑼可與互連結構通信，如目7所示。這種 配置可用^減小電阻損耗並減小晶片面積，如以上詳細所述。 除箣述外，電晶體佈局可在圖2所示的功率IC中連接及 也可使用圖20-33顯示出其他配置。 1A，：、、中顯不出用於橫向擴散金氧半場效電晶體 ..^ )至屬氧化物半導體(LDMOS)電晶體1300的範例性高密度 布局。该佈局傾向於減小導通汲極-源極電阻11〇8〇11。電晶體丨3㈨包 ^源極區域1304、沒極區域13〇6和閘極區域131〇。源極區域13〇4 些或全部可以包括—個或多個源極接觸點i3i卜或者源極區域 1304可以都不包括一個或多個源極接觸點1311。出於說明目的，不是 所有源極區域1304都被顯示為具有源極接觸點1311。 閑極1310限疋一棋盤圖案。源極區域⑽4沿著汲極區域1306 34 200847381 的側邊配置。更具體而言，沒極區域1306可以具有一般矩形型狀。源 極區域1304可沿著一般矩形的汲極區域1306的每一側配置。基板接 觸點1330可設置在相鄰於汲極區域1306的角落、相鄰源極區域1304 之間的交點處。汲極接觸點1334也可設置在汲極區域1306内的中央 位置處。 每個汲極區域1306可配置在與其他相鄰汲極區域1306共同的源 極區域1304相鄰。例如，在圖41A中的虛線區域1331中，汲極區域 1306-1與沒極區域1306_2共用源極區域1304-1。汲極區域1306-1與 汲極區域1306-3共用源極區域1304-2。汲極區域1306-1與汲極區域 f 13〇6-4共用源極區域1304·3。没極區域1306-1與汲極區域1306-5共 用源極區域1304-4。可以對相鄰的汲極區域1306重複此模式。 汲極區域1306中的每一個可具有大於或等於源極區域13〇4中的 每一個面積的兩倍面積。在圖41Α中，汲極區域1306具有一寬度“b，， 和一高度“a”。源極區域1304具有一寬度（或高度）“d”和一高度（或 寬度）“c”。汲極區域1306可具有與源極區域1304基本相同的長度。 汲極區域1306可具有大於或等於源極區域1304寬度的兩倍寬度。 現在參考圖41B，其顯示出圖41A的佈局更詳細視圖的一部分。 汲極接觸點1334-1和1334-3可以分別與汲極區域1306-1和1306-3相 關聯。基板接觸點1330之位置與汲極區域1306-1的角落相鄰。源極 接觸點1311小1311-2、."和1311»6可配置在源極區域1304_2和1304-4 中’其中B是整數。汲極接觸點1334-1和1334-3可分別配置在汲極 區域1306-1和1306-3的每一個中。汲極接觸點1334-1可限定比汲極 區域1304-2中的源極接觸點1311_1的面積更大的面積。 實質上所有在汲極區域1306-3和相鄰的源極區域13〇4_2的源極 接觸點131M、1311-2、…和1311-B之間流動的電流都在汲極接觸點 1334-3的一對向部分（facingp0rti〇n) 1335和源極區域1304_2中的源 極接觸點 1311-1、1311-2、…和 1311-B 的對半 1337-1、1337_2、..·和、 1337-S之間流動。電流以類似的方式在汲極接觸點1334-3的其他對向 F刀和其他相鄰源極區域1304-5、1304-6和1304_7中的源極接觸點（未 35 200847381 顯示出）之間流動。 現在參考圖41C，其中顯示出了橫向擴散金氧半場效電晶體 (MOSFET)金屬氧化物半導體(LDMOS)電晶體1340的另一範例性高 密度佈局。該佈局傾向於提供較低的導通没極_源極電阻奶8〇11。電晶 體1340包括源極區域1304-1卜1304-12、…、1304-4Q、汲極區g 1306-11、1306-12、…、1304-4T 和閘極 1310 ’ 其中 Q 和 τ 是整數。 雖然圖41C中顯示出四列，但也可使用額外的及/或更少的列及/或行。 源極區域1304中的一些或全部可以包括源極接觸點1311，或者源極 區域1304可以都不包括源極接觸點1311。出於說明目的，不是所有 源極區域1304都被顯示為具有源極接觸點1311。例如，源極區域 1304-12包括源極接觸點13H4、1311_2、和1311_β，其中B是整 數。 ，、 正 其他狹長源極區域1344-1、1344-2、1344-3、…和1344-R被配 置在沒極區域1306的列（或行）之間，並且可由配置在圖41C中的 佈局的一側或兩側（或頂部）的驅動器13464、1346-2、···和1346_r 驅動。狹長源極區域13444、1344-2、1344_3、…和1344-R可延伸到 與至少兩個汲極區域13G6 (例如至少没極區域i遍_u 的側邊相鄰。 ；Referring now to Figure 39, a pm 〇 transistor 112 显示 is shown. The transistor 112 包 package, the gate contact point II22, a source contact point 脳, a immersion contact point (10), and a negative (N) well contact point 113 〇. The source contact 1126 is provided in the P-type substrate 1140 in a sequential manner with the connection layer 1138 of the -p* region n34 in the N-type substrate layer 1138. The p* region 1134 forms a source. The immersion contact 1128 provides a connection to the enamel area coffee formed on the N-type substrate layer 1138. ρ·Η·regional depolarization pole. The Sakai contact point 1130 provides a connection to the area 1141 or the Sakai area. Referring now to Figure 40, a plan view of a sixth exemplary transistor layout 1198 is shown. For some transistor designs such as PMOS and/or NM〇S transistors, Electrostatic Discharge (ESD) is less important than other design standards. Therefore, the area of the N well contact point can be minimized. For pM〇s transistors, the N-well contact area may be about 2.5 to 3 times the area of the NM0S transistor. The trace resistance can be less important. Thus the layout in Figure 40 minimizes the contact area and source-drain region of the well area. Those skilled in the art will appreciate that while the above description relates to PMOS transistors, similar principles apply to _8 transistors. In the transistor layout shown in FIG. 40, the gate regions 12A (Μ, 12〇〇_2, and 1200-G (commonly the gate _ or the gate (four)) are limited to the source region, 1224- 2, "· and 1224_S (commonly for the source region 1224) and the drain regions 1220-1, 1220-2, ... and 1220-D (commonly the drain region 122〇). The poles 1200-1 and 1200-2 define a region 1210 having a wider width than the adjacent region 1212. The drain region 1220 and the source region 1224 are alternately defined between adjacent gates 12A. Groups 1230-11, 1230·12, and 123〇-55 (collectively, transistor 33 200847381 group 1230) are configured to be adjacent to each other. Although shown as a 5χ5 multiplier array, X and Υ are integers greater than !. Adjacent electrical uses R N well contact points 126G, where R is an integer greater than ς. ς ^ 1260 1230 ^ fa1, 12 〇〇 This layout minimizes the source/drain region. For example, each group It can include 4_6 2 bodies. R N well contact points are provided in the vertical and horizontal directions for adjacent groups. == This, adjacent groups with no R N well contact points 126〇 are corrected Area of m· 2 towel. Age, _ 丨 fine can minimize the area of the region 1212 of the contact point 126G without R N well area. The crystal layout 1198 of the 狄 月 ι ι ι 〇 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 电1198 can communicate with the slab metal layer (P) and the outer contact layer (9) via an insulating 7 via/local interconnect layer (I/V/LI). As before, the outer contact layer 〃(9) can be interconnected with Wei Jian And/or can be configured in a package. By way of example only, the insulation/via/local interconnect layer (I/V/U) of Figures 4A-4D can be used to provide T-plane transistor layout and slab metal The connection between layers (p) is as described in Fig. 3. The plate metal layer (p) can communicate with the outer successor layer (9), as also shown in Figures 4a-4d. The outer fine layer (9) can be interconnected Communication, as shown in Figure 7. This configuration can be used to reduce the resistive losses and reduce the wafer area, as described in detail above. In addition to the above description, the transistor layout can be connected in the power IC shown in Figure 2 Other configurations can be shown using Figure 20-33. 1A, :, , and not for lateral diffusion of gold oxide half field effect transistors.. ^) to oxide half Exemplary high density layout (LDMOS) transistor 1300 thereof. This layout tends to reduce the turn-on drain-source resistance 11〇8〇11. The transistor 丨3 (9) includes a source region 1304, a non-polar region 13〇6, and a gate region 131〇. Some or all of the source regions 13〇4 may include one or more source contact points i3i or source regions 1304 may not include one or more source contact points 1311. Not all source regions 1304 are shown as having source contact points 1311 for illustrative purposes. The idle pole 1310 is limited to a checkerboard pattern. The source region (10) 4 is disposed along the sides of the drain region 1306 34 200847381. More specifically, the non-polar region 1306 can have a generally rectangular shape. Source regions 1304 can be disposed along each side of a generally rectangular drain region 1306. Substrate contact 1330 can be disposed at an intersection between a corner adjacent to the drain region 1306 and an adjacent source region 1304. The drain contact 1334 can also be disposed at a central location within the drain region 1306. Each of the drain regions 1306 can be disposed adjacent to a source region 1304 that is common to other adjacent drain regions 1306. For example, in the dotted line region 1331 in Fig. 41A, the drain region 1306-1 shares the source region 1304-1 with the non-polar region 1306_2. The drain region 1306-1 shares the source region 1304-2 with the drain region 1306-3. The drain region 1306-1 shares the source region 1304·3 with the drain region f 13〇6-4. The source region 1304-4 is shared between the gate region 1306-1 and the drain region 1306-5. This mode can be repeated for adjacent drain regions 1306. Each of the drain regions 1306 can have twice the area greater than or equal to each of the source regions 13A4. In Fig. 41A, the drain region 1306 has a width "b," and a height "a". The source region 1304 has a width (or height) "d" and a height (or width) "c". Region 1306 can have substantially the same length as source region 1304. Gate region 1306 can have a width that is greater than or equal to twice the width of source region 1304. Referring now to Figure 41B, a portion of the more detailed view of the layout of Figure 41A is shown. The drain contact points 1334-1 and 1334-3 may be associated with the drain regions 1306-1 and 1306-3, respectively. The substrate contact point 1330 is located adjacent to the corner of the drain region 1306-1. The source contact point 1311 small 1311-2, ." and 1311»6 can be configured in source regions 1304_2 and 1304-4 where B is an integer. The drain contacts 1334-1 and 1334-3 can be respectively disposed in the drain region 1306. In each of -1 and 1306-3, the drain contact 1334-1 can define a larger area than the area of the source contact 1311_1 in the drain region 1304-2. Essentially all in the drain region 1306- 3 and the electric current flowing between the source contact points 131M, 1311-2, ..., and 1311-B of the adjacent source regions 13〇4_2 The flow is at the opposite portion (facing p0rti〇n) 1335 of the drain contact 1334-3 and the opposite half 1337 of the source contact points 1311-1, 1311-2, ... and 1311-B in the source region 1304_2. 1. Flow between 1337_2, .., and 1337-S. Current flows in a similar manner at the other opposing F-knife and other adjacent source regions 1304-5, 1304-6 of the drain contact 1334-3 and Flow between the source contact points in 1304_7 (not shown in 35, 1987, 811.) Referring now to Figure 41C, there is shown another laterally diffused metal oxide half field effect transistor (MOSFET) metal oxide semiconductor (LDMOS) transistor 1340. An exemplary high-density layout. The layout tends to provide a lower conduction immersion _ source resistance milk 8 〇 11. The transistor 1340 includes source regions 1304-1, 1304-12, ..., 1304-4Q, bungee Region g 1306-11, 1306-12, ..., 1304-4T and gate 1310' where Q and τ are integers. Although four columns are shown in Figure 41C, additional and/or fewer columns may be used. / or row. Some or all of the source regions 1304 may include source contact points 1311, or source regions 1304 may not include sources Contact point 1311. For purposes of illustration, not all source regions 1304 are shown as having source contact points 1311. For example, source regions 1304-12 include source contact points 13H4, 1311_2, and 1311_β, where B is an integer . , other narrow source regions 1344-1, 1344-2, 1344-3, ..., and 1344-R are disposed between columns (or rows) of the gate region 1306, and may be laid out in the layout of FIG. 41C. One or both sides (or top) of the drivers 13464, 1346-2, ... and 1346_r are driven. The narrow source regions 13444, 1344-2, 1344_3, ..., and 1344-R may extend to be adjacent to at least two of the drain regions 13G6 (e.g., at least the sides of the gate region i-u.

>及極區域1306中的每一個（例如汲極區域13〇6⑴可 或等於源極區域1304巾的每—個⑽如祕區域切面積的兩 倍面巧。汲極區域1306 (例如錄區域脳_n)可具有轉極區域 13= 區域1304_12)基本相同長度哪遍J 切鱗於獅域叫獅極區域 基板接觸點 m?_ii、ι347_12、1347_2卜 1347_22、1347_23、、 ί:區域是或者可以針對每個狹長 乍為乾例’圖41C所示的基板接觸點1347 36 200847381 了相對於相鄰狹長源極區域1344中的某板接觸點 J 1344 1 二或=目的基板接觸點1347。基板接觸點1347可以對齊或如 還可變Γ她長.區域1344可不包括基板接觸點1347。 1345 ^在ίί 圖 41D ’ 第一區域 1345-八卜 1345_A2、1345^ 和 可提供有用的電晶體區域。例如，第一區域1345-A1、 祕]345-A3和1345·Μ可分別位於沒極區域130642和源極區 二m ^ 1344_卜13G4]3和 1344_21345&、 筮=B3和134別可提供不太有用的電晶體區域。例如， 13〇1 12 1W f1 ^ 1345'B2 ^ 1345-B3 ^ 1345'B4 1304-12、1344-1、1304-13 和 1344-2 之間。> and each of the pole regions 1306 (eg, the drain region 13〇6(1) may be equal to or equal to twice the area of the source region 1304, such as the area cut by the secret region. The drain region 1306 (eg, the recorded region)脳_n) can have a rotating region 13 = region 1304_12) basically the same length which J cut scale in the lion domain called the lion pole region substrate contact point m?_ii, ι347_12, 1347_2 Bu 1347_22, 1347_23,, ί: the area is or A substrate contact point 1347 36 200847381 shown in FIG. 41C may be used for each of the elongated ridges as a dry contact with a board contact point J 1344 1 or a target substrate contact point 1347 in the adjacent elongated source region 1344. The substrate contact 1347 may be aligned or may be variable as long as it is. The region 1344 may not include the substrate contact 1347. 1345^ is in the ίί Figure 41D' first area 1345-eight-b 1345_A2, 1345^ and can provide a useful transistor area. For example, the first region 1345-A1, the secret] 345-A3 and 1345·Μ may be located in the non-polar region 130642 and the source region two m ^ 1344_b 13G4] 3 and 1344_21345 &, 筮 = B3 and 134 may be provided A less useful transistor area. For example, 13〇1 12 1W f1 ^ 1345'B2 ^ 1345-B3 ^ 1345'B4 1304-12, 1344-1, 1304-13 and 1344-2.

在一些實施方式中，基板接觸點1347七、1347-12、1347_2][、 13^-22、1347-23、…可配置在源極區域13体卜13体2、和134从 的第二區域1345-B卜1345-B2、1345-B3和1345-B4巾的-些或全部 H :或者不位於這些第二區域之中，如圖4m所示。基板接觸點 1347-11 > 1347-12 ^ 1347-21 ^ 1347-22 ^ 1347-23 ^ 狹長源極區域1344-1和1344-2之中，並且傾向於降低rds—on。基 板接觸，1347-11、1347-12、1347_2卜 1347-22、1347-23、二可具有 小於或等於源極區域1304的一寬度“c”（如圖41A所示）的高度以及 小於或等於源極區域1304的一寬度“d”（如圖41A所示）的寬度。 現在參考圖41E，基板接觸點和133〇_2分別設置在一對 狹長源極區域1344_1A #口 1344-1B和-對狹長源極區域1344-2A和 1344-2B之間。狹長源極區域1344_ia和1344-2A由驅動器1346-1A 和1346-2A從侧邊驅動。狹長源極區域13体1β和134冬2B由驅動器 1346-1B和1346-2B從另一侧驅動。In some embodiments, the substrate contact points 1347, 1374-122, 1347_2][, 13^-22, 1347-23, ... can be disposed in the source region 13 body 13 body 2, and 134 from the second region Some or all of the 1345-B Bu 1345-B2, 1345-B3 and 1345-B4 towels are either not located in these second regions, as shown in Figure 4m. Substrate contact points 1347-11 > 1347-12 ^ 1347-21 ^ 1347-22 ^ 1347-23 ^ Among the narrow source regions 1344-1 and 1344-2, and tend to lower rds-on. The substrate contacts, 1347-121, 1347-122, 1347-2, 1347-22, 1347-23, 2, may have a height less than or equal to a width "c" of the source region 1304 (as shown in FIG. 41A) and less than or equal to The width of the source region 1304 is a width "d" (as shown in Figure 41A). Referring now to Fig. 41E, substrate contact points and 133 〇 2 are respectively disposed between a pair of elongated source regions 1344_1A # port 1344-1B and - pair of elongated source regions 1344-2A and 1344-2B. The narrow source regions 1344_ia and 1344-2A are driven from the sides by drivers 1346-1A and 1346-2A. The elongated source regions 13 1 1 and 134 2 2B are driven from the other side by drivers 1346-1B and 1346-2B.

圖41A-41E中的汲極接觸點1344可具有最小尺寸或大於最小尺 寸的一尺寸。汲極接觸點1344可具有簡單或規則的形狀及/或不規則 或複雜的形狀。例如，汲極接觸點1344可以是方形或矩形（如圖41A 37 200847381 處所不）^字形（如圖41F中1344-W處所示;)、：荦草形 (^«410 1334.X,〇w 4m ^ 1334_¥^1-*^ S 域（如圖411中的1334題所示）以及/或者其他適當的 i 不/艮於菱形、圓形、對稱的、非對稱的等等。基板接觸 或不規則歧雜槪1334触賴單或綱的形狀及/ nnf^n2 m4t 2*B*( 接觸Li Λ目i的面積）°例如’ # B等於3時，汲極 1^2、有約大於或等於—個源極接觸點⑶1-1、 311_2 .··或1311-B的面積的ό倍的面積。者B蓉 可具有約大於或等於—個源極^觸點咖+’則士 或1311-B的面積的8倍的面積。 … 極接觸點1334的尺寸树於減難區域⑽辦大，可 二層過程可能不利地影響挪區域及/或下 囬町層马了減I過度蝕刻問題，可以為汲極接觸點m4 在及極接觸點1334之中及/或之下使用深注入離子。 j乍為將基板接觸點1330放置在狹長源極3 ，方式’可以提供-釋放面積（relief ―在un 可放置在釋放面積中。在釋放面積的： ，源極區域U44的形狀，以抵消釋放面 域1344靠近釋放面積的區域中電流密度的減小曰。Ρ方止在狹長源極區 返回參考圖38Β’圖41純1的電晶體佈局中的任何一種老 來取代電晶體佈局1050，，如前所述，並且可 ^^ 連層（I/V/LI)與板狀金屬層（Ρ)和外側接觸⑼U互 所述，外侧接觸點層⑼可與互連結構通信並且/或;:置2 38 200847381 裝中。 用』乍為範例’圖4越中的絕緣/過孔/局部互輕魄i)可 用來k供下面的電晶體佈局（例如圖41A 曰:（ ）了 41C中的雷曰挪洗a nw、 〒的电日日體佈局1300和圖 低甲的包曰曰體佈局1340)和板狀金屬層（ ' 二 在圖4A_4D中张;+、丨人苟曰、^ <間的連接’如上述 二卜侧接觸點層⑼===圖 所= 減小電阻損耗並減小日日日片面積，如以上詳細 述外’電晶體佈局可在圖2所示的功率1C中連接和使用。 也可使關2㈣所示的無配置。 用 4 1 考圖42_44，其中分別顯示出電晶體佈局1347心1347·2 共，地f為1347)。汲極、源極和閘極區域可具有能夠用 f使RDSON敢小化的其他形狀。例如，沒極區域1348可且有圖42 =的電晶體佈局1347·1中所示的圓形形狀，圖43的電晶體佈局1347_2 中所福橢圓形狀及/或其他適當的形狀。閘極區域1349包括與線狀 閘^連接區域1352相連接的圓形閘極區域135〇。在圖43中用'括號 、（）來標識類似的元件。汲極區域1348位於圓形閘極區域135〇中二 源極區域1360位於閘極區域1349之間、除圓形閘極區域1350内部之 ^的區域中。基板接觸點1364位於源極區域136〇中。沒極區域1348 還可包括接觸點區域1366。線狀閘極區域1352可具有被最小化以增 大密度的垂直間距“g”。同樣，在相鄰圓形閘極區域135〇之間被標識 為“f’的橫向間距可被最小化以增大密度。 >及極區域1368也可是多邊形的。例如，沒極區域可以是圖44 的電晶體佈局1347-3中所示的六邊形，但也可使用其他多邊形。閘極 區域1369包括與線狀閘極連接區域丨372相連接的六邊形閘極區域 1370。汲極區域1368位於六邊形閘極區域1370中。源極區域1380 位於閘極區域1369之間，在除六邊形閘極區域1370内部之外的區域 中。基板接觸點1384位於源極區域1380中。汲極區域還可包括接觸 點區域1386。線狀閘極連接區域1372優先具有被最小化以增大密度 39 200847381 的一垂直間距“Γ。同樣地，在相鄰六邊形閘極區 為“i”的橫向間距可被最小化以增大密度。 — 之間被&識 可以意識到’圖42-44中的沒極ϋ域和閘極區域的形 於錄區域的水平中線和垂直中線中的至少 ^ 42-44的電晶體可以是LDM〇s電晶體嘴極區域的 稱的形狀/Jf彡狀可峨著與汲祕域的巾心點的轉增大* ^錐 形及/或隨著與汲極區域的巾心、點的距離在向著—個或多個1他·曰 體的方向上增大而逐漸成錐形。 ^ 八包曰曰 取代電返ΐΓη,’圖42_44 __佈局中的任何—種都可用來 佈局1050 ;如前所述，並且可經由絕緣/過孔 ^外側接咖層⑼可與互連結構通信並 用例’圖4A_4D中的絕緣/過孔/局部互連層⑽LD可 面的電晶體佈局，例如來自圖42-44的電晶_局⑽ ί狀金顧（p)之關連接，如上述在圖4α·®中所 =板H層⑺可與外側接觸點層⑼通信，亦如圖4A-4D中 ΪΪ用點層⑼可與互連結構通信，如圖7所示。這種配 置了用咸小电阻損耗並減小晶片面積，如前詳細所述。 也可#除用電晶體佈局可在圖2所示的一功率IC中連接和使用。 也了使用圖20-33所示的其他配置。 方式現在參考圖45A_45G，顯示了含本發明的教導的各種範例性實現 1· 在I考圖45A’本發明的教導可以實施在一硬碟驅動器（HDD) ism 4、ί u的積體電路（IC)中°HDD 1500包括一硬碟元件（HDA) 1503 /二印刷電路板（PCB) 1502。HDA1501可包括磁性介質 料的入元件1504，其中磁性介質1503是一個或多個儲存資 斜續取/寫入元件1504可被配置在磁頭驅動臂1505上，並且 ^ 貝1503上的資料進行讀取和寫入。此外，HDA1501包括 200847381 旋轉磁性介質1503的主軸馬達脳和磁頭驅動臂 !vcm) 1507。-歧器元件·，在細桑作期間05&取圈= ^ 1504產生的#號進行放大，並且在寫入操作 二_ 件1504提供信號。 N取/冩入το HDD PCB 1502包括-讀取/寫入通道模組（以 ‘ 道，，）1509、一硬碟控制器（HDC)模组151〇、一緩衝器 f性記憶體1512、一處理器1513和一主轴/yCM驅動器模 讀取通道1509對接收自和發送到放大器元件15〇8的資^ 。 且一 1=控.上HDA1501的元件並且經由1/0介面1515 J外部 =備（未不出）通信。外部賴可包括電腦、多媒體裝置、移動 衣置ϋΐ人7輸出⑽）介面1515可包括有線及/或無線通信鏈路二 HDC模組1510可接收來自HDA15〇1、讀取通道15〇9、 1511、 非揮發性記憶體⑸2、處理器1513、主轴驅動器模 1514，及/或輸入/輸出（!/〇)介面1515的資料。處理器Mu可對^資 S處』解碼、濾波及/或格式化。處理後的資料可被 = 严1509、緩肺151卜非揮發性記憶體 1512、 處理态1513、主軸/VCM驅動器模組1514及/或輸入/輸出（ι/〇 介面1515。 HDC模組1510可使用緩衝器1511及/或非揮發性記憶體1512 來儲存與HDD 1500的控制和操作有關的資料。緩衝器1511可包括 DRAM、SDRAM等等。非揮發性記憶體1512可包括快閃記憶體（包 括NAND和NOR快閃記憶體）、相變記憶體、磁阻式隨機存取記情體 ^Magnetic RAM)，或者在其中每個儲存單元具有多於兩種狀態^多 恶Zk體。主軸/VCM驅動器模組1514控制主軸馬達1506和VCM 1507。HDDPCB 1502包括提供hdd 15〇〇元件電力的電源1516。 、現在參考圖45B，本發明的教導可以實施在一 DVD驅動器1518 或一 CD驅動器（未示出）的積體電路（IC)中。DVD驅動器1518 包括一 DVDPCB 1519 和一 DVD 元件（DVDA)152〇cDVDPCB 1519 包括一 DVD控制模組1521、一緩衝器1522、非揮發性記憶體1523、 200847381 二，器1524、1軸/FM (饋送馬達）驅動器模組1525、類比 杈、、且1526、一寫入策略模組1527和一 Dsp模組1528。、 控制模組1521控制DVDA 152〇的元件並且經由⑽介面 移動信。外部裝置可包括細、多媒體裝置、 移動心*置料。I/O”面1529可包括有線及/或無線通信鏈路。 DVD控制模組1521可接收來自緩衝器1522 _揮 T、處理器主轴/FM (饋送馬達）驅動器模組 ^亡組1526、寫入策略模組1527、Dsp模組1528,及/或^^ 、15 。處理益1524可對資料進行處理’包括'編碼、解碼、遽波及/ ° DSP模組1528執行信號處理，例如視頻及/或音頻^碼/解 碼三處理後的貧料可被輸出到緩衝器1522、非揮發性記憶體1523、處 理為1524、主軸/FM驅動器模組1525、類比前端模組1526、寫入籃 略模組1527、DSP模組1528及/或I/O介面1529。 ··、 DVD控制模組1521可使用緩衝器1522及/或非揮發 1523以儲存與DVD .驅動器1518的控制 :: ⑸2可包括DRAM、SD讀料。非揮發性記憶體可 閃挹憶體（包括NAND和NOR快閃記憶體）、相變記憶體、磁阻式隨 機存取記憶體（Magnetic RAM)，或者在其中每個儲存單元具有多於 兩種狀態的多態記憶體。DVD PCB 1519包括提供DVD驅動^ 1518 元件電力的電源1530。 …DVDA1520可包括一放大器元件1531、一雷射驅動器1532和一 光夺元件1533，该一光學元件1533可以是光學讀取/寫入（〇RW)元 件或光學唯讀取（OR)元件。一主軸馬達1534旋轉光學儲存介質 1535，並且一饋送馬達(fm)1536相對於光學儲存介質1535促動光^ 元件1533。 當從光學儲存介質1535讀取資料時，雷射驅動器向光學元件 1533提供讀取功率。光學元件1533檢測來自光學儲存介質1535的資 料’並且將資料發送到放大器元件1531。類比前端模組1526接收來 自放大器元件1531的資料，並且執行諸如濾波和a/D轉換之類的功 42 200847381 能。為了向光學儲存介質1535進行寫入，寫入策略模組1527向雷射 驅動器1532發送功率層和定時資料。雷射驅動器1532控制光學元件 1533 ’以將資料寫入到光學儲存介質1535。 現在參考圖45C，本發明的教導可以實施在高晝質數位電視 (HDTV) 1537的積體電路（ic)中。HDTV 1537包括一HDTV控制 模組1538、一顯示器1539、一電源1540、記憶體1541、一儲存裝置 1542、一網路介面1543以及一外部介面1545。如果網路介面1543包 括一無線區域網路介面，則可以包括天線（未示出）。 HDTV 1537可以接收來自網路介面1543及/或外部介面1545的 輸入信號，網路介面1543及/或外部介面1545可以經由電、寬頻網 際網路及/或衛星發送和接收資料。HDTV控制模組1538可對輸入信 號進行處理，包括編碼、解碼、濾波及/或格式化，並產生輸出信號。 輸出信號可被傳輸到顯示器1539、記憶體1541、儲存裝置154^、%罔 路介面1543和外部介面1545中的一個或多個。 記憶體1541可包括隨機存取記憶體（ram)及/或非揮發性記憶 體，例如快閃δ己丨思體、相變記憶體或其中每個儲存單元具有多於兩種 狀，的多態記憶體。儲存裝置1542可包括光儲存裝置（例如DVD驅 動器）及/或硬碟驅動器（HDD)。HDTV控制模組1538經由網路介面 1543及/或外部介面1545與外部通信。電源1540向HDTV 1537的 件提供電力。 現在參考圖45D，本發明的教導可以實施在一車輛1546的積體 電路（1C)中。車輛1546可包括一車輛控制系統1547 ' 一電源1548、 記憶體1549、一儲存裝置1550以及一網路介面1552。如果網路介面 1552/包括一無線區域網路介面，則可以包括天線（未顯示出）。車輛 控，系統1547可以是一傳動系控制系統、一車體控制系統、一娛樂控 制系統、一防鎖死剎車系統（ABS)、一導航系統、一無線資料通| 統、一車道偏離系統、一主動車距控制巡航系統等。 〜、 車輛控制系統1547可與一個或多個感測器1554通信並產生一個 或多個輸出信號1556。感測器1554可包括溫度感測器、加速度感測 43 200847381 器、壓力感測器、旋轉感測器、氣流感測器等等。輸出信號1556可控 制引擎工作參數、傳動工作參數、懸吊參數等。 二電源1548向車輛1546的元件提供電力。車輛控制系統1547可 憶體1549及/或儲存裝置1550中儲存資料。記憶體1549可包括 幾存取記憶體（RAM)及/或非揮發性記憶體，例如快閃記憶體、相 變^憶體或其中每個儲存單元具有多於兩種狀態的多狀態記憶體。儲 ，裝置1550可包括一光學儲存（例如DVD驅動器）及/或一硬碟驅動 裔（HDD):車輛控制系統1547可利用網路介面1552與外部通信。 現在參考圖45E，本發明的教導可以實施在行動電話1558的積 體電路（ic)中。行動電話1558包括一電話控纖、组156〇、一電源 15=、記憶體1564、一儲存裝置1566以及一行動網路介面1567。行 ，電話1558可包括-網路介面1568、一麥克風157〇、一音頻輸出1572 (例如揚聲器及/或輸出插孔）、一顯示器1574和一使用者輸入1576 ^例如鍵盤及域點擊裝置）。如果網路介面1568包括一無線區域網路 w面，則可包括天線（未顯示出）。 電話控制模組1560可接收來自行動網路介面1567 '網路介面 巧8、麥克風1’及/或使用者輸入裝置㈣的輸入信號。電話控制 =1560可對信號進行處理，包括編碼、解碼、驗及/或格式化， 亚產生輸出信號。輸出信號可被傳輸到記憶體1564、儲存裝置1566、 行動網路 1 介面1567、網路介面1568和音頻輸出1572中的一個或多個。 記憶體1564可包括隨機存取記憶體（RAM)及/或非揮發性記憶 妝丄記憶體、相變記憶體或其中每個儲存單元具有多於兩種 2記憶體。儲存裝置1566可包括—光儲存裝置（例如励 碟驅動器（HDD)。電源1562向行動電話1558的 電路在Λ1 圖本發明的教導可以實施在機頂盒1578的積體 干^ if中 機頂盒1578包括一機頂盒控制模、组_、一顯 S =、Ιΐ源1582、記憶體1583、一儲存裝置1584以及一網路 面1585。如果網路介面1585包括一無線區域網路介面，則可包括 44 200847381 天線（未表示出）。 機頂盒控制模組1580可以接收來自網路介面1585和外 1587的輸入信號，網路介面1585和外部介面1587可以經由電豐、嘗 頻網際網路及/或衛星發秘桃簡。機㈣齡刪可 號進行處理，包括編碼、解碼、濾波及/或格式化，並產生輸出信： 輸出Μ可包括鮮及/或高清晰格柄音頻及域視頻錢。輸出作费 可被傳輸到網路介面1585及/或顯示器1581。顯示器1581可二雷υ 視、一投影機及/或一監視器。 电 電源1582向機頂盒1578的元件提供電力。記憶體1583 機存取記憶體（讀）及/或非揮發性記憶體，例如賴記憶體、^ =憶體或其巾每雜存單元具衫於兩雛態的多狀態記憶體。儲 存設，腦可包括-光學儲存裝置（例如DVD驅動器〕及/或一硬碟 驅動裔（HDD )。 触+ f在參考圖45G，本發明的教導可以實施在行動裝置腳的積 =路（ic) t。行動裝置1589可包括一行動裝置控麵組159〇、 -電源159卜記憶體1592、-齡裝置1593、—網路介面1594以及 ，部介面1599。如果網路介面1594包括一無線區 行動裝置控麵組1590可以接收來自網路介面1594及/或外部介 ί 15Γ的信號。外部介面1599可包括usb、紅外線及/或乙太網 雨入仏^可包括經壓縮的音頻及/或視頻，並且可以符合MP3格 ϋ外’行動裝置控制模組1590可以接收來自諸如鍵盤、觸控板或 η二按Ϊ之使用者輸入1596的輸入。行動裝置控制模組1590可 =理輸入# 5虎（包括編碼、解碼、過濾及/或格式化），並產生輸出 1吕號0 哭組i590可向音頻輸出1597輸出音頻信號和顯示 i t 就。音頻輸出1597可包括揚聲器及/或輸出插孔。 呈現圖形使用者介面，該介面可包括功能表、圖示等 等電源1591向行動裝置1589的元件提供電力。 45 200847381 4¼體1592可包括隨機存取記憶體及/或非揮發性圮，㊅ 體二例如快閃記㈣、相變記憶誠其巾每個儲存單元财多於兩^ 狀恝的多恶記憶體。儲存裝置1593可包括一光學儲存裝置（例如DVD 驅動器）及/或-硬碟驅動器（HDD)。行動裝置可包括—個人數位助 理器、一媒體播放器、一膝上型電腦、一遊戲機或其他行動計算裝置。 本領域技術人員現在可以從前述描述中意識到，本公開的廣 導可以以多種形式實現。因此，儘管該公開包括了特定示例，但是 公開的真實範圍不應當受限於此，因為本領域技術人員將清 r 附圖、s兒明書和申請專利範圍之後的其他修改。 【圖式簡單說明】 從附圖中詳細描述和充分地了解本發明： 囷A疋具有弟和弟一互連的電晶體的第一範例性功率ic的電路 圖， 圖1B是具有第一和第二互連的電晶體的第二範例性功率汜的電路 圖2 =連接到驅動IC的圖丨功率IC的電路圖和功能方塊圖； 圖3是功率ic的頂部金屬層的第一佈局的平面圖； f4A為依據本發明的功率汇佈局的截面圖，針對圖ia 截面圖是沿著圖3中的A-A取得的； 、 圖4B為依據本發明的功率妃佈局的截面圖，針對圖ΐβ功率I。的 截面 圖是沿著圖3中的A_A取得的； 白^截^依據本發明的替換功率1C佈局的截面圖，針對圖1A功率1C 面圖是沿著圖3中的A-A取得的； 圖5A是說明圖ία的功率Ic的電路圖； 圖5B是說明圖iB的功率Ic的電路圖； 46 200847381 圖6A-6D是圖4和5中的功率ic的頂部金屬層的替換佈局之 圖7是說明第一範例性互連結構的層之截面圖； 回’ 圖8A是說明圖7的互連結構的頂部金屬層之平面圖； 圖8B是說明互連結構的頂部金屬層和IC的頂部金屬層的對齊之平 δ 圖； 圖9是圖7的互連結構的電介質層之平面圖； 圖10是圖7的互連結構的金屬層之平面圖； ,3 的互連結構的阻焊層（S°ldermaSklayer)之平面圖； 圖12 #兄明圖7_11所示的層的對齊和定向； 圖13說明第二範例性互連結構的層； =4是具有鍍通孔（PTH)的核心電介質層之平面圖； 目圖5现明核心電介質層（在底部顯示出）的錢通孔（簡）與類似 1〇所示的層之額外金屬層（在頂部顯示幻的對齊； 質層（與圖 9 圖16 .兒明圖is的金屬層（在底部顯示出）與額外的電介The drain contact 1344 of Figures 41A-41E can have a minimum size or a size greater than the minimum size. The bungee contact 1344 can have a simple or regular shape and/or an irregular or complex shape. For example, the bungee contact 1344 may be square or rectangular (as shown in FIG. 41A 37 200847381). (as shown at 1344-W in FIG. 41F;): 荦 形 (^«410 1334.X, 〇 w 4m ^ 1334_¥^1-*^ S domain (shown as 1334 in Figure 411) and / or other suitable i not / rhombic, circular, symmetrical, asymmetrical, etc. substrate contact Or irregular 槪 1334 lie to the shape of a single or a class and / nnf ^ n2 m4t 2 * B * (area of contact Li i i) ° For example, when # B is equal to 3, the bungee 1^2, about Greater than or equal to the area of the source contact point (3) 1-1, 311_2 . . . or 1311-B ό times the area. B Rong can have about greater than or equal to - a source ^ contact coffee + 'shishi Or 8 times the area of the 1311-B area. ... The size of the pole contact point 1334 is large in the area of the distressed area (10), but the second layer process may adversely affect the area of the area and/or the lower back of the town. For etching problems, deep implanted ions may be used for the drain contact m4 and/or under the contact 1334. j乍 is to place the substrate contact 1330 at the narrow source 3, the mode 'may be provided - The area of relief - in which the un can be placed in the release area. In the area of the release area: the shape of the source region U44, to offset the decrease in current density in the region of the release area 1344 near the release area. The narrow source region returns to reference any of the transistor layouts of Fig. 38 Β 'Fig. 41 pure 1 to replace the transistor layout 1050, as described above, and can be connected (I/V/LI) with the board. The metal layer (Ρ) and the outer contact (9) U are mutually described, and the outer contact layer (9) can communicate with the interconnect structure and/or; 2: 2008. Via/local mutual 魄i) can be used for the following transistor layout (for example, Figure 41A 曰: ( ), Thunder, a nw in 41C, 电 电 电 1300 1300 and 1300 The package body layout 1340) and the plate-like metal layer ('two in Figure 4A_4D Zhang; +, 丨人苟曰, ^ < connection' as the above two side contact point layer (9) === figure = Reducing the resistance loss and reducing the area of the day and the day, as detailed above, the 'transistor layout can be connected in the power 1C shown in Figure 2. It can also be used to disable the configuration shown in Figure 2 (4). Use 4 1 to test Figure 42_44, which shows the crystal layout 1347 heart 1347·2 total, ground f is 1347). The drain, source and gate regions can be There are other shapes that can minimize the RDSON with f. For example, the non-polar region 1348 can have the circular shape shown in the transistor layout 1347·1 of Fig. 42, and the transistor layout of Fig. 43 is blessed in 1347_2. Elliptical shape and / or other suitable shape. The gate region 1349 includes a circular gate region 135A connected to the linear gate connection region 1352. In Fig. 43, similar elements are identified by 'brackets, (). The drain region 1348 is located in the circular gate region 135, where the two source regions 1360 are located between the gate regions 1349, except for the interior of the circular gate region 1350. The substrate contact 1364 is located in the source region 136A. The non-polar region 1348 can also include a contact point region 1366. The linear gate region 1352 may have a vertical pitch "g" that is minimized to increase density. Likewise, the lateral spacing identified as "f' between adjacent circular gate regions 135A can be minimized to increase density. > and the polar regions 1368 can also be polygonal. For example, the non-polar region can be The hexagon shown in the transistor layout 1347-3 of Fig. 44, but other polygons may be used. The gate region 1369 includes a hexagonal gate region 1370 connected to the linear gate connection region 372. The pole region 1368 is located in the hexagonal gate region 1370. The source region 1380 is located between the gate regions 1369 in a region other than the interior of the hexagonal gate region 1370. The substrate contact 1384 is located in the source region 1380. The drain region may also include a contact region 1386. The linear gate connection region 1372 preferably has a vertical pitch "Γ" that is minimized to increase the density 39 200847381. Similarly, the lateral spacing of "i" in the adjacent hexagonal gate region can be minimized to increase density. - the transistor between the horizontal center line and the vertical center line of the recorded area of the infinite region and the gate region of Fig. 42-44 can be realized by & The shape of the LDM 〇s transistor's mouth is called /Jf 彡 峨 峨 峨 峨 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ The distance is gradually tapered toward the direction of one or more of the other. ^ Eight packs of 曰曰 电 电 电 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Communication and use of the insulation/via/local interconnect layer (10) LD facet transistor layout in Figures 4A-4D, such as the gate connection from Figure 42-44, such as the above In Fig. 4α·®, the plate H layer (7) can communicate with the outer contact layer (9), and the dot layer (9) can also communicate with the interconnect structure as shown in Fig. 4, as shown in Fig. 7. This configuration uses a small salt resistance loss and reduces the wafer area, as described in detail above. Alternatively, the transistor layout can be connected and used in a power IC as shown in FIG. 2. Also use the other configurations shown in Figure 20-33. Modes Referring now to Figures 45A-45G, various exemplary implementations incorporating the teachings of the present invention are shown. 1. The teachings of the present invention can be implemented in a hard disk drive (HDD) ism 4, ί u integrated circuit ( IC) Medium HDD 1500 includes a hard disk component (HDA) 1503 / two printed circuit board (PCB) 1502. The HDA 1501 can include an in-component 1504 of magnetic media, wherein the magnetic media 1503 is one or more storage reclining/writing elements 1504 can be disposed on the head drive arm 1505, and the data on the die 1503 can be read. And write. In addition, the HDA 1501 includes a spindle motor 2008 and a head drive arm !vcm) 1507 of the 200847381 rotating magnetic medium 1503. - The dissipator element is amplified by the ## generated by the circle & = 1504 during the fine mulberry operation, and the signal is supplied in the write operation ii 1504. N fetch/input το HDD PCB 1502 includes - read/write channel module (by 'channel, ') 1509, a hard disk controller (HDC) module 151 〇, a buffer f-memory memory 1512 A processor 1513 and a spindle/yCM driver mode read channel 1509 are received and sent to the amplifier elements 15A8. And 1 = control the upper HDA1501 components and communicate via the 1/0 interface 1515 J external = standby (not out). The external device may include a computer, a multimedia device, and a mobile device 7 output (10) interface 1515 may include a wired and/or wireless communication link. The HDC module 1510 can receive from the HDA 15 〇 1, the read channel 15 〇 9, 1511 , non-volatile memory (5) 2, processor 1513, spindle driver module 1514, and / or input / output (! / 〇) interface 1515 information. The processor Mu can decode, filter and/or format the information. The processed data can be = 严1509, slow lung 151 non-volatile memory 1512, processing state 1513, spindle / VCM driver module 1514 and / or input / output (ι / 〇 interface 1515. HDC module 1510 can The buffer 1511 and/or non-volatile memory 1512 is used to store data related to the control and operation of the HDD 1500. The buffer 1511 may include DRAM, SDRAM, etc. The non-volatile memory 1512 may include flash memory ( Including NAND and NOR flash memory, phase change memory, magneto-resistive random access memory (Magnetic RAM), or in each of the memory cells has more than two states ^ multi-Zh body. The spindle/VCM driver module 1514 controls the spindle motor 1506 and the VCM 1507. The HDD PCB 1502 includes a power supply 1516 that provides power to the HDD 15 〇〇 component. Referring now to Figure 45B, the teachings of the present invention can be implemented in an integrated circuit (IC) of a DVD drive 1518 or a CD drive (not shown). The DVD drive 1518 includes a DVDPCB 1519 and a DVD component (DVDA) 152〇cDVDPCB 1519 including a DVD control module 1521, a buffer 1522, a non-volatile memory 1523, 200847381, a 1524, a 1 axis/FM (feed) The motor) driver module 1525, analogy, and 1526, a write strategy module 1527, and a Dsp module 1528. The control module 1521 controls the components of the DVDA 152 and transmits the signal via the (10) interface. External devices may include thin, multimedia devices, mobile heart*s. The I/O" face 1529 can include a wired and/or wireless communication link. The DVD control module 1521 can receive from the buffer 1522 _ wave T, the processor spindle / FM (feed motor) driver module ^ 15 group, write Into the policy module 1527, Dsp module 1528, and / or ^ ^, 15. Processing benefits 1524 can process the data 'including' encoding, decoding, chopping and / ° DSP module 1528 to perform signal processing, such as video and / Or the audio code/decode three processed poor material can be output to the buffer 1522, the non-volatile memory 1523, the processing 1524, the spindle/FM driver module 1525, the analog front end module 1526, and the write basket mode. Group 1527, DSP module 1528 and/or I/O interface 1529. The DVD control module 1521 can use buffer 1522 and/or non-volatile 1523 to store and control DVDs. Driver 1518: (5) 2 can include DRAM , SD reading material. Non-volatile memory can flash memory (including NAND and NOR flash memory), phase change memory, magneto-resistive random access memory (Magnetic RAM), or in each of them The unit has more than two states of polymorphic memory. DVD PCB 1519 includes DVD The power supply 1530 of the component power supply 1530. The DVDA 1520 may include an amplifier component 1531, a laser driver 1532, and a light-trapping component 1533, which may be an optical read/write (〇RW) component or optical A read only (OR) component. A spindle motor 1534 rotates the optical storage medium 1535, and a feed motor (fm) 1536 activates the optical component 1533 with respect to the optical storage medium 1535. When reading data from the optical storage medium 1535, The laser driver provides read power to the optical element 1533. The optical element 1533 detects the material from the optical storage medium 1535 and sends the data to the amplifier element 1531. The analog front end module 1526 receives the data from the amplifier element 1531 and performs such filtering. And work such as a/D conversion 42 200847381. In order to write to the optical storage medium 1535, the write strategy module 1527 sends the power layer and timing data to the laser driver 1532. The laser driver 1532 controls the optical element 1533' To write the data to the optical storage medium 1535. Referring now to Figure 45C, the teachings of the present invention can be implemented at high prime digits. The HDTV 1537 includes an HDTV control module 1538, a display 1539, a power supply 1540, a memory 1541, a storage device 1542, a network interface 1543, and an external interface. 1545. If the network interface 1543 includes a wireless local area network interface, an antenna (not shown) may be included. The HDTV 1537 can receive input signals from the network interface 1543 and/or the external interface 1545. The network interface 1543 and/or the external interface 1545 can transmit and receive data via electrical, broadband internet and/or satellite. The HDTV control module 1538 can process the input signal, including encoding, decoding, filtering, and/or formatting, and produce an output signal. The output signal can be transmitted to one or more of display 1539, memory 1541, storage device 154, % interface 1543, and external interface 1545. The memory 1541 may include random access memory (ram) and/or non-volatile memory, such as flash δ 丨 丨 、, phase change memory or each of the storage units having more than two shapes, State memory. The storage device 1542 can include an optical storage device (e.g., a DVD drive) and/or a hard disk drive (HDD). The HDTV control module 1538 communicates with the outside via the network interface 1543 and/or the external interface 1545. Power supply 1540 provides power to the components of HDTV 1537. Referring now to Figure 45D, the teachings of the present invention can be implemented in an integrated circuit (1C) of a vehicle 1546. The vehicle 1546 can include a vehicle control system 1547', a power source 1548, a memory 1549, a storage device 1550, and a network interface 1552. If the network interface 1552/ includes a wireless local area network interface, an antenna (not shown) may be included. The vehicle control system 1547 can be a powertrain control system, a vehicle body control system, an entertainment control system, an anti-lock brake system (ABS), a navigation system, a wireless data communication system, a lane departure system, An active distance control cruise system, etc. The vehicle control system 1547 can communicate with one or more sensors 1554 and generate one or more output signals 1556. The sensor 1554 can include a temperature sensor, an acceleration sensor 43 200847381, a pressure sensor, a rotation sensor, a gas flu detector, and the like. The output signal 1556 can control engine operating parameters, transmission operating parameters, suspension parameters, and the like. A second power source 1548 provides power to the components of the vehicle 1546. The vehicle control system 1547 can store data in the memory 1549 and/or the storage device 1550. The memory 1549 may include several access memory (RAM) and/or non-volatile memory, such as a flash memory, a phase change memory, or a multi-state memory in which each storage unit has more than two states. . The storage device 1550 can include an optical storage (e.g., a DVD drive) and/or a hard disk drive (HDD): the vehicle control system 1547 can communicate with the outside using the network interface 1552. Referring now to Figure 45E, the teachings of the present invention can be implemented in an integrated circuit (ic) of a mobile telephone 1558. The mobile phone 1558 includes a telephone control fiber, a group 156, a power source 15=, a memory 1564, a storage device 1566, and a mobile network interface 1567. The line 1558 can include a network interface 1568, a microphone 157A, an audio output 1572 (e.g., a speaker and/or output jack), a display 1574, and a user input 1576 (e.g., a keyboard and a domain pointing device). If the network interface 1568 includes a wireless local area network w-area, an antenna (not shown) may be included. The telephone control module 1560 can receive input signals from the mobile network interface 1567 'network interface 8, microphone 1' and/or user input device (4). The telephone control =1560 can process the signal, including encoding, decoding, checking and/or formatting, and sub-generating the output signal. The output signal can be transmitted to one or more of memory 1564, storage device 1566, mobile network 1 interface 1567, network interface 1568, and audio output 1572. The memory 1564 can include random access memory (RAM) and/or non-volatile memory memory, phase change memory, or each of the memory cells having more than two types of memory. The storage device 1566 can include an optical storage device (eg, a dish drive (HDD). The power supply 1562 is directed to the mobile phone 1558. The teachings of the present invention can be implemented in the set top box 1578. The set top box 1578 includes a set top box. Control mode, group_, one display S =, power source 1582, memory 1583, a storage device 1584, and a network plane 1585. If the network interface 1585 includes a wireless local area network interface, it may include 44 200847381 antenna (not The set top box control module 1580 can receive input signals from the network interface 1585 and the outer 1587. The network interface 1585 and the external interface 1587 can be sent via the eF, the Internet, and/or the satellite. The machine (4) age deletes the number, including encoding, decoding, filtering and/or formatting, and produces an output message: the output port may include fresh and/or high-definition handle audio and domain video money. The output fee may be transmitted. To the network interface 1585 and/or display 1581. The display 1581 can be used for two radars, a projector, and/or a monitor. The electrical power source 1582 provides power to the components of the set top box 1578. 1583 machine access memory (read) and / or non-volatile memory, such as reliance memory, ^ = memory or its towel, each memory unit has a multi-state memory in two states. Storage, brain Included may be - an optical storage device (e.g., a DVD drive) and/or a hard disk drive (HDD). Touch + f Referring to Figure 45G, the teachings of the present invention may be implemented at the mobile device foot product = road (ic) t. The mobile device 1589 can include a mobile device control panel 159, a power supply 159, a memory 1592, an ageing device 1593, a network interface 1594, and a portion interface 1599. If the network interface 1594 includes a wireless zone mobile device control The quilt 1590 can receive signals from the network interface 1594 and/or external interface. The external interface 1599 can include usb, infrared, and/or Ethernet rain, and can include compressed audio and/or video, and The mobile device control module 1590 can be configured to receive input from a user input 1596 such as a keyboard, a touchpad, or a two-button press. The mobile device control module 1590 can be a logical input #5 tiger (including Encoding, decoding, filtering, and/or grid The output of the crying group i590 can output an audio signal and display it to the audio output 1597. The audio output 1597 can include a speaker and/or an output jack. The graphical user interface is presented, the interface can include functions The power supply 1591 provides power to the components of the mobile device 1589. 45 200847381 41⁄4 body 1592 may include random access memory and/or non-volatile germanium, six-body two such as flash (four), phase change memory Each storage unit of the towel has more than two scorpions of polymorphic memory. The storage device 1593 can include an optical storage device (eg, a DVD drive) and/or a hard disk drive (HDD). The mobile device can include a personal digital assistant, a media player, a laptop, a gaming machine, or other mobile computing device. Those skilled in the art can now appreciate from the foregoing description that the disclosure of the present disclosure can be implemented in various forms. Therefore, although the disclosure includes specific examples, the true scope of the disclosure should not be limited thereto, as those skilled in the art will clarify the drawings, the description of the invention, and other modifications after the scope of the claims. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be described and fully understood from the drawings: 囷A疋 has a circuit diagram of a first exemplary power ic of a brother and an interconnected transistor, and FIG. 1B has the first and the first Second exemplary power 汜 circuit of two interconnected transistors Figure 2 = circuit diagram and functional block diagram of the diagram power IC connected to the driver IC; Figure 3 is a plan view of the first layout of the top metal layer of power ic; f4A For a cross-sectional view of the power sink layout in accordance with the present invention, a cross-sectional view for Figure ia is taken along AA in Figure 3; and Figure 4B is a cross-sectional view of a power 妃 layout in accordance with the present invention for Figure 功率β Power I. The cross-sectional view taken along A_A in FIG. 3; the cross-sectional view of the alternative power 1C layout according to the present invention, and the power 1C surface view of FIG. 1A taken along AA in FIG. 3; FIG. Is a circuit diagram illustrating the power Ic of the diagram ία; FIG. 5B is a circuit diagram illustrating the power Ic of the diagram iB; 46 200847381 FIGS. 6A-6D are alternate layouts of the top metal layer of the power ic of FIGS. 4 and 5, FIG. A cross-sectional view of a layer of an exemplary interconnect structure; FIG. 8A is a plan view illustrating a top metal layer of the interconnect structure of FIG. 7; FIG. 8B is a view illustrating alignment of a top metal layer of the interconnect structure and a top metal layer of the IC Figure 9 is a plan view of the dielectric layer of the interconnect structure of Figure 7; Figure 10 is a plan view of the metal layer of the interconnect structure of Figure 7; 3, the solder mask of the interconnect structure (S°ldermaSklayer) Figure 12 shows the alignment and orientation of the layers shown in Figure 7_11; Figure 13 illustrates the layer of the second exemplary interconnect structure; = 4 is a plan view of the core dielectric layer with plated through holes (PTH); Figure 5 shows the core dielectric layer (shown at the bottom) of the money through hole (simplified) and An additional layer of metal similar to the layer shown in Figure 1 (showing a magical alignment at the top; a layer of metal with a metal layer (shown at the bottom) and an additional dielectric

Cvia) ; 圖17疋為明金屬層的平面圖； 層0(在兄觸16的電介質層（在底部顯示出）的過孔與圖Π的金屬 頂部顯示出）的對齊； =19說明圖18的層與圖u的阻焊 實:2。和21說明互連結構的頂部金屬堆積層、_叩_的替換 例； 其回具22和23疋互連結制部分截_(沿著圖 圖 8B中的B-B取得）， 47 200847381 有附屬到圖8B的互連結構的解辆電容器。 圖24A、24B和24C說明了可配置在互連姓椹 器 逆、、、°耩上的各種範例性的散熱 (head sink)； 圖25A和25B說明了包括銘基材的互連結構； 圖26說明了具有銘基材的替換互連結構； 的圖退和27B分別是具有絲材的互連結構的第二雜範例性佈局 平面圖和截面圖（沿著圖27A中的線C_C取彳曰）· 的圖平微和湖分別是具有銘基材的互連結構^三替換範例性佈局 面圖和截面圖（沿著圖27B中的線D-D取得）； 圖29A是另一範例性功率IC的電路圖 圖 面 _口 29C是包括連接到圖29A的功率lc的傳輸線的導線架的平 圖； 圖30A是另一範例性功率IC的電路圖； 圖30B是包括連接到圖3〇A的功率Ic 圖是包細於另—範讎轉IC的輪線 的 另一導線架的平面圖； 圖32A，另一範例性功率忙的電路圖； 平面圖； ^ Ξ H是在源極中主體的第—範例性佈局的電晶體. 蜜圖3犯疋包括平面圖中間極對齊的主體的第二範例的電晶 48 200847381 圖35是包括配置在源極中的主體的第二範例性佈局的電晶體； 圖36是包括配置在源極中的主體的第三範例性佈局的電晶體； 圖37是包括配置在源極巾的主體的第四範例性佈局的電晶體； 圖38A是包括配置在源極中的主體的第五範例性佈局的電晶體； 圖38B說明配置有板狀金屬層、絕緣/過孔/局部互連層和互連結構的 圖 34A-38A的電晶體； 圖39是依據習之技術的PM0S電晶體的截面圖； 圖40是包括井區基板接觸點的第六範例性佈局的平面圖； 圖41A疋用於減小Rd—的第七範例性佈局的平面圖； 圖41B是圖41A的第七範例性佈局的平面圖； 圖41C疋用於減小知—的第八範例性佈局的平面圖； 圖41D是類似於圖41C的用於減小RDS〇n的第九範例性佈局的平面 圖； 圖.41E是類似於圖41C的用於減小RDS〇n的第十範例性佈局的平面 圖； 圖41F-41I說明其他的範例性汲極接觸點； 圖42疋用於減小RDS(>n的第^^一範例性佈局的平面圖；以及 圖43疋用於減小RDS()n的第十二範例性佈局的平面圖； 圖44疋用於減小知―的第十三範例性佈局的平面圖； 圖45A是硬碟驅動器的功能方塊圖； 圖45B是DVD驅動器的功能方塊圖； 圖45C是高畫質數位電視的功能方塊圖； 圖45D是車輛控制系統的功能方塊圖； 圖45E是行動電話的功能方塊圖； 圖45F是機頂盒的功能方塊圖；以及 圖45G是媒體播放器的功能方塊圖。 【主要元件符號說明】 49 200847381 10、20、54 功率 IC 12 第一功率電晶體 14 第二功率電晶體 22 第一功率電晶體 24 第二功率電晶體 26 元件Cvia); Figure 17 is a plan view of the metal layer; layer 0 (the via of the dielectric layer of the brother 16 (shown at the bottom) is aligned with the top of the metal of the figure); =19 illustrates the The solder resist of the layer and the figure u: 2. And 21 illustrate an alternative form of the top metal buildup layer of the interconnect structure, _叩_; its return 22 and 23疋 interconnected portion cut _ (taken along BB in Figure 8B), 47 200847381 attached to the figure 8B's interconnect structure for the capacitors. 24A, 24B, and 24C illustrate various exemplary head sinks that can be placed on the interconnect, ;, 、, ;; 25A and 25B illustrate interconnect structures including the inscription substrate; 26 illustrates a replacement interconnect structure having a substrate; FIG. 27B is a second miscellaneous layout plan view and cross-sectional view of the interconnect structure having wires (taken along line C_C in FIG. 27A). Fig. 29A is another exemplary power IC, which is an interconnected structure with an inscription substrate, respectively, and an alternative layout layout and cross-sectional view (taken along line DD in Fig. 27B); The circuit diagram port 29C is a plan view of a lead frame including a transmission line connected to the power lc of FIG. 29A; FIG. 30A is a circuit diagram of another exemplary power IC; and FIG. 30B is a power Ic including the connection to FIG. Figure is a plan view of another lead frame that is thinner than the other wheel of the IC; Figure 32A, another exemplary power busy circuit diagram; plan view; ^ Ξ H is the first example of the body in the source Layout of the transistor. Honey Figure 3 is the first part of the body that is aligned in the middle of the plan Exemplary Electro-Crystals 48 200847381 FIG. 35 is a transistor including a second exemplary layout of a body disposed in a source; FIG. 36 is a transistor including a third exemplary layout of a body disposed in a source; FIG. Is a transistor including a fourth exemplary layout of the body of the source wiper; FIG. 38A is a transistor including a fifth exemplary layout of the body disposed in the source; FIG. 38B illustrates that a plate metal layer is disposed, FIG. 39 is a cross-sectional view of a PMOS transistor in accordance with the prior art; FIG. 40 is a sixth example of a substrate contact point including a well region; FIG. FIG. 41A is a plan view of a seventh exemplary layout for reducing Rd— FIG. 41B is a plan view of the seventh exemplary layout of FIG. 41A; FIG. 41C is an eighth example for reducing knowledge. FIG. 41D is a plan view similar to FIG. 41C for reducing the ninth exemplary layout of RDS〇n; FIG. 41E is a tenth exemplary example for reducing RDS〇n similar to FIG. 41C. Plan view of the layout; Figure 41F-41I illustrates other example FIG. 42 is a plan view for reducing the first exemplary layout of the RDS (>n; and FIG. 43A is a plan view for reducing the twelfth exemplary layout of the RDS()n; Figure 44 is a plan view of a thirteenth exemplary layout for reducing the knowledge; Figure 45A is a functional block diagram of the hard disk drive; Figure 45B is a functional block diagram of the DVD drive; Figure 45C is a function of the high quality digital television; Figure 45D is a functional block diagram of the vehicle control system; Figure 45E is a functional block diagram of the mobile phone; Figure 45F is a functional block diagram of the set top box; and Figure 45G is a functional block diagram of the media player. [Description of main component symbols] 49 200847381 10, 20, 54 Power IC 12 First power transistor 14 Second power transistor 22 First power transistor 24 Second power transistor 26 Components

30 驅動1C 130 頂部金屬層 130_1 〜130-N、200、210、220、230 接觸點部分30 drive 1C 130 top metal layer 130_1 ~ 130-N, 200, 210, 220, 230 contact point

131 絕緣材料 72、82、164、167 没極 74、84、163、168 源極 76、88、162、166 閘極 90、94、100、104、114、120、140、144、150、160、172、304、 306、308、310-1、310-2〜310-8、304,、306,、308,、310-Γ、310-2,〜 310-8’ 過孔 98 110、124、171 110-2、124-2 110-1 ^ 1244 134 180-1 〜180_M 182-1 〜182-P 186-1 〜186-Q 188-1 〜188-R 204、214、264 202、212、262 236、600、630 242 局部互連 板狀金屬層 第二板狀部份 第一板狀部份 絕緣層 電晶體 電晶體 電晶體 電晶體 274基部 272翼 、650、700、908 第二金屬層 950互連結構 50 200847381 244、252 電介質層 246-卜 246_2、246-N 過孔 250 252 254、474 260 270 280 第一金屬層 防焊膜 、620焊球 第一板狀接觸點部份 第二板狀接觸點部份 第三板狀接觸點部份 284、284-1、284-2〜284-8額外的接觸點部份 320、400 324、404 326、406 320， 324’ 326， 第一板狀導電部分 第二板狀導電部分 第三板狀導電部分 第一部分 第二部分 第三部分 330-1、330-2、330-3〜330-8、410、410-1 〜410-8 額外的板狀導電 部分 340-1、340-2〜340_16 孔 348 基板131 insulating material 72, 82, 164, 167 poles 74, 84, 163, 168 source 76, 88, 162, 166 gates 90, 94, 100, 104, 114, 120, 140, 144, 150, 160, 172, 304, 306, 308, 310-1, 310-2 to 310-8, 304, 306, 308, 310-Γ, 310-2, ~ 310-8' via 98 110, 124, 171 110-2, 124-2 110-1 ^ 1244 134 180-1 ~ 180_M 182-1 ~ 182-P 186-1 ~ 186-Q 188-1 ~ 188-R 204, 214, 264 202, 212, 262 236 , 600, 630 242 partial interconnection plate metal layer second plate portion first plate portion partial insulation layer transistor transistor crystal transistor 274 base portion 272 wings, 650, 700, 908 second metal layer 950 Connection structure 50 200847381 244, 252 dielectric layer 246- 246_2, 246-N via 250 252 254, 474 260 270 280 first metal layer solder mask, 620 solder ball first plate contact point portion second plate Contact point portion third plate contact point portions 284, 284-1, 284-2 to 284-8 additional contact point portions 320, 400 324, 404 326, 406 320, 324' 326, first plate shape Conductive portion second plate-shaped conductive portion third plate-shaped conductive portion Divided into the first part, the second part, the third part 330-1, 330-2, 330-3~330-8, 410, 410-1~410-8, additional plate-shaped conductive parts 340-1, 340-2~340_16 holes 348 substrate

350 、 354 、 370、376、 374 375 378 ‘ 356、360_1、360_2〜360-8 鍍通孔（PHT) .480金屬層 電介質層 過孔 孑L 402 板狀導電部分 340-1’、340-2,〜340-16’開口 412、422 414、424 418、428 第一外側接觸點部份 第二外側接觸點部份 中間接觸點部份 51 200847381 419 額外的接觸點部份 420 堆積層 430 額外的部分350, 354, 370, 376, 374 375 378 '356, 360_1, 360_2~360-8 plated through hole (PHT) .480 metal layer dielectric layer via 孑L 402 plate conductive portion 340-1', 340-2 , 340-16' opening 412, 422 414, 424 418, 428 first outer contact point portion second outer contact point portion intermediate contact point portion 51 200847381 419 additional contact point portion 420 stacking layer 430 additional section

444、472、501 1C 440 456 450 452 460、462 480-1 ^ 480-2 482-1 ^ 482-2 解耦電容器 絕緣材料 第一導電板 第二導電板 導電臂 額外的金屬層 短路寄生電阻 484、960 電容器 500-1、500-2 散熱器 504 鰭狀物 502 基部 509 焊球柵陣列 510、520 散熱器帶 514 強化條 604、606、608、610、702、704、706、708 閘極區域 614、664、714過孔及/或堆積層 616、660、710強化材料 634 焊盤 652、654、656 區域 810、840 導線架444, 472, 501 1C 440 456 450 452 460, 462 480-1 ^ 480-2 482-1 ^ 482-2 Decoupling Capacitor Insulation Material First Conductive Plate Second Conductive Plate Conducting Arm Additional Metal Layer Short Circuit Parasitic Resistance 484 960 capacitor 500-1, 500-2 heat sink 504 fin 502 base 509 solder ball grid array 510, 520 heat sink strip 514 stiffener strip 604, 606, 608, 610, 702, 704, 706, 708 gate region 614, 664, 714 vias and/or buildup layers 616, 660, 710 reinforcement material 634 pads 652, 654, 656 regions 810, 840 leadframe

812-卜 812-2、812-3、822、822-1〜822-5、844-卜 844-Q、 910-1 〜910-3、912-1 〜912-4、954-1〜954-3 傳輸線 800 、 818 1C 850 成形材料812-Bu 812-2, 812-3, 822, 822-1~822-5, 844-Bu 844-Q, 910-1~910-3, 912-1~912-4, 954-1~954- 3 transmission line 800, 818 1C 850 forming material

900、951 1C 52 200847381 1050、1120、1198、105(Τ、1300、1340 電晶體 1054 1056 1058 1066 1070 1080 1122 1126 1128 1130 1138 1140 源極 沒極 閘極 主體 源極接觸分接頭 主體接觸分接頭 閘極接觸點 源極接觸點 没極接觸點 Ν井區接觸點 Ν型基板層 Ρ型基板 1134、1136 Ρ*區域 1141 N#區域 1200、1200-1〜1200-G 閘極區域 1224、1224-1〜1224-S 源極區域 1220、1220-1〜1220-D 汲極區域 1210 限定區域 1212 相鄰區域 1230、1230_11、1230-12〜1230_55 電晶體群組 1260 Ν井區接觸點 1304、1304-1、1304-2、1304_3、1304-4、1304_5、1304-6、1304-7、 1304-11、1304-12、1304-4Q 源極區域 1306、1306-1、1306-2、1306-3、1306-4、1306-5、1306-U、1306-12、 1306-4Τ 汲極區域 1310 閘極區域 1311、1311-1〜1311-Β源極接觸點 1330、1330-1、1330-2 基板接觸點 53 200847381 1334、1334-1、1334-3 汲極接觸點 1331 虛線區域 1335 對向部份 1337-1 〜1337_S 對半900, 951 1C 52 200847381 1050, 1120, 1198, 105 (Τ, 1300, 1340 transistor 1054 1056 1058 1066 1070 1080 1122 1126 1128 1130 1138 1140 source poleless gate body source contact tap body contact tap gate Extreme contact point source contact point immersion contact point Ν well area contact point Ν type substrate layer Ρ type substrate 1134, 1136 Ρ * area 1141 N# area 1200, 1200-1~1200-G gate area 1224, 1224-1 ~1224-S source region 1220, 1220-1~1220-D drain region 1210 defined region 1212 adjacent region 1230, 1230_11, 1230-12~1230_55 transistor group 1260 Sakai contact point 1304, 1304-1 , 1304-2, 1304_3, 1304-4, 1304_5, 1304-6, 1304-7, 1304-1, 1304-12, 1304-4Q source regions 1306, 1306-1, 1306-2, 1306-3, 1306 -4, 1306-5, 1306-U, 1306-12, 1306-4Τ drain region 1310 gate region 1311, 1311-1~1311-Β source contact point 1330, 1330-1, 1330-2 substrate contact point 53 200847381 1334, 1334-1, 1334-3 bungee contact point 1331 dashed area 1335 opposite part 1337-1 ~ 1337_S half

1344-卜 1344-2〜1344-R、1344-1A、1344-1B、1344-2A、1344-2B 狹長源極區域1344-b 1344-2~1344-R, 1344-1A, 1344-1B, 1344-2A, 1344-2B narrow source area

1346- 1、1346-2〜1346-R、1346-1A、1346_2A、1346-1B、1346-2B 驅動器 1347- H、1347-12、1347-21、1347-22、1347-23〜1347-5卜 1347-52、 1364、1384 基板接觸點 1345-A1、1345-A2、1345-A3、1345-A4 第一區域 1345-B卜 1345-B2、1345-B3、1345-B4 第二區域 1347-1、1347-2、1347-3 電晶體佈局 1348 1349 1352 1350 1360 1366 1500 1501 1502 1503 1504 15051346- 1, 1346-2~1346-R, 1346-1A, 1346_2A, 1346-1B, 1346-2B Driver 1347-H, 1347-122, 1347-21, 1347-22, 1347-23~1347-5 1347-52, 1364, 1384 substrate contact points 1345-A1, 1345-A2, 1345-A3, 1345-A4 first area 1345-B Bu 1345-B2, 1345-B3, 1345-B4 second area 1347-1, 1347-2, 1347-3 transistor layout 1348 1349 1352 1350 1360 1366 1500 1501 1502 1503 1504 1505

1368 汲極區域 1369、1370閘極區域 1372 線狀閘極連接區域 圓形閘極區域 1380 源極區域 1386 接觸點區域 硬碟驅動器(HDD) 硬碟元件(HDA) 印刷電路板(PCB) 磁性介質 讀取/寫入元件 磁頭驅動臂 1506、1534 主轴馬達 1507 音圈馬達 1508、1531 放大器元件 1509 讀取/寫入通道模組 54 200847381 1510 1511 1512 1513 1514 1515 1516 1518 1519 1520 1521 1526 1527 1528 1532 1533 1535 1536 1537 1538 1539 1541 1542 1543 1545 1546 1547 1554 1556 硬碟控制器模組 1522 緩衝器 1523 非揮發性記憶體 1524 處理器 1525 主軸/FM驅動器模組 1529 輸入/輸出介面 1530、1540、1548、1562、1582、1591 電源1368 drain region 1369, 1370 gate region 1372 linear gate connection region circular gate region 1380 source region 1386 contact point region hard disk drive (HDD) hard disk component (HDA) printed circuit board (PCB) magnetic media Read/write component head drive arm 1506, 1534 spindle motor 1507 voice coil motor 1508, 1531 amplifier component 1509 read/write channel module 54 200847381 1510 1511 1512 1513 1514 1515 1516 1518 1519 1520 1521 1526 1527 1528 1532 1533 1535 1536 1537 1538 1539 1541 1542 1543 1545 1546 1547 1554 1556 Hard Disk Controller Module 1522 Buffer 1523 Non-volatile Memory 1524 Processor 1525 Spindle/FM Driver Module 1529 Input/Output Interface 1530, 1540, 1548, 1562 , 1582, 1591 power supply

DVD驅動器 DVD PCB DVD元件 DVD控制模組 類比前端模組 寫入策略模組 DSP模組 雷射驅動器 光學元件 光學儲存介質 饋送馬達 高晝質數位電視 HDTV控制模組 1574、1581、1598 顯示器 1549、 1564、1583、1592 記憶體 1550、 1566、1584、1593 儲存裝置 1552、1567、1568、1585、1594 網路介面 1587、1599外部介面 車輛 車輛控制系統 感測器 輸出信號 55 200847381 1558 1560 1570 1572 1576 1596 1578 1580 1589 1590 1597 行動電話 電話控制模組 麥克風 音頻輸出 使用者輸入裝置 使用者輸入 機頂盒 機頂盒控制模組 行動裝置 行動裝置控制模組 音頻輸出 56DVD drive DVD PCB DVD component DVD control module analog front end module write strategy module DSP module laser driver optical component optical storage medium feed motor high quality digital TV HDTV control module 1574, 1581, 1598 display 1549, 1564 , 1583, 1592 memory 1550, 1566, 1584, 1593 storage devices 1552, 1567, 1568, 1585, 1594 network interface 1587, 1599 external interface vehicle vehicle control system sensor output signal 55 200847381 1558 1560 1570 1572 1576 1596 1578 1580 1589 1590 1597 Mobile phone control module microphone audio output user input device user input set-top box set-top box control module mobile device mobile device control module audio output 56

Claims (1)

200847381 、申請專利範圍： 一種積體電路，包括： N個板狀金屬層，其中N是大於1的整數； 一第一板狀金屬層，其包括分別血所 個接觸點部分，其中μ是大於'i 金屬層〜通信的m j層和所述N個板狀金屬層位於分開的平面' y述第一板狀金 一第一源極； ’ 一第一汲極； 一弟一源極’其中所述至少兩個裳—^» 述第二源極與所述n個板狀金屬層'中至少m没極和所 難，配置在職第 以及 在第 在比所述第二區域更遠的距 2. 如申清專利範圍第2項所述之 —區域中的井區基板接觸點-進—步包括配置在所述第 3. 如申請專利範圍第W所述之 —區域中的R個井區基板接觸點，在所述第 4. ίΐί專利範圍第3項所述之積體電路，其中R是大於3且小於7 其中所述積體電路包括複 IS範圍第1項所述之積體電路， 57 200847381 ㈣5項所述之龍電路，射賴電晶體包括 7. 物，綱紅輸基板接 8.七印範圍第1項所述之積體電路’進-步包括： 一 閘極，配置在所述第二源極和所述第二沒極之間， 第替第三和第四區域，所述第二和 距離。 故弟二£域中被配置在比所述第四區域中更遠的 9· = 斤述Γ體，，其中所述第-區域被配置 三區域。 °°或皿所述第二區域被配置在轉所述的第 域積體電路，其中所述第-和第三區 u.以!:==二斤述之積體電路，其中所述n個板狀金屬 12·如申睛專利範圍第1項所述之積 層位於分開的平面中。 、 體電路，其中所述n個板狀金屬 如申請專利範圍第丨項所 和第二源極以及所述第-難的^個進局一部步互包連括與所述第一 58 200847381 14_如申請專利範圍第丨項 分中至少一個是橢圓形的。Λ |包路，其中所述Μ個接觸點部 15.如申請專利範圍第丨項 分中的第一和第二接觸點A f體^路，其中所述Μ個接觸點部 翼，並且所述Μ個接觸點^乂由、^7_基部和從所述基部延伸的 Μ個接觸點部分中的所述笛二弟三接觸點部分被接收在所述 乐和弟二接觸點部分的所述翼之間。 16· 觸點部分中的第三接觸點部分形狀，並且所述Μ個接 所述第一和第二接觸點部分之間。斤述Μ個接觸點部分中的 I7·如申請專利範圍第1項所述之 1率IC，所述Μ個接觸點部分體電路實施 Τ提供第—電壓電勢，所述Μ個3刀向所述功率 向所述功率1C提供第^ 接觸點部分 第三接觸點部分接收所述功3的亚^出所電攻壓Μ個接觸點部分中的 18 — • 2系包括如申請專利範圍第工 5括-導線架，該導線架包括與所述Μ個接觸進-步 個通信的傳輸線。 接觸^邛刀中的至少兩 19. ^ =專利範圍第18項所述之系統，其 輸線被一成形材料所包封。 <谓聪电路和所述傳 2〇 專利範圍第19項所述之系統，其中所述導線竿和所伴辦 电路只施一四邊扁平無接腳（QJ^)封裝。 、、木孝所述和體 59 200847381 一、第三和第四 的長度相等。 源極區域的長度實質上_述第—沒極區域 24.如申圍第22項所述之積體電路 二弟二和弟四源極區域的寬度比所述第-汲極S的寬ί 25· =^專3圍第24項所述之積體電路，其中所述第一 度的-原極區域的寬度大約為所述第—汲極區域寬 26. ^請專利範圍第22項所述之積體電路，進—步包括. 般為矩形形狀並配置在相鄰於所述第- 第i所、f，、'七源極區域，具有一般為矩形形狀並配置在相鄰 於所述第二汲極區域的另一側。 且你々日州 27· ^申請專利範圍帛26工員所述之積 =區=所述第一、第五、第六和第七源極‘戶以 28· ^申凊專利範圍第27項所述之積體電路，進一步包括第五丄 土板接觸點區域，配置在相鄰於所述第二没極區域的角落。 29·如申請專利範圍第22項所述之積體電路，其中所述積體電路 橫向擴散MOSFET電晶體。 30·如申^專利範圍第22項所述之積體電路，進一步包括在所述 一、第二、第三和第四源極區域的每一個之中的B個源極接觸點， 61 200847381 包〆克匕括Μ請專利細第1項所述之積體電路，進一步 ^言傳輸線’其與所述Μ個接觸點部分的第—接觸點部分 一pi專輸線’其與所述Μ個接觸點部分的第二接觸點部分 第二傳輸線，其與所述Μ個 通信；以及 楼觸點部分的第三接觸點部分 ::其傳與二第;所壓述第;傳输=:，其中所 輸線提供一第二電壓電勢弟电壓電勢，亚且所述第三傳 22· —種積體電路，包括： Ν巧板狀金屬層，其中Ν是大於1的整數； 一屬層’包括與所述Ν個板狀金屬層中的夂個 g =弟—板狀金屬層和所述Ν個板狀金屬層位於分開 二第一j極區域，具有一般為矩形的形狀； 弟Ϊ在第四源極區域，息具有一般為矩形形狀並配 置在相郝於所述弟一及極區域的侧邊； 其中所述第-汲極區域和所述第-、第二、第三和第四源極 區域與所述N個板狀金屬層中的至少兩個通信； '、 一第-問極區域，配置在所述第-、第二、第三和第四源極區 域和所述第一汲極區域之間；以及 第一、第二、第三和第四基板接觸點區域，配置在與所述第一汲 極區域相鄰的角落。 23.如申請專利範圍第22項所述之積體電路，其中所述第一、第 200847381 其中B是大於i的整數。 31. 32. 33. 34. 35. k 36. 良有面積A，且其中所述面 如申請專利範圍第30項所述之積體番故、上、 具有面積D並且職b麵極細’，、’4 —汲極區域 積D大於或等於2*b*A。 如申睛專利範圍第22項所述之#生縣& 層中的至少兩個是共面的 *路’其中所述N個板狀金屬 項所述之積體電路’其中所述N個板狀金屬 =專一項所ί，積第體電路，進-步包括-複數個局 一汲極區域通信 弟―、弟二和細祕區域以及所述第 部二 ，纟键Μ個接觸點 J申第22項所述之積體電路，其中所述第-、第二、 ίϊ r個板狀金屬層中的第—板狀金屬層 金屬層通4 與所述n個板狀金屬射的第二板狀 it二專中=圍一第和2;項:述之積體電路，其中所述m個接觸 個^觸^部分中的第三接觸點部分被 的所述翼之間。 ”，、邛刀中的所述第一和第二接觸點部分 62 37. 200847381 38·如申請專利範圍第22 點部分中的第一和第、斤述之積體電路，其中所述M個换觸 M個接觸點部分中觸點部分-般是“c”形狀，並且財户斤述 點部分中的所述第一 ^二接觸點部分被配置在所述M、個操艄 乐和弟二接觸點部分之間。 •如申明專利範圍第22馆 實施一功率Ic，、斤秕之積體電路，其中所述積體電路 =述功率1C提供第點部分中的第-接觸點部分尚 第二接觸點部分向所述電勢，所述Μ個接觸點部分中的 述Μ個接觸點部分中二士]0一提供-第二電壓電勢，龙且所 的輪出電壓。 、弟二接觸點部分接收所述功率1C 40. 積體電路，進一步 Μ個接觸點部分中的至 線包ί如二f專利範圍第22項所述之 匕Γ 該導線架包括與所述 夕兩個通信的傳輸線。 41. ^申請專利範圍帛40項所述之系統 輸線被成形材料所包封。 ’其中所述積體電路和所述傳 42. 如申請專利範圍第41項所述之系統 電路實施一四邊扁平無接腳（QP]^) ’其中所述導線架和所述積體封叢。 種系統，包括如申請專利範圍第22項所述之積體電路，進一步 乙括： 一第一傳輸線，其與所述Μ個接觸點部分的第一接觸點部分 通信； 一第二傳輸線，其與所述Μ個接觸點部分的第二接觸點部 通信； 63 200847381 一^傳其與舰則目_轉麵第三接觸點部分 -電容’其與所述第二傳輸線和 第二傳輸線提供-第-電壓電勢且;中所述 第二電壓電勢。 所述弟二傳輸線提供一 44· 一種積體電路，包括·· N，板狀金屬層，其中N是大於1的整數； 的m個接觸點部分? :整1 板^^通信 i 7板狀金屬層和所述N個板狀金屬丄二;ΐ 及極區域，具有—水平和垂直中線至少—條對稱的形 -第-’區域’具有圍繞所述第— 一，二錄區域，具有所述對稱形狀；_弟械， 區t具有?繞所述第二汲極區域的第-形狀； 連接區域，連接所述第一和第二閘極區域； 第二閘 一第一源極區域，配置在相鄰於所述第一閘極區域、戶片 極區域和所述連接區域的一侧；以及 -第二源極區域’配置在相鄰於所述第—閘極區域、所述第二 閘極區域和所述連接區域的側邊的一側； 其中所述第一、源極區域、所述第二源極區域、所述第一汲 極區域和所述第二没極區域與所述N個板狀金屬層中的至 少兩個通信。 45.如申請專利範圍第44項所述之積體電路，其中所述對稱形狀隨著 與所述對稱形狀的中心的距離增大而逐漸成錐形。 64 200847381 46·如申請專利範圍第44項所述之積體電路，進一步包括配置 第一和第二源極區域中的第一和第二基板接觸點。 α 47·如申清專利範圍第44項所述之積體電路，其中所述積體電路 橫向擴散的MOSFET電晶體。 48.如申請專利範圍第44項所述之積體電路，豆中所述對稱形 一 圓形。 八 49·如申請專利範圍第44項所述之積體電路，其中所述對稱形狀 橢圓形。 50·如申明專利範圍苐44項所述之積體電路，立中戶斤述對稱形狀是一 多邊形。 〃 51·如申請專利範圍第44項所述之積體電路，其中所述對稱形狀是一 六邊形。 八 52· ^申請專利範圍第私項所述之積體電路，立中所述Μ個板狀金 屬層中的至少兩個是共面的。 53·如申睛專利範圍第44項所述之積體雷路，其中所述Ν個板狀 金屬層位於分開的平面中。 、 ’、 54·如申請專利範圍第44項所述之積體電路，進〆梦包括複數個局部 其與所述第—和第二源極區域以及所述第〆和第二沒極區 55·如申請專利範圍第44項所述之積體電路，其中所述Μ個接觸 65 200847381 點部分中至少-個是橢圓形的。 56.如申請專利範圍第44項所述之積㈣ 點部分中的第—和第二接觸點部^ ’其巾所述M個接觸 延伸的翼，並且所述M個接觸一基部和從所述基部 被接收在所述M個接觸點部分中^中，-第三接觸點部分 份的所述翼之間。 、斤述第一和第二接觸點部 點第4二項^^電路，其中所述μ個接觸 ΙΜ分中的所述第一和第二接觸點部分=置在所述Μ健 =清專利範圍第44項所述 貝知功率Ic，所述 、1路，其中所述積體電路 1C 曰第一接觸點部分向所述功率IC»固接觸點部分中 ι. ^斤述Μ個接觸點部分中的壓電勢，並 IC的輪出電壓。 一接觸2 σ卩分接收所述功率 包括绩。，青專利範圍第44項所述之積體電路，進-牛 述項包所^之系統，其中所述積體電路和所 66 61· 200847381 62. =系統，包括如申請專利範圍第44項所述之積體電路，進一步 ^言；傳輸線，其與所逑M個_點部分的第—接觸點部分通 一第二傳輸線，其與所述M個接 信； W獲觸點邛分的第二接觸點部分通 一第三傳輸線，其與所述M 信；以及 们接觸點部分的第三接觸點部分通 一電容，其與所述第二傳輸線和 :述第二傳輸線提供一第一電工條 J : 傳輸線提供一第二電壓電勢。 亚且所述弟二 63. —種積體電路，包括： N巧板狀金屬層，其中N是大於丨的整數； ，一板狀金屬層，其包括分別與所述N ==部分’其中m是大於1的整數 ^狀五屬層和所述Ν彳_狀金屬層位於分開的平面中； Μ及 Ϊ一和^二汲極區域，其具有一般為矩形的形狀； 第二、第和第三源極區域區域，其具有一般為矩形的形狀，其 :所述第一源極區域被配置在所述第一和第二汲極區域的第 »側之間，並且所述弟一和弟二源極區域被配置在相鄰於所述 _弟一和第二汲極區域的第二侧； 第四和第五源極區域，其中所述第四源極區域被配置在相鄰於所 述第一和第二汲極區域的第三側，且所述第五源極區域被配置 在相鄰於所述第一和第二汲極區域的第四侧； 一閘極區域，配置在所述第一、第二、第三、第四和第五源極區 域和所述第一和第二汲極區域之間；以及 67 200847381 第中和第一及極接觸‘點，各自被配置在所述第-和第二沒極區域 Ά所述第和第二沒極區域和所述第-、第-、第：、第四和 中的至少兩個與所述弟則以^ 第63項所述之積體電路，其中所述第-、 度相等，ϋΐ區Ϊ的長?實質上與所述第—沒極區域的長 於所述第一和第極區域二 65_ tti專63項所述之積體電路，其中所述第一、第 -矛弟二絲區域的寬度比所述第_祕區域的寬度小。 66· 第二=述之積體電路，其中所述第一、 ^^弟二絲區域的寬度賴是所述第—錄區域的寬度 圍ΐ63項所述之積體電路，其中所述第四和 弟五源極區域疋從其側邊被驅動的。 68·如申請專利範圍帛63項職之積體電路， 極接觸點的尺寸大於最小汲極接觸點的尺寸、。； / 69·如申請專利範圍第63項所述之積體雷 甘由祕、f、％搞被 觸點具有規則形狀和不規則形狀之」。@、中所〜及極接 70· =項所述之積體電路，其中所躲極接 觸點為方形、矩形和十子形之一。 68 200847381 71· ^申請專利範圍第63項所述之積體電路，其中所述第一、 弟一和弟二源極區域包括源極接觸點。 72. 申請專利範圍第63項所述之積體電路，其中所述第一和 第二汲極區域和所述第一、第二和第三源極區域被配置在第 一列中’並且包括Ν個額外的列，其中所述ν個額外的列中 至少一列的汲極區域共用所述第四和第五源極區域之一。 73· 專利範圍第63項所述之積體電路，其中所述Ν個板 狀金屬層中至少兩個是共面的。 ，其中所述Ν個板 狀金屬層位於分開的平面中。200847381, Patent application scope: An integrated circuit comprising: N plate-shaped metal layers, wherein N is an integer greater than 1; a first plate-shaped metal layer comprising a portion of the contact point of the blood, wherein μ is greater than 'i metal layer ~ communication mj layer and the N plate metal layers are located in separate planes' y first plate-shaped gold-first source; 'one first bungee; one brother-source' The at least two of the second source and the n plate-shaped metal layers are at least m-difficult and difficult to configure, and are disposed at a position further away from the second region. 2. The well substrate contact point-in step in the region as described in claim 2 of the patent scope includes R wells disposed in the region as described in claim 3. The integrated circuit of the fourth aspect of the present invention, wherein R is greater than 3 and less than 7 wherein the integrated circuit includes the integrated body of the first aspect of the complex IS range Circuit, 57 200847381 (d) The dragon circuit described in 5, the smashing transistor includes 7. The substrate circuit of the seventh embodiment of the seventh embodiment includes: a gate disposed between the second source and the second pole, the third and the third The fourth area, the second and the distance. The second domain is disposed in a farther distance than the fourth region, wherein the first region is configured with three regions. Or the second region of the dish is disposed in the first domain integrated circuit, wherein the first and third regions u. are integrated circuits of ::== two kilograms, wherein the n The slab-shaped metal 12 is laminated in a separate plane as described in claim 1 of the patent application. And a body circuit, wherein the n plate-shaped metals are as described in the scope of the patent application and the second source, and the first-to-difficult one step is mutually packaged with the first 58 200847381 14_ At least one of the items of the patent application scope is elliptical. Λ |包路, wherein the one contact point portion 15. The first and second contact points in the 丨 分 申请 , , , , , , , , a contact point, a base portion, and a portion of the contact point portion of the contact point extending from the base portion are received at a portion of the contact point of the music and the second contact point Between the wings. 16. The third contact point portion of the contact portion is shaped, and the plurality of contacts are between the first and second contact point portions. I1 is described in the contact point portion of the I7. According to the rate IC described in claim 1, the one-touch portion of the body circuit is configured to provide a first-voltage potential, and the three-knife The power is supplied to the power 1C. The third contact point portion of the third contact point portion receives the power tapping of the power 3, and the contact point portion of the contact point portion is 18 - 2 Including a lead frame, the lead frame includes a transmission line in communication with the one of the contacts. At least two of the contact knives 19. The system of claim 18, wherein the transmission line is enclosed by a forming material. The system of claim 19, wherein the lead wire and the associated circuit are only provided in a four-sided flat pinless (QJ^) package. , Mu Mu said the body and body 59 200847381 First, the third and fourth lengths are equal. The length of the source region is substantially the same as described above. The width of the second circuit region of the second circuit and the fourth source region is greater than the width of the first electrode. The integrated circuit according to Item 24, wherein the width of the first-order region is about 26. The width of the first-pole region is 26. The patent scope is 22 The integrated circuit includes a generally rectangular shape and is disposed adjacent to the first-th, i, f, and 'seven source regions, has a generally rectangular shape, and is disposed adjacent to the The other side of the second bungee region. And you 々日州27· ^ application for patent scope 帛 26 workers described in the product = area = the first, fifth, sixth and seventh source 'houses 28 · ^ apply for patent scope, item 27 The integrated circuit further includes a fifth bauxite contact point region disposed at a corner adjacent to the second stepless region. The integrated circuit of claim 22, wherein the integrated circuit laterally diffuses the MOSFET transistor. 30. The integrated circuit of claim 22, further comprising B source contact points in each of said one, second, third and fourth source regions, 61 200847381 〆 〆 匕 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 传输 传输 传输a second contact point portion of the contact point portion of the second transmission line, which communicates with the one of the plurality; and a third contact point portion of the floor contact portion:: the second and the second contact point; the first description; the transmission =: Wherein the transmission line provides a second voltage potential voltage potential, and the third transmission circuit comprises: a singular sheet metal layer, wherein Ν is an integer greater than 1; The genus layer 'comprising a plurality of g-different-plate-like metal layers and the one of the slab-shaped metal layers in the two slab-shaped metal layers are separated from the first first j-pole regions, and have a generally rectangular shape; In the fourth source region, the sisters have a generally rectangular shape and are arranged in the phase of the brothers and the polar regions. a side of the domain; wherein the first-pole region and the first, second, third, and fourth source regions communicate with at least two of the N plate-like metal layers; a polarity region disposed between the first, second, third, and fourth source regions and the first drain region; and first, second, third, and fourth substrate contact regions And disposed at a corner adjacent to the first drain region. 23. The integrated circuit of claim 22, wherein the first, the number 200847381, wherein B is an integer greater than i. 31. 32. 33. 34. 35. k 36. There is a good area A, and the above-mentioned surface is as described in item 30 of the patent application scope, and has an area D and a fine surface b. , '4 — The area of the drain region D is greater than or equal to 2*b*A. At least two of the #生县& layers described in Item 22 of the scope of the patent application are coplanar * roads, wherein the N circuits of the N plate metal items are described in the N Plate metal = special one, the first body circuit, the step-by-step includes - a plurality of bureau-bungee area communication brothers - brothers and secret areas and the second part, the 纟 key Μ a contact point J The integrated circuit according to Item 22, wherein the first, second, and second plate-shaped metal layers of the first plate-shaped metal layer metal layer 4 and the n plate-shaped metal beams The second plate-shaped it two-in-one = the first and the second; the item: the integrated circuit, wherein the third contact point portion of the m contact portions is between the wings. The first and second contact point portions in the trowel 62 37. 200847381 38. The first and second integrated circuit circuits in the 22nd point of the patent application, wherein the M Replacing the contact portions of the M contact point portions is generally a "c" shape, and the first and second contact point portions of the financial member's point portion are disposed in the M, a joy and a brother Between the two contact points. • If the power of the 22nd building of the patent scope is implemented by a power Ic, the integrated circuit of the battery, wherein the integrated circuit 1C provides the first-contact point in the first part. The second contact point portion provides a second voltage potential to the electric potential, the second contact voltage in the one of the contact point portions of the one contact point portion, and the wheel voltage of the dragon. The point portion receives the power 1C 40. The integrated circuit, and further the contact line portion of the contact point portion is as described in item 22 of the patent range of the second f. The lead frame includes two communicating with the eve Transmission line 41. ^The system transmission line described in item 40 of the patent application is formed The material is encapsulated. 'The integrated circuit and the transmission 42. The system circuit according to claim 41 of the patent application implements a four-sided flat no-pin (QP)^) 'the lead frame and The integrated system includes the integrated circuit as described in claim 22, further comprising: a first transmission line communicating with the first contact point portion of the one contact point portion a second transmission line that communicates with the second contact point portion of the one contact point portion; 63 200847381 a pass to the ship's head _ turn surface third contact point portion - capacitor 'its and said second The transmission line and the second transmission line provide a -first voltage potential and the second voltage potential. The second transmission line provides a 44. an integrated circuit comprising: · N, a plate-like metal layer, wherein N is greater than 1 Integer; m contact point portions?: 1 plate ^^ communication i 7 plate metal layer and the N plate metal 丄2; ΐ and pole regions, having - horizontal and vertical center lines at least - strip symmetry Shape-of-the-area has around the first one, two a region having the symmetrical shape; a brother, a region t having a first shape around the second drain region; a connection region connecting the first and second gate regions; and a second gate first a source region disposed on a side adjacent to the first gate region, the cell pole region, and the connection region; and a second source region ' disposed adjacent to the first gate region a side of the second gate region and a side of the connection region; wherein the first, source region, the second source region, the first drain region, and the second The electrodeless region is in communication with at least two of the N sheet metal layers. 45. The integrated circuit of claim 44, wherein the symmetrical shape tapers as the distance from the center of the symmetrical shape increases. The integrated circuit of claim 44, further comprising configuring the first and second substrate contact points in the first and second source regions. The integrated circuit of claim 44, wherein the integrated circuit laterally diffuses the MOSFET transistor. 48. The integrated circuit of claim 44, wherein the symmetrical shape of the bean is a circle. The integrated circuit of claim 44, wherein the symmetrical shape is elliptical. 50. As stated in the patented area 苐 44, the integrated circuit is a polygon. The integrated circuit of claim 44, wherein the symmetrical shape is a hexagon.八 52· ^ In the integrated circuit of the patent application scope, at least two of the one of the slab-shaped metal layers are coplanar. 53. The integrated lightning path of claim 44, wherein the one of the sheet metal layers is in a separate plane. , ', 54. The integrated circuit of claim 44, comprising a plurality of local and the first and second source regions and the second and second non-polar regions 55 The integrated circuit of claim 44, wherein at least one of the points of the contact 65 200847381 is elliptical. 56. The first and second contact point portions of the product (four) point portion of claim 44, wherein the M contact extension wings, and the M contacts one base and the slave The base is received between the wings of the M contact point portions, and the third contact point portion. The first and second contact point portions of the fourth item ^^ circuit, wherein the first and second contact point portions of the μ contact points are placed in the patent The range of the above-mentioned integrated circuit 1C 曰 first contact point portion to the power IC» solid contact point portion ι. The piezoelectric potential in the part, and the IC's turn-off voltage. A contact 2 σ 卩 receives the power including performance. The system of the integrated circuit described in the 44th item of the patent scope, the system of the invention, wherein the integrated circuit and the system include the system, including the 44th item of the patent application. The integrated circuit, further, a transmission line, which is connected to a first contact line of the first contact point of the M-point portion, and a second transmission line, which is connected to the M; The second contact point portion is connected to a third transmission line, and the M-signal; and the third contact point portion of the contact point portion thereof pass through a capacitor, and the second transmission line and the second transmission line provide a first Electrician strip J: The transmission line provides a second voltage potential. And the second circuit 63. The integrated circuit includes: an N-shaped plate-like metal layer, wherein N is an integer greater than 丨; and a plate-shaped metal layer including the N == portion respectively m is an integer of greater than 1 and the Ν彳-like metal layer is located in a separate plane; Μ and Ϊ and ^ 2 汲 regions having a generally rectangular shape; second, a third source region region having a generally rectangular shape, the first source region being disposed between the »» sides of the first and second drain regions, and a second source region is disposed on a second side adjacent to the first and second drain regions; fourth and fifth source regions, wherein the fourth source region is disposed adjacent to a third side of the first and second drain regions, and the fifth source region is disposed adjacent to a fourth side of the first and second drain regions; a gate region, configured Between the first, second, third, fourth, and fifth source regions and the first and second drain regions; and 67 200847381 a middle and first and a pole contact 'points, each of which is disposed in the first and second electrodeless regions, the first and second poleless regions, and the first, the first, the fourth, the fourth And at least two of the sum and the other are the integrated circuit according to the item 63, wherein the first and the degrees are equal, and the length of the meandering region is substantially longer than the length of the first and second regions. The integrated circuit of the first and second pole regions, wherein the width of the first and first spear-shaped two-filament regions is smaller than the width of the first-secret region. 66. The second embodiment of the integrated circuit, wherein the width of the first and second filament regions is the integrated circuit of the width of the first recording region, wherein the fourth circuit The five source regions of the brothers are driven from their sides. 68. If the application system has a patent range of 63 items, the size of the pole contact point is larger than the size of the minimum pole contact point. / 69· As described in Section 63 of the patent application, the stalks of the stalks are made of a regular shape and an irregular shape. @, 中中~和极接70· = The integrated circuit described in the item, wherein the escaping contact is one of a square, a rectangle and a ten sub-shape. 68. The method of claim 63, wherein the first, second, and second source regions comprise source contact points. 72. The integrated circuit of claim 63, wherein the first and second drain regions and the first, second, and third source regions are disposed in a first column 'and include An additional column, wherein the drain region of at least one of the ν additional columns shares one of the fourth and fifth source regions. 73. The integrated circuit of claim 63, wherein at least two of the plurality of plate-like metal layers are coplanar. Where the one of the sheet metal layers is in a separate plane. 述第一和第二汲極區域通信。 •如申請專利範圍第63項所述之積體電路 •檟體電路，進一步包括複數個局部 第三、第四和第五源極區域以及所 76·如申請專利範圍第63The first and second bungee regions communicate. • The integrated circuit as described in claim 63, the body circuit, further comprising a plurality of partial third, fourth and fifth source regions and 76. 項所述之積體電路 第二接觸Et加a ^ 接觸點部分一 78·如申請專利範圍第63 點部分中的第一和第 :電路，其中所述Μ個接觸 一般是“C”形狀，並且其中 69 200847381 接觸置在所… 79' ' -Γμ™：- 並且所述μ個接二率一1C提供-第二綱 IC的輸出電壓。 刀的弟—接觸點部分接收所述功率 包括—導線亥申導戶^^述之積體電路，進一步 少兩個通信的傳輸線。 >、义M個接觸點部分中的至 述之系統’其中所述積體電路和所 82. 如申請專利範圍第81 積體電路實施一四邊扁平無二裝所述導線架和所述 83. 包Ϊ糸統’包括如申請專利範圍第63項所述積體電路，進〆少 一傳輸線，其與所述M個接觸點部分的第-接觸點部分通 一=傳輸線，其與所述M個接觸點部分的第二接觸點部分通 一^傳輸線，其與所述M個接觸點部分的第三接觸點部分通 以及 200847381 一電容，其與所述第二傳輸線和所述第三傳輸線通信，其中 所述第二傳輸線提供一第一電壓電勢，並且所述第三傳傳輸線 提供一第二電壓電勢。The second contact Et of the integrated circuit described in the item is a plus a ^ contact point portion 78. The first and the first circuits in the 63rd portion of the patent application, wherein the one contact is generally a "C" shape. And wherein 69 200847381 is placed in contact with... 79' ' -ΓμTM:- and the μ is connected to a 1C to provide the output voltage of the second IC. The younger brother of the knife-contact point receives the power, including the integrated circuit of the conductor, and further reduces the transmission line of the two communication. >, the system of the above-mentioned M contact points, in which the integrated circuit and the 82. The method of the 81st integrated circuit of the patent application implements a four-sided flat wire package and the said lead frame 83. The package system includes the integrated circuit as described in claim 63, and the transmission line is reduced by a transmission line, and the first contact point portion of the M contact point portion is connected to a transmission line. The second contact point portion of the M contact point portion passes through a transmission line that is partially connected to the third contact point portion of the M contact point portion and a capacitor of 200847381, which is associated with the second transmission line and the third Transmission line communication, wherein the second transmission line provides a first voltage potential and the third transmission line provides a second voltage potential.
TW097109386A 2007-03-15 2008-03-17 Integrated circuits and interconnect structure for integrated circuits TWI479634B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US89502207P 2007-03-15 2007-03-15

Publications (2)

Publication Number Publication Date
TW200847381A true TW200847381A (en) 2008-12-01
TWI479634B TWI479634B (en) 2015-04-01

Family

ID=39493459

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097109386A TWI479634B (en) 2007-03-15 2008-03-17 Integrated circuits and interconnect structure for integrated circuits

Country Status (3)

Country Link
CN (1) CN101652858A (en)
TW (1) TWI479634B (en)
WO (1) WO2008115468A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8884420B1 (en) * 2013-07-12 2014-11-11 Infineon Technologies Austria Ag Multichip device
CN109952642B (en) * 2016-12-07 2024-03-26 英特尔公司 Integrated circuit device with saw tooth shaped metal trace layout

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07283377A (en) * 1994-01-03 1995-10-27 Texas Instr Inc <Ti> Small-sized gate array and manufacture thereof
JP2611687B2 (en) * 1995-06-26 1997-05-21 セイコーエプソン株式会社 Semiconductor device
US6737301B2 (en) * 2000-07-13 2004-05-18 Isothermal Systems Research, Inc. Power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, power current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor
US6724044B2 (en) * 2002-05-10 2004-04-20 General Semiconductor, Inc. MOSFET device having geometry that permits frequent body contact
US6744288B1 (en) * 2002-10-15 2004-06-01 National Semiconductor Corporation Driver with bulk switching MOS power transistor
US7851872B2 (en) * 2003-10-22 2010-12-14 Marvell World Trade Ltd. Efficient transistor structure
US7265448B2 (en) * 2004-01-26 2007-09-04 Marvell World Trade Ltd. Interconnect structure for power transistors
JP4565879B2 (en) * 2004-04-19 2010-10-20 ルネサスエレクトロニクス株式会社 Semiconductor device

Also Published As

Publication number Publication date
WO2008115468A4 (en) 2009-12-10
WO2008115468A2 (en) 2008-09-25
WO2008115468A3 (en) 2009-09-24
CN101652858A (en) 2010-02-17
TWI479634B (en) 2015-04-01

Similar Documents

Publication Publication Date Title
US11532584B2 (en) Package substrate with high-density interconnect layer having pillar and via connections for fan out scaling
TWI431759B (en) Stackable power mosfet, power mosfet stack, and process of manufacture thereof
US7875529B2 (en) Semiconductor devices
US6376904B1 (en) Redistributed bond pads in stacked integrated circuit die package
CN103855216B (en) Semiconductor device including alternating source and drain regions, and respective source and drain metallic strips
TW577152B (en) Semiconductor integrated circuit device
TW461108B (en) Semiconductor device
TWI548061B (en) Semiconductor memory device
US8026550B2 (en) Integrated circuits and interconnect structure for integrated circuits
CN110491872B (en) Semiconductor die assemblies, packages, and systems and methods of operation
CN107851615A (en) Independent 3D is stacked
TW200841445A (en) Low profile flip chip power module and method of making
WO2005101476A1 (en) Semiconductor element and semiconductor element manufacturing method
TW201236088A (en) Semiconductor package having through substrate via (TSV) interposer and method of manufacturing the semiconductor package
JP2015507843A (en) 3D integrated circuit package with window interposer
JP2009527109A (en) Multi-chip module for battery power control
US9721898B2 (en) Methods of forming under device interconnect structures
TW201011884A (en) Use of discrete conductive layer in semiconductor device to re-route bonding wires for semiconductor device package
TW200847381A (en) Integrated circuits and interconnect structure for integrated circuits
TWI264789B (en) Semiconductor integrated circuit and its manufacturing method
US6788552B1 (en) Method and apparatus for reducing substrate bias voltage drop
CN107431022A (en) Microelectronic substrate with the embedded trace layer with overall attachment structure
US8847404B2 (en) Three-dimensional semiconductor device comprising an inter-die connection on the basis of functional molecules
JP2004140133A (en) Semiconductor integrated circuit and its manufacturing method
JPH04120769A (en) Delay cell for master slice system ic device

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees