WO2008115468A3 - Integrated circuits and interconnect structure for integrated circuits - Google Patents

Integrated circuits and interconnect structure for integrated circuits Download PDF

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Publication number
WO2008115468A3
WO2008115468A3 PCT/US2008/003491 US2008003491W WO2008115468A3 WO 2008115468 A3 WO2008115468 A3 WO 2008115468A3 US 2008003491 W US2008003491 W US 2008003491W WO 2008115468 A3 WO2008115468 A3 WO 2008115468A3
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WO
WIPO (PCT)
Prior art keywords
plane
integrated circuits
drain
source
metal layers
Prior art date
Application number
PCT/US2008/003491
Other languages
French (fr)
Other versions
WO2008115468A4 (en
WO2008115468A2 (en
Inventor
Sehat Sutardja
Original Assignee
Marvell World Trade Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Marvell World Trade Ltd. filed Critical Marvell World Trade Ltd.
Publication of WO2008115468A2 publication Critical patent/WO2008115468A2/en
Publication of WO2008115468A3 publication Critical patent/WO2008115468A3/en
Publication of WO2008115468A4 publication Critical patent/WO2008115468A4/en

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    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Geometry (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

An integrated circuit comprises N plane-like metal layers, where N is an integer greater than one. A first plane-like metal layer includes M contact portions that communicate with the N plane-like metal layers, respectively, where M is an integer greater than one. The first plane-like metal layer and the N plane-like metal layers are located in separate planes. At least two of a first source, a first drain and a second source communicate with at least two of the N plane-like metal layers. A first gate is arranged between the first source and the first drain. A second gate is arranged between the first drain and the second source. The first and second gates define alternating first and second regions in the first drain, and wherein the first and second gates are arranged farther apart in the first regions than in the second regions.
PCT/US2008/003491 2007-03-15 2008-03-17 Integrated circuits and interconnect structure for integrated circuits WO2008115468A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US89502207P 2007-03-15 2007-03-15
US60/895,022 2007-03-15

Publications (3)

Publication Number Publication Date
WO2008115468A2 WO2008115468A2 (en) 2008-09-25
WO2008115468A3 true WO2008115468A3 (en) 2009-09-24
WO2008115468A4 WO2008115468A4 (en) 2009-12-10

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PCT/US2008/003491 WO2008115468A2 (en) 2007-03-15 2008-03-17 Integrated circuits and interconnect structure for integrated circuits

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CN (1) CN101652858A (en)
TW (1) TWI479634B (en)
WO (1) WO2008115468A2 (en)

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Publication number Priority date Publication date Assignee Title
US8884420B1 (en) * 2013-07-12 2014-11-11 Infineon Technologies Austria Ag Multichip device
WO2018106233A1 (en) * 2016-12-07 2018-06-14 Intel Corporation Integrated circuit device with crenellated metal trace layout

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