TW200845230A - Forming a semiconductor device having epitaxially grown source and drain regions - Google Patents

Forming a semiconductor device having epitaxially grown source and drain regions Download PDF

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TW200845230A
TW200845230A TW097105061A TW97105061A TW200845230A TW 200845230 A TW200845230 A TW 200845230A TW 097105061 A TW097105061 A TW 097105061A TW 97105061 A TW97105061 A TW 97105061A TW 200845230 A TW200845230 A TW 200845230A
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insulating layer
layer
region
forming
gate
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TW097105061A
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TWI434355B (zh
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Laegu Kang
Vishal P Trivedi
Da Zhang
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Freescale Semiconductor Inc
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    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
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    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
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Description

200845230 九、發明說明： 【發明所屬之技術領域】 且：：：言二本揭示内容係關於形成半導體裝置之製程， 丰遙舻壯$ 有猫日日生長源極和汲極區域之 牛導體裝置之製程。 本申請案已於2007年2月28 a南盖m植， 安啼& , 干月28日向吳國提出，其專利申請 案號為 1 1/680,2 1 9。 【先前技術】 用於形成具有蟲晶生長源極和汲極區域之半導體裝置之 傳統方法涉及若干氫氟酸清洗步驟，例如"HF清;先:。例 如，以具有蟲晶源極/沒極區域的p型通道裝置為例，在源 極，汲極凹槽形成後即開始實施册清洗過程。然而，此清 洗步驟導致除掉一些用作隔離區一部分的場氧化物及用於 遮罩η型通道裝置的氧化物。此外，隨後使用hf清洗過程 移除用於遮罩n型通道裝置之氧化物遮罩將進—步導致移 除掉作為隔離區一部分的場氧化物。移除場氧化物有違清 洗初衷，#能導致幾個有害結果。例如，當雙㈣終止層 开:成後在半導體裝置之通道區域内生成壓應力或拉應力 時，場氧化物的損失可引起來自雙姓刻終止層的不期望應 力對齊。況且，隔離區場氧化物的損失亦可引起隔離區應 力下降。 因此，需要用來形成具有磊晶生長源極和汲極區域的半 導體裝置之製程。 【發明内容】 128704.doc 200845230 在一恶樣中，提供一種在具有半導體層（帶有隔離區域） 的半導體基板上製作半導體裝置結構之方法。該方法包括 在3半導體層的第一區域上形成第一閘極結構及在該半導 體層第一區域上形成第二閘極結構。該方法進一步包括沿 第-閘極及第二閘極側壁形成側壁間隔層。該方法進一步 f括在第-區域與第二區域上形成第—絕緣層，其中第一 巴緣層可在半‘體層蝕刻期間用作遮罩，且可相對於隔離 區域與側壁間隔層被有選擇性地移除。該方法進一步包括 移除掉第-區域上的第一絕緣層以保留第二區域上第一絕 緣層的剩餘邛分。该方法進一步包括在毗鄰第一閘極的第 -區域内使半導體層凹陷以形成凹槽。該方法進一步包括 在该=凹槽内蠢晶生長半導體材料。該方法進一步包括移 除掉第一絕緣層的剩餘部分。 、在另^樣中，提供一種形成半導體裝置的方法。該方 法包括，供一具有半導體層的半導體基板。該方法進一步 包括在第一區域内形成第一閘極及在第二區域内形成第二 閘極，其中_ 七货 、 3有弟一材料之隔離區將第一區域與第二區 域分離開。与·古、、土、仓 , °亥方法進一步包括用第二材料形成側壁間隔 ::亥第二材料不同於沿第-閉極與第二閉極側壁的第一 一絕緣纟弟-區域及第二區域上形成第 、、、曰，、可相對於第一材料與第二材料有選擇地 〇 方去進一步包括在第一絕緣層上形成篦 緣芦m # 子於弟一絕緣層有選擇地蝕刻第二絕 緣層且可相對於第二絕緣層有選擇性㈣刻半導體層。 128704.doc 200845230 該方法進一步包括圖案化第二絕緣層以保留第二區域上 第二絕緣層的剩餘部分。該方法進一步包括圖案化第一= 緣層以保留第二區域上之第—絕緣層的剩餘部分。該方: 進-步包括在晚鄰第一閑極之第一區域内使半導體：凹陷 以形成凹槽。該方法進一步包括在該等凹槽内磊晶生+ 一 半導體材料。該方法進-步包括移除掉第二絕緣層的剩餘 部分σ該=法進—步包括移除掉第—絕緣層的剩餘部分。'
U 在再一態樣中，提供一種在具有矽層（其帶有含氧化矽 隔離區域）的半導體基板上製作半導體裝置結構之方法。 該方=包括在該㈣卜區域上形成[閘極結構及在該 矽層第二區域上形成第二閘極結構，丨中第一區域用於形 成不同於第_區域内形成之電晶體類型之電晶體類型。該 方法進-步包括沿第-閘極及第二閘極之側壁形成氮化物 側壁：隔層。該方法進一步包括在第一區域及第二區域上 心成第、、、巴緣層，其中可相對於第一絕緣層有選擇地餘刻 石夕，且可相對於氧化石夕及氮化物有選擇地姓刻第一絕緣 /方法進步包括從第一區域上移除掉第一絕緣層以 ’、弟一區域上第一絕緣層之剩餘部分。該方法進一步包 岫第閘極之第一區域内使半導體層凹陷以形成凹 :^方法進一步包括在該等凹槽中磊晶生長一半導體材 料，該材料包含由矽碳與矽鍺組成之群中之一者。該方法 進步包括移除掉第一絕緣層之剩餘部分。 【實施方式】 圖1展示一半導體裝置1〇在一處理步驟期間之視圖。半 128704.doc 200845230 導體裝置10可包含在一基板16上之一埋置氧化物層 (BOX) 14上使用半導體材料12形成之一裝置。本文戶斤述之 半導體材料12可以係任意半導體材料或材料組合，例如石申 化鎵、矽鍺、矽及類似材料、以及上述材料之組合。儘管 圖1展示的是SOI實施方案，但亦可在塊體基板上形成半導 體裝置10。半導體裝置1〇可包括一 p型通道區域24及一 η型 通道區域26，此兩區域由絕緣區域22分離開。可用場氧化 物形成隔離區域22。亦可形成額外隔離區域18及2〇以隔離 開毗鄰裝置。可用場氧化物形成隔離區域18及2〇。可在ρ 型通道區域24内形成一ρ型通道裝置，且可在η型通道區域 26内形成-η型通道裝置。ρ型通道裝置可包括在閘極介電 層27上所形成之閘極電極2卜可在閘極電極28附近形成一 間隔層30。舉例言之，間隔層3〇可係氮化物間隔層。可在 閘極電極28上形成-罩層32。罩層32亦可係氮化物罩層。 可在閘極電極28與間隔層3〇中間形成一概層4〇。概㈣可 ί. 係氧化物襯層。亦可形成源極/汲極延伸區域44, 46以作 為Ρ型通道裝置之-部分。同樣地，η型通道裝置可包括間 極介電層33上之-閘極電_。可用多⑭或金屬或多曰 :與金屬的組合形成閑極電極也可用合適材料： $形成閘極電極2 8與3 4。玎户叫k兩 層36。兴計 了在閘極電極34附近形成—間隔 :+ 間_ 36可錢化物間隔層。可在閘極 電極34上形成罩厣^ a 长間極 曰。罩層38亦可係氮化物罩層。可在n 隔層36與閘極電極34中 在間 物襯層。藉由植入人、/ 觀層42。概層42可係氧化 σ適之摻雜物可形成源極/汲極延伸與 128704.doc 10· 200845230 深源極/汲極48、50作為n型通道裝置之一部分。可在此處 理之較晚階段形成沬源極/汲極，例如，在圖11所示階段 中移除掉磊晶層硬遮罩52之後形成深源極/汲極。儘管圖！ 繪不無襯層覆蓋在源極/汲極區域上及覆蓋在閘極結構之 頂部上，但可在此等區域及結構上存在一襯層。 如圖2所示，可在ρ型通道及η型通道裝置上形成一磊晶 層更C罩5 2可用對HF清洗具有高耐受性的材料形成蟲晶 層硬遮罩52。換言之，蟲晶層硬料52可用在册清洗時具 有低敍刻速率之材料形成。例如，可用高〖材料形成蟲晶 層硬遮罩52。在-實施例中，形成蟲晶層硬遮罩52的材料 之介，常數可大於形成間隔層3〇與36的材料之介電常數。 ，一實施例中’形成蟲晶層硬遮罩52的材料之介電常數可 高於氧化物的較高介電常數。在非限制性實施例中，可用 金屬氧化物（例如，Hf〇2或Zr〇2、或職〇2)形成蟲晶層硬 遮罩5 2。亦可用其他對H F清洗具有高耐受性的材料（例 2 ’ TiN與HfN)形成蟲晶層硬遮罩52。可用化學氣體沈積 製程、原子層沈積製程或物理氣體沈積製程形成蟲晶層硬 遮罩〜蟲晶層硬遮罩52之厚度範圍可㈣埃至細埃之 來#圖3所不’可在磊晶層硬遮罩52上形成—硬 、4 °舉例言之，詩形成硬遮罩54之材料可係、能使硬 遮罩抑對^晶層硬遮㈣被料㈣狀㈣^ ==(例如’未經摻雜的氧切）形成硬遮罩54。可用電 7K 9的化學氣體沈積製程形成硬遮罩54。硬遮罩Μ之厚 128704. doc 200845230 度範圍可在50埃至200埃之間。 接下來，如圖4所示，可在η型通道裝置上形成圖案化光 阻層56。舉例言之，作為該步驟之一部分，可在硬遮罩^ 上形成光阻層，然後可圖案化該層以得到圖案化光阻声 56。 θ 接下來，如圖5所示，可從ρ型通道裝置上蝕刻掉硬遮罩 54。濕蝕刻或乾蝕刻均可用作該步驟之一部分。 接下來’可用電漿灰化製程與pkanha清洗過程移除掉圖 案化光阻層5 6，如圖6所示。 接下來，如圖7所示，可移除掉覆蓋於P型通道妒置上之 蟲晶層硬遮罩52。舉例言之，可在攝氏650度下用氯化氯 (HC1)軋體裱境清洗過程移除掉覆蓋於ρ型通道裝置上之石
晶層硬遮罩。作為該清洗步驟之―部分，可實施快速Z 至30秒鐘。亦可用其他適合之姓刻技術移除掉 1瓜於p型通道裝置上之磊晶層硬遮罩52。 Ο 凹=來6。可簡蚪型通道裝置之—部分的源錄極 凹㈣，，如圖8所示。舉例言之，可使用一乾 ㈣成源極/沒極凹槽58, 6〇。或者，亦可組合使用渴钮 刻製程與乾蝕刻製程。作為該步驟之一 ，、、‘ 凹槽之姓刻深度可在3〇〇埃至埃之間。源極/及極 接下來，如圖9所示，可實施磊晶層清 步驟之—部分，可移除掉源極/汲極凹槽/6彳為該 氧化物。可用册清洗過程實施蟲晶層清i。今石〇=自主然 步驟亦可導致全部或部分地移除掉覆蓋於η型：二= 128704.doc -12 - 200845230
ϋ 一區域内之硬遮罩54。此外，該磊晶層清洗步驟亦可能移 除掉隔離區域1 8及22的頂部部分，如參考編號62與64所 示。因為隔離區域22之一部分覆蓋有磊晶層硬遮罩52，所 以不會移除掉此被覆蓋部分的頂部部分。儘管圖9未示出 區域24内ρ型通道裝置左方有一毗鄰η型通道裝置，但該ρ 型通道裝置左側將會有另外一個η型通道裝置。這樣一 來’僅有隔離區域18之-部分經受遙晶層冑洗步驟清洗。 舉例言之，可從隔離區域18之經暴露部分與隔離區域以之 經暴露部分移除掉高度在約5〇埃至1〇〇埃之間的頂部部 分0 接下來’如圖_示，可在凹槽58、6〇内蟲晶生長源極/ 汲極66、68。舉例言之’可在半導體材料層12上生長原位 掺雜蝴㈣鍺源極/沒極。例如，删之摻雜濃度可在 le20/cm3 至 le21/cm3之間。例如， 1】如鍺的原子含量範圍可為 20-40% ° 接下來’如圖11所示，可移除覆蓋在η型通道裝置上之 蟲晶層硬料52的剩餘部分。舉例言之，可在攝氏㈣度 ==)氣體環境清洗過程移除掉覆蓋於η輸 之1層硬料52之剩餘㈣。作為該清洗步驟之 一 ^ ’可實施快速熱退火過㈣践秒鐘。亦可用其他 適合之蝕刻技術移除掉覆蓋於^型通道裝置 、 ___分。因為此清洗步驟部分並=層: I所以隔離區域中的氧化物不會被敍 ； 形成的蝕刻終止層有更佳 』保姐稍後 <的應力對齊。使場氧化物的損失 128704.doc 200845230 降到取小亦能夠減小對於引發自隔離區域之應力的任何不 利影響。同樣地，因為此步驟部分中未使用氯氣酸，所以 間隔層30、36沒有被消耗掉的部分。 接下來，如圖12所示，可移除掉罩層32及38。在移除掉 . 罩層32及38岫，可先移除掉存在於閘極電極28和34頂部的 任何襯層。接下來，可形成石夕化物區域7G、72、74、76、 78及80。可用鎳、職合金或其他適合之材料製成石夕化 區域 70、72、74、76、78及 80。 接γ來，可在P型通道裝置上形成蝕刻終止層82，如圖 斤示可用此夠將壓應力施加至p型通道裝置之通道 内之材料形成钮刻終止層82。可在n型通道裝置上形成敍 刻終止層84。可用一能將拉應力施加至η型通道裝置之、雨 道内之材料形成姓刻終止層84。可用氮化物形成姓刻終^ 層82和84 〇 、、儘管已針對特定導電型式或電位極性對本發明加以描 〇 ㉛’但㈣此項技術者應瞭解可反置該等導電型式及電位 極性。 此外在說明書及申凊專利範圍中，詞語，，前”、，，後，，、 頂部”、π底部”、π在上面"，，士 在上面 在下面”及類似術語（若有）係 用於闡述之目的而並非用於闡述固定不變的相對位置。應 瞭解’如此使用之詞語在合適情形下可互換，以使本" 所闡述之本發明實施例能夠（例如）以不同於本文所閣釋或 另外闡述之彼等定向之定向運作。 儘管已參照具體實施例對本發明加以描述，但可對其實 128704.doc 200845230 ί 施各種修改及改動，此並不背離下文申請專利範圍中所給 出的本發明範圍。例如，儘管所闡釋之實施例與具有凹陷 源極/汲極區域之Ρ型通道裝置有關，但也可用相似之製程 形成具有凹陷源極/汲極區域之η型通道裝置。對於具有凹 陷源極/汲極區域之η型通道裝置的情況，可在源極/汲極凹 槽内磊晶生長經原位η型摻雜的碳化矽（SiCp因此，應將 本說明書及附圖視作闡釋性而非具有限定性意義，而且所 有此等修改皆意欲包括於本發明範疇内。本文針對具體實 施例所描述之任何優點、益處或問題之解決方案皆非意欲 被理解為任何或所有申請專利範圍之關鍵、必需或基本特 徵或要件。 此外，將本文所用詞語”如，，定義為一個或一個以 上另外，在申請專利範圍中使用說明性片語”至少一個，， 或=、或多個’’不應理解為意指在藉由不定冠詞”一”（a或an) “說月另明求項要件時係將任何包含此被說明請求項要
:之特定請求項限制為僅包含_個此種要件之發明，即使 "明求項包含"兄明性片語，，一或多個，，或，，至少一個，，及 諸如”一”㈣叫等不定冠詞時亦是如此。此亦適用於定冠 5司的使用。 除非另有說明，否則，所用 係為了任意區分該等詞語所描 忒等祠語並非意欲表明該等多 他優先順序。 【圖式簡單說明】 諸如’’第一 ”及”第二”等詞語 述之多個元件。因此，使用 個元件之時間先後順序或其 128704.doc 200845230 本文以實例方式闡釋本發明，但不受附圖之限制，在附 圖中’相同的參考符號表示相同的元件。β中之元件係出 於簡單明晰之目的而緣示，且未必按照比例$會製。 圖1係一半導體裝置在處理階段之視圖； 圖2係-半導體震置在—處理步驟期間之視圖； 圖3係-半導體裝置在一處理步驟期間之視圖； 圖4係-半導體裝置在—處理步驟期間之視圖； 圖5係—半導體裝置在—處理步驟期間之視圖 圖6係-半導體裝置在—處理步驟期間之視圖 導體裝置在一處理步驟期間之視圖 =-半導體裝置在一處理步驟期間之視圖， 圖9係一半導體裝置在一處理步 . 圖10係-半導體裝置在一處理^ 視圖； m 1 Ί v驟期間之視圖； ⑽-半導體裝置在_處理步_間之 圖12係—半導體裝置在-處 ，
U 圖13係—半導體裝置在—處理步=間之視圖；及 【主要元件魏制】 』間之視圖。 10 半導體裝置 12 半導體材料 14 埋置氧化物層 16 半導體基板 18 隔離區域 20 隔離區域 22 隔離區域 128704.doc ~ 16 - 200845230
Cj 24 P型通道區域 26 N型通道區域 27 閘極介電層 28 閘極電極 30 間隔層 33 閘極介電層 34 閘極電極 36 間隔層 40 襯層 42 襯層 44 源極/汲極延伸區域 46 源極/汲極延伸區域 48 深源極/汲極 50 深源極/汲極 66 源極/汲極 68 源極/汲極 70 石夕化物區域 72 矽化物區域 74 矽化物區域 76 矽化物區域 78 矽化物區域 80 矽化物區域 82 蝕刻終止層 84 蝕刻終止層 128704.doc •17- 200845230 32 38 52 54 56 58 60 62 64 罩層 罩層 磊晶層硬遮罩 硬遮罩 圖案化光阻層 源極/汲極凹槽 源極/汲極凹槽 隔離區域頂部部分 隔離區域頂部部分
128704.doc -18-

Claims (1)

  1. 200845230 十、申請專利範圍： 1· 一種在一半導體基板上製作一半導體裝置結構之方法， 该半導體基板具有一含隔離區域的半導體層，該方法包 含： . 在該半導體層的一第一區域上形成一第一閘極結構及 • 在該半導體層的-第二區域上形成-第二閘極結構； 〜名第一閘極及該第二閘極之側壁形成側壁間隔層； ( 在 苐區域與δ亥苐二區域上形成一第一絕緣層，其 中。亥第一絕緣層可在該半導體層蝕刻期間用作一遮罩， 且可相對於该等隔離區域與該等側壁間隔層被有選擇地 移除； 、從該第一區域上移除掉該第一絕緣層以保留該第二區 域上該第一絕緣層之剩餘部分； 在毗鄰該第一閘極的該第一區域内使該半導體層凹陷 以形成凹槽； 〇 在忒等凹槽内磊晶生長一半導體材料；及 移除掉該第一絕緣層之該剩餘部分。 2·如請求項丨之方法，其進一步包含·· 在該第一絕緣層上形成一第二絕緣層； 圖案化該第二絕緣層以保留該第二區域上該第二絕緣 層之剩餘部分；及 在移除該第一絕緣層之步驟中，使用該第二絕緣層之 該剩餘部分作為一硬遮罩。 月长項2之方法，其中形成該第一絕緣層之該步驟的 128704.doc 200845230 2-步特徵為’該第—絕緣層包 層材料的介電常數之材料。 $吊數大於間隔 4. 如請求項3之方法，i击 的 進一步特徵為彳/成該第一絕緣層之該步 、饮為，该弟_絕緣層 5. 如請求項2之太 屬礼化物。 上貝2之方法，其進_步包含： 在該第二絕緣層上形成-光阻層； 圖木化遠光阻層以保留該第二區域上 餘部分；及 妁該先阻層之剩 在圖案化該第二絕緣層 緣β > &止 ^驟5亥後並在移除該第一絕 緣層之❹驟前移除掉該光阻層。 6 ·如請求項2之方法，其中·· = 亥第二絕緣層之該步驟之進一步特徵為，該第二 系巴緣層包含氧化矽；且 形成該第一絕緣層之續牛 步驟之進—步特徵為，該第— 、、、巴緣層包含鈴及氧或铪、錯及氧。 7·如請求項1之方法，置進一半—入士 一— 進步包含在該第一閘極上形成 二弟—應力層且在該第二間極上形成-第二應力層，且 5亥弟—應力層的應力類型與該第-應力層之應力類型不 同。 8. 如請求項1之方法，其中兮石曰4 e卜 、 /、r β挪日日生長步驟之進一步特徵 9. 為該材料包含由矽鍺與矽碳組成之群中之一者。 如請求1之方法，其中嗜石S 4 e h 丄 ^ r ^猫日日生長步驟之進一步特徵為 該材料包含經原位摻雜為p型之矽鍺。 H) ·如請求項1之方法，並φ μ 中移除该弟一絕緣層之該步驟係 128704.doc 200845230 在高於攝氏500度的溫度下實施。 11，如請求項1之方法，其中用氣化氫氣體環境清洗過程實 施移除該第一絕緣層之該步驟。 1 2·如請求項丨丨之方法，其進一步包含在移除該第一絕緣層 •之該步驟後實施快速熱退火。 . 13· 一種形成一半導體裝置之方法，其包含·· 提供一具有一半導體層之半導體基板； (、 在一第一區域内形成第一閘極且在一第二區域内形成 第二閘極，其中一包含有一第一材料之隔離區域將該第 一區域與該第二區域分離開； 沿該第一閘極及該第二閘極之側壁使用不同於該第_ 材料的一第二材料形成側壁間隔層； 在该第一區域及該第二區域上形成第一絕緣層，其中 可相對於該第一材料與該第二材料有選擇地蝕刻該第一 絕緣層； I) 在該第一絕緣層上形成一第二絕緣層，其中可相對於 該第一絕緣層有選擇地蝕刻該第二絕緣層，且可相對於 該第二絕緣層有選擇地蝕刻該半導體層； _ 圖案化該第二絕緣層以保留該第二區域上的該第二絕 • 緣層之剩餘部分； 巴 圖案化該第一絕緣層以保留該第二區域上的該第一浐 緣層之剩餘部分； 巴 在毗鄰該第一閘極之該第一區域内使該半導體層凹陷 128704.doc 200845230 在該等凹槽内蟲晶生長-半導體材料； 移除掉該第二絕緣層之該剩餘部分；及 =除掉該第-絕緣層之該剩餘部分。 絕 應 鏠：求項13之方法’其進一步包括完成移除掉該第 ?之該剩餘部分之步驟後，在該第-區域上形成 力層。
    Lj :长項14之方法’其中形成該第一閘極及該第二閘極 之該步驟之進—步特徵為該第-區域用於-P通道電晶 體且該第二區域用於-N通道電晶體。 16·如請求項13之方法，其中： $成遠第-絕緣層《該步驟之進一步特徵為該第一絕 緣層包含一金屬氧化物；且 形成4第二絕緣層之該步驟之進一步特徵為該第二絕 緣層包含氧化矽，且該氧化矽之蝕刻速度比該隔離區域 内材料的蝕刻速度快。 1 7·如明求項1 6之方法，其中圖案化該第二絕緣層之該步驟 包含使用圖案化光阻層作為一遮罩。 1 8·如明求項1 7之方法，其進一步包含在圖案化該第一絕緣 層之该步驟前移除掉該圖案化光阻層。 19.如吻求項18之方法，其中圖案化該第一絕緣層之該步驟 包έ使用高於攝氏5 〇〇度之溫度。 20·種在帶有一石夕層之一半導體基板上製作一半導體裝置 、、口構之方法’且該石夕層帶有包含氧化石夕的隔離區域，該 方法包含： 128704.doc 200845230 在該石夕層第一區域上形成第一閘極結構及在該矽層第 一區域上形成第二閘極結構，其中該第一區域用於形成 不同於在該第二區域内形成之電晶體類型之電晶體類 型； /口 〇弟一閘極及該第二閘極之側壁形成氮化物側壁 隔層； a 在該第一區域及該第二區域上形成第一絕緣層，其中 可相對於該第-絕緣層有選擇地㈣石夕，且可相對於氧 化石夕及氮化物有選擇地蝕刻該第一絕緣層； ^亥弟-區域上移除掉該第一絕緣層以保留該第二區 域上的該第一絕緣層之剩餘部分； 在田比鄰該第一閘極 _ 以形成凹槽； "弟-£域内使該半導體層凹陷 该材料包含由 在該等凹槽中石曰a e 肀μ日日生長一半導體材料 矽碳與矽鍺組成之群中之一者；及 U 移除掉該第—絕緣層之該剩餘部分。 21. 如請求項20之方法，其進-步包含： 在該第-絕緣層上形成—層氧化物層； 在貫施移除掉該第—絕緣層之該步 化物層以形成-圖案化氧化物層；及 》案化该乳 在實施該磊晶生長步驟 該圖案化氧化4勿層。 在^先該等凹槽期間蚀刻 22. 如請求項21之方法，其進一步包含： 在移除掉該第一絕 、θ b彳餘部分之該步騍後，在該第 128704.doc 200845230 ，在該第 且該第二 區域上形成一具有第一應力類型之應力層；> 多除掉δ亥第一絕緣層剩餘部分之該步驟後 一區域上形成一具有第二應力類型之應力層， 應力類型與該第一應力類型不同。 128704.doc
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