200844276 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種單結晶氧化鋅基板之製法，更詳言 之，係有關一種半導體裝置之建構中所使用的單結晶氧化 鋅基板。 【先前技術】 於半導體製造領域中，寬間隙（wide gap)半導體（係指 $ 帶間隙（band gap)大的半導體），深切企求開發擔當下一世 代之藍色、紫色、紫外線領域之發光二極管等的光半導體、 或低損失能量裝置之材料。主要的寬間隙半導體之一，係 .爲以氧化鋅（ZnO)作爲典型的II族氧化物，特別是由於ZnO ， 爲直接過渡型、帶間隙爲3.37eV之大値，且激發鍵結能量 爲6OmeV之極大値，故隱藏了具有短波長之高效率發光裝 置等的可能性極大。 另外，由一種半導體材料開發裝置、予以商品化，於 φ 廣泛範圍利用時，該半導體材料爲高品質且可以較低成本 予以製造’係爲重要。Zn〇就原材料本身、在地殼中豐富 存在而言係爲低價，惟無法作爲構成半導體裝置之材料， 直至目前作爲轉位殘缺密度較低的單結晶Zn0基板予以供 應者，係爲僅在藍寶石基板上使單結晶ΖηΟ成長者。然而， 藍寶石與ΖηΟ結晶之格子不整合度約爲1 8 %之大値。因此， 在藍寶石基板上之單結晶ΖηΟ薄膜上容易產生粒界或格子 面方向之晃動情形，不易形成高品質之單結晶ΖηΟ薄膜， 就推展開發基於單結晶ΖηΟ基板之發光裝置等而言係爲阻 200844276 害的要因之一。而且，由於藍寶石基板極爲高價，故使用 該物作爲基板所製造的單結晶zn〇基板變得極爲高價，因 此，就該以基於單結晶ZnO基板所開發的裝置而言係爲極 大的阻害要因。 於曰本專利第3 1 8 3 93 9號（專利文獻1)中，揭示藉由於 同一裝置內、使單結晶矽基板在沒有暴露於大氣下，在單 結晶矽基板面上形成由碳化矽（SiC)所形成的薄膜，且在該 薄膜上形成單結晶ZnO薄膜，以製造單結晶ZnO薄膜之方 法。藉由在同文獻中記載的方法，係以使單結晶矽基板在 約1 350 °C下進行加熱，且於其中供應例如載體氣體（氫氣等） 中之碳化氫氣體等方法，在單結晶矽基板面上形成〇. 2〜 3μιη(較佳者爲2〜3m m)之SiC薄膜，然後於其上形成單結 晶 Ζ η 0。 然而，該方法在SiC薄膜之形成階段中無法以該物作 爲單結晶製得，惟即使可製得時，本發明人確認（數據中沒 有表示）會有結晶混亂情形、產生極多的缺陷。因此，在所 得的SiC薄膜上所成長的單結晶ZnO，亦會有很多的缺陷， 無法達到適合實用的品質。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for producing a single crystal zinc oxide substrate, and more particularly to a single crystal zinc oxide substrate used in the construction of a semiconductor device. [Prior Art] In the field of semiconductor manufacturing, wide gap semiconductors (referred to as semiconductors with a large band gap) are deeply developed to develop light-emitting diodes in the blue, purple, and ultraviolet fields for the next generation. Materials such as optical semiconductors, or low loss energy devices. One of the main wide-gap semiconductors is zinc oxide (ZnO) as a typical Group II oxide, especially ZnO, which is a direct transition type with a gap of 3.37 eV and excitation bond energy. The 6OmeV is extremely ambiguous, so there is a great possibility of hiding a high-efficiency light-emitting device having a short wavelength. Further, when a semiconductor material development device is commercialized and used in a wide range of φ, it is important that the semiconductor material is of high quality and can be manufactured at a low cost. Zn〇 is low in terms of the raw material itself and abundant in the earth's crust, but it cannot be used as a material for a semiconductor device. Until now, it is supplied as a single crystal Zn0 substrate with a low indexing defect density, which is only in sapphire. A single crystal ΖηΟ is grown on the substrate. However, the lattice incompatibility of sapphire and ΖηΟ crystals is about 18%. Therefore, the single crystal ΖηΟ film on the sapphire substrate is likely to be swayed in the grain boundary or the lattice direction, and it is difficult to form a high-quality single crystal ΖηΟ film, and the light-emitting device based on the single crystal ΖηΟ substrate is developed. One of the causes of the damage to 200844276. Further, since the sapphire substrate is extremely expensive, the single crystal zn 〇 substrate produced by using the material as a substrate is extremely expensive, and therefore, it is an extremely important factor for the device developed based on the single crystal ZnO substrate. In Japanese Patent No. 3 1 3 3 93 9 (Patent Document 1), it is disclosed that a single crystal germanium substrate is formed of tantalum carbide on a single crystal germanium substrate surface without being exposed to the atmosphere in the same device. A film formed of SiC) and a single crystal ZnO thin film formed on the film to produce a single crystal ZnO thin film. By a method described in the same literature, a single crystal germanium substrate is heated at about 1350 ° C, and a method such as a hydrocarbon gas in a carrier gas (hydrogen gas or the like) is supplied thereto, in a single crystal germanium. A SiC film of 2 to 3 μm (preferably 2 to 3 m m) is formed on the surface of the substrate, and then a single crystal Ζ η 0 is formed thereon. However, this method cannot be obtained by using the object as a single crystal in the formation stage of the SiC film, but even if it can be obtained, the inventors confirmed (not indicated in the data) that there is a crystal disorder and a large number of defects. Therefore, the single crystal ZnO grown on the obtained SiC film also has many defects, and it is impossible to achieve a practical quality.
此外’於半導體裝置中減少自矽層外漏的電流、即降 低寄生容量，提高電晶體之性能的基板，係使用在單結晶 矽層下具備絕緣層[二氧化矽（Si 0 2)層等]者之SOI (矽•在 •絕緣層）基板，係爲已知。使用SOI基板形成單結晶siC 層的方法，提案使SOI基板在碳化氫系氣體中進行加熱， 使表面之單結晶矽層改性成單結晶SiC層，於該層上使SiC 200844276 進行定向附晶成長的方法（專利文獻2)。 另外，提案一種單結晶ZnO基板之製法，其特徵爲使 SOI基板在碳化氫氣體氣氛中進行加熱，使表面之單結晶 矽層改性成單結晶SiC層，視其所需就在該表面上使SlC 進行定向附晶成長以使單結晶S i C層成長而言，於其上使 Zn〇進行定向附晶成長以形成單結晶ZnO層（專利文獻3、 於本發明提出申請時尙未公開）。然而，詳細進行檢討的結 果’本發明人寺發現直接進彳了該專利文獻3之方法，不易 製得高品質的SiC層，無法以該方法製得轉位殘缺密度低 的單結晶Zn〇基板。 因此’仍然企求可以較低成本製造高品質的單結晶 Zn〇基板的技術。 此外’亦報告有藉由犧牲氧化及氟酸等除去SOI基板 表面之單結晶矽層，予以極薄化成5nm的程度，且使該物 在碳化氫氣體氣氛中進行加熱，使表面之單結晶矽層改性 成單結晶SiC層，藉由於其上藉由定向附晶成長積層Sic、 予以厚度化’製得高品質之單結晶SiC基板（參照非專利文 獻1)。 專利文獻1:日本專利第3 1 83939號公報 專利文獻2:日本特開2006-228763號公報 專利文獻3:日本特願2005-297687號 非專利文獻丨：「產學官連攜總合論文集」要旨集、 第1〜11頁、大阪府立大學產學官連攜機構、平成18年2 月28曰 200844276 【發明内容】 發明欲解決之問題 於上述背景中，本發明之一目的係爲提供一種使高品 質之單結晶Zn〇基板，與習知相比時以較低成本製造的方 法。 本發明之另一目的係提供一種藉由該方法，與習知相 比時爲較低成本且高品質的單結晶Ζη〇基板。 解決問題之手段 本發明人等發現於具有表面之單結晶矽層與設於其下 方之Si〇2絕緣層的基板中，使單結晶矽層之表面氧化、除 去，形成約數nm之厚度的薄層，在加熱下於其中供應載體 中之碳化氫氣體，使全層變換成SiC時，製得平坦性極佳 的單結晶SiC層，在該平坦的SiC層上藉由使用化學氣相 成長法（CVD)，在所定的加熱條件下可容易形成轉爲殘缺密 度極低的單結晶ZnO層。本發明以該見解爲基準，再三深 入硏究檢討所完成者。 換言之，本發明提供下述者。 1.一種單結晶ZnO基板之製法，其係爲單結晶氧化鋅 基板之製法，其特徵爲包含 (a) 準備含有Si〇2絕緣層、與設置於該絕緣層上之構成表面 的單結晶矽層的半導體基板之步驟， (b) 使該半導體基板之單結晶矽層自表面側，在絕緣層上單 結晶矽層殘留厚度僅爲3〜7nm下予以氧化的步驟， (c) 將步驟（b)中氧化所產生的表面側Si〇2層自殘留的單結 200844276 晶矽層上去除之步驟， (d) 在所殘留的單結晶矽層上進行加熱，且供應載體氣體與 碳化氫氣體，使該殘留的單結晶矽層之全層變換成單結晶 SiC層之步驟， (e) 在單結晶SiC層之表面上藉由化學氣相成長以形成厚度 爲0.1〜5// m之單結晶ZnO層的步驟， (f) 使步驟（e)所形成的單結晶ZnO層以規定溫度進行煅燒 的步驟， ^ (g)步驟（f)經煅燒的單結晶ZnO層之表面上藉由化學氣相 成長以形成單結晶ZnO層，而使全體單結晶ZnO層之層厚 增加的步驟。 2. 如上述1之製法，其中步驟（d)係爲在基板溫度爲 125 0°C以上、未達1 405 °C下進行者。 3. 如上述1或2之任一製法，其中步驟（d)中對該載體 氣體之供應量而言該碳化氫氣體供應量，以體積比爲〇· 1 〜0 · 8 % 〇 4. 如上述1〜3中任一製法，其中該載體氣體爲氫氣。 5. 如上述1〜4中任一製法，其中步驟（e)及（g)中單結晶 Zn〇層之形成，係藉由使基板加熱且於其中供應鋅源氣體 及氧源氣體者。 6. 如上述5之製法，其中該鋅源氣體係爲含有二（低級） 烷基鋅所成者。 7. 如上述5或6之製法，其中該氧源氣體係爲選自氧、 二氧化碳、水、一氧化碳、二氧化氮、及一氧化氮所組成 -10 - 200844276 成之群者。 8. 如上述1〜7中任一製法，其中步驟（e)中單結晶zn〇 層之形成係在基板溫度300°C以上、未達800°C下進行者。 9. 如上述1〜8中任一製法，其中步驟（f)中煅燒處理係 在基板溫度500°C以上、未達i〇〇〇°c下進行者。 10. 如上述1〜9中任一製法，其中步驟（g)中單結晶Zn〇 層之形成係在基板溫度爲400°C以上、未達900°C下進行者。 11. 如上述1〜10中任一製法，其中該半導體基板係爲 ® 含有在該Si〇2層下載負該物之基層者。 12. 如上述11之製法，其中該基層係爲單結晶或多結 晶矽層。 13. 如上述11或12之製法，其中另外含有該基層、該 基層及該Si〇2層、自該基層至該單結晶SiC層爲止、或自 該基層至步驟（e)所形成的單結晶ZnO層之全層，自與該單 結晶SiC層之界面側除去以步驟（g)所形成的單結晶Zn〇層 0 中部分厚度的步驟。 14. 如上述13之製法，其中該部分厚度相當於自與該 單結晶SiC層之界面至10/zm以內之厚度的部分。 15. 如上述13或14之製法，其中另外含有在該藉由除 去而於所殘留的基板裏面形成光反射層之步驟。 1 6 .如上述1 4之製法，其中該光反射層係爲選自鋁、 銀或此等合金所組成之群者。 17.如上述16之製法，其除去至少自該基層至該Si〇2 層爲止者 -11 - 200844276 18·如上述17之製法，其中在該光反射層之裏面另外 含有可焊接的金屬層之步驟。 1 9 ·如上述1 8之製法，其中該可焊接的金屬係含有選 自銅、鎳及此等合金所組成之群的金屬所形成者。 20·—種單結晶ΖηΟ基板，其特徵爲藉由如上述1〜19 中任一製法所製得。 21.如上述20之單結晶ΖηΟ基板，其中該單結晶Ζη〇 之轉位殘缺密度爲107/cm2以下。 發明效果 由上述構成所形成的本發明，可形成高品質之單結晶 Zn〇層[表面爲（000 1)面]。此係除了單結晶ΖηΟ及單結晶 SiC之格子定數差與藍寶石之格子定數差相比時較小外，另 一要因係於本發明中就使S i 0 2絕緣層上之單結晶矽層形成 3〜7nm之超薄膜而言，使其全層予以SiC化所得的層與使 較厚的單結晶矽層予以SiC化時相比，可得極爲平坦的SiC 表面（藉由本發明人等確認）。換言之，本發明亦發現該超 薄膜SiC表面（形成3C-SiC之（111)面）的平坦性，於其上另 外使S iC進行定向附晶成長以增加層厚時，與層厚成比例， 變得顯著粗糙，與當初的表面粗糙度約0.2nm(RMS)相比 時，層厚每增加10nm時，表面粗糙度各約增加lnm(RMS)。 因此，就使Si〇2絕緣層上之單結晶矽層爲3〜7nm之超薄 膜而言，使該物予以SiC化所得的層，雖藉由其極度之薄 度化爲不具強度者，惟沒有於其上另外積層SiC層以增加 厚度與強度時，直接使用於單結晶ΖηΟ之成長，可得優異 -12- 200844276 品質之單結晶Zn〇層。另外，該超薄膜Sic層多少容易具 有伸縮性，且使該層自下方控制的Si〇2絕緣層爲非晶質， 由於在加熱下具有柔軟性，不會妨礙Sic層之稍微伸縮性。 由此等可知，該超薄膜SiC與其上成長的單結晶ZnO間之 格子不整合情形，可藉由僅SiC層之結晶格子的伸縮作用 予以緩和。此係與超薄膜SiC層表面之高度平坦性有關， 可使於其上成長的單結晶ZnO之轉位殘缺密度顯著降低， 且可賦予高品質之單結晶ZnO層。如此本發明可製造轉位 ^ 殘缺密度爲107/cm2以下之高品質的單結晶基板。 而且，本發明由於使用在由單結晶或多結晶矽所形成 的基層上積層Si〇2絕緣層及單結晶矽層，因此，與藍寶石 基板相比時，可以使用極爲低價取得的S 01基板，故可提 供遠較於習知者更爲低成本的高品質單結晶ZnO基板。此 外，由於可以低價取得該矽基底之S 01基板與由藍寶石表 面上所形成的單結晶ZnO層所成的基板相比時爲極大口徑 I 者，故可以低成本製造具有遠較於習知者更大口徑且高品 質的單結晶ZnO基板。 另外，本發明使用具有非光透過性基層（單結晶矽、多 結晶矽等）之半導體基板作爲材料時，藉由除去該非光透過 性基層，可以低成本製造全體具有光透過性之單結晶Ζη〇 基板。 此外，本發明光反射層之形成，係在藉由該物所得的 單結晶ZnO基板上構成發光二極管時，自該發光層放射至 全方向（立體角4 7Γ )之光中，藉由使朝後方（設置有發光二 13- 200844276 極管之機器內部方向）之光朝向前方（立體角2 ττ )進行方向 轉換，提高光取出效率，且藉此可防止發光二極管之溫度 上昇情形。而且，反射層就在含有藍色波長範圍之可視光 中具有高反射效率之金屬而言，以使用鋁、銀或此等之合 金極爲有效。另外，在反射層上另外設置附有可焊接的金 屬層時，可提高光取出效率下利用該物作爲電極，可使設 計使用發光二極管之機器的自由度，在不會損害光產生或 .取出效率下予以提高。 【實施方式】 爲實施發明之最佳形態 製造本發明之單結晶ΖιιΟ基板時所使用的半導體基 板，只要是使表面單結晶矽層控制Si〇2絕緣層之形態的SOI 基板即可，其他沒有特別的限制。以較低成本、容易取得 的SOI基板之較佳例，係爲在單結晶矽基板表面下具備Si〇2 絕緣層，於其下方具有控制該層之基層的矽結晶層者（Si/ Si〇2/Si)。此時，於本發明中由於可使用在絕緣層上形成有 單結晶矽層之基板，故在位於Si〇2層下方，支持該層的基 層可爲單結晶较，或爲多結晶砂。 [表面之單結晶矽層的犧牲氧化] 第1(a)圖係爲上述之現在可以較低成本取得的SOI基 板例的截面槪念圖解（而且，圖中各層之厚度與實際之厚度 無關）。該基板之典型例，係在Si〇2絕緣層2上形成約45nm 之單結晶矽層丨，構成該半導體基板之（上側）表面。在Si〇2 絕緣層2之下方存在控制該層之基層的矽結晶層（單結晶或 -14 - 200844276 多結晶）。Si〇2絕緣層2上側表面之單結晶矽層1的氧化處 理，可以該領域中已知的任何方法作爲犧牲氧化處理。對 S 01基板表面之單結晶矽層1而言，使未氧化的單結晶矽 層1’在Si〇2絕緣層2上以3〜7nm之厚度殘留下進行氧化 處理（參照第1(b)圖）。因此，此氧化步驟之各條件以該業 者之慣用方法予以適當設定，該調整係爲該業者之日常作 業事項。設定條件後，可在同一條件下處理材料基板。例 如，可藉由在大氣壓、基板溫度1000°C下，使氧氣以lOOOcc/ 分鐘流通約110分鐘，再藉由在基板溫度1100°C下使氧氣 以lOOOcc/分鐘流通約40分鐘等，進行該處理。溫度及氧 氣供應量以及處理時間，可視表面之單結晶矽層的厚度予 以適當調整。單結晶矽被氧化形成Si〇2層時，層厚約增加 2.25倍。因此，由單結晶矽層中被氧化的厚度可求得被氧 化後之厚度增加量，於條件設定時，亦可以此作爲指標。 [犧牲氧化層之除去] 除去藉由上述處理所產生的表面之Si 〇2犧牲層4，亦 可使用任何於半導體業界中爲除去單結晶矽之表面的Si〇2 時所常用的已知方法進行。典型例如可藉由浸漬於氟酸（HF 濃度例如爲1〜50%者）予以進行。浸漬時間係與Si〇2犧牲 層之厚度與氟酸之HF濃度有關，惟Si〇2犧牲層之厚度爲 lOOnm、氟酸之HF濃度爲10%時，浸漬時間在室溫下可爲 約1 0分鐘。另外，亦可使用緩衝氟酸（在H F水溶液中加入 氨者。在商業上可取得者）取代氟酸。於洗淨後，製得在表 面上具有乾淨、3〜7nm之薄單結晶矽層1 ’的基板（參照第 -15- .200844276 1 (c)圖）。 [單結晶矽層變換成單結晶s i C層] 使藉由上述處理所得的表面之3〜7nm厚度的單結晶 矽層Γ變換成單結晶SiC層，係可藉由使基板在1 250 °C 以上、未達1405 °C之溫度下進行加熱，且使載體氣體（較佳 者爲氫氣）與碳化氫氣予以接觸進行。單結晶矽層丨，爲3 〜7nm之極薄厚度且該層僅於Si〇2絕緣層2上時，可容易 • 製得極高品質之單結晶SiC層5(3C-SiC。表面爲（111)面）（參 照弟1(d)圖）。單結晶矽層藉較該層更厚時，即使使該層以 碳化氫/載體進行處理，仍無法製得平坦的S i C層，即使處 理時間變長時，會有SiC成長成粒狀、多結晶化的傾向。 處理時之基板溫度以1 290〜1 390°C較佳，以1 320〜1 3 80°C 更佳，例如約爲135 0°C。而且，使用的碳化氫氣體可適當 選自容易取得者即可，沒有特別的限制，通常使用丙烷較 爲方便。處理可在大氣壓〜真空之任何氣壓中進行，以在 φ 大氣壓下進行較佳。對載體氣體量而言氫氣之體積比例， 以0·1〜0.8%較佳，以0.2〜0.7%更佳，通常例如設定於約 0.5%左右。可以載體氣體及碳化氫氣體之供應量爲宜，在 大氣壓下例如可各約爲lOOOOcc/分鐘及50cc/分鐘。 [單結晶ZnO層之形成] 在藉由上述所形成的單結晶SiC層5上藉由化學氣相 成長形成單結晶ZnO層，可使用該業者習知的適當材料作 爲鋅源、氧源，沒有特別的限制。鋅源例如二（低級）烷基 鋅（此處，「低級」係指碳數1〜6個者）。具體而言，例如 -16- 200844276 二甲基鋅、二乙基鋅 '二異丙基鋅、二丁基鋅、二（第2-丁基）鋅等。氧源例如氧、二氧化碳、水、一氧化碳、二氧 化氮、一氧化氮等。單結晶ΖηΟ層之形成，係基於以下述 步驟（1)〜（3)予以進行。 (1)單結晶Ζη〇緩衝層的形成 單結晶Ζη〇層[表面爲（000 1 )面]之形成，係使單結晶 ΖηΟ層到達0.1〜5 μ m之範圍內的所定厚度（以適當設定爲 佳）爲止，適當設定基板溫度爲宜，較佳者爲300°C以上、 更佳者爲350°C以上、最佳者爲500°C以上，且未達1200 °C、較佳者未達800°C、更佳者未達750°C、最佳者未達700 °C (使該單結晶ΖηΟ層形成步驟稱爲「緩衝層形成步驟」）（參 照第1(e)圖）。緩衝層形成步驟中基板溫度之適當例，如約 500°C。在該溫度範圍進行處理時，防止SiC層5上最初所 形成的單結晶ΖηΟ層（緩衝層6)之表面形態混亂情形，係爲 重要。 緩衝層形成步驟係可在大氣壓〜真空下等任一環境下 進行。處理例如在真空下進行時，ΖηΟ源（例如二（低級）烷 基鋅）之供應量以0.1〜10cc/分鐘較佳，氧源之供應量以10 〜1000cc/分鐘較佳。例如ΖηΟ源之供應量約爲lcc/分鐘， 氧源之供應量各爲約100cc/分鐘等。另外，在真空下進行 處理時，成長壓力以0.0 1〜1 OPa較佳，例如約爲0.1 Pa。 (2)煅燒處理 緩衝層6爲調整結晶ΖηΟ之結晶中存在的混亂情形 時，實施煅燒處理（第1(f)圖）。煅燒時之基板溫度可適當設 -17- 200844276 定，較佳者爲500°C以上、更佳者爲600°C以上，且未達1405 °C、較佳者未達1 200°C、更佳者未達l〇〇〇°C、最佳者未達 800°C。煅燒時基板溫度之適合例，爲650°C。煅燒處理係 在氧氣氣氛下進行較佳。煅燒處理可在大氣壓〜真空下等 任一環境中進行。在真空下進行煅燒處理時，氧氣之供應 量爲100〜1 000 0cc/分鐘，壓力爲0,1〜l〇〇Pa。煅燒處理係 以高溫下短時間處理爲宜，例如以使用燈加熱型熱處理爐 較佳。而且，來自Si/Si〇2/Si型SOI基板之3丨〇2層，於煅 燒處理時（特別時降溫時）具有抑制基板產生彎曲的情形， 此係對於形成高品質之單結晶ZnO基板時特別有利。 (3)單結晶ZnO之厚膜的形成 緩衝層6進行煅燒處理後，藉由化學氣相成長另外形 成單結晶ZnO層以進行厚膜化處理（該步驟稱爲「厚膜形成 步驟」）（第1(g)圖）。藉由該步驟，形成含有最初所形成的 緩衝層6之厚膜的單結晶ZnO層6’ [表面爲（0001)面]。厚 膜形成步驟可適當設定基板溫度，且進行單結晶ZnO層之 成長（參照第1(g)圖）。基板溫度以400 °C以上較佳、以500 °C以上更佳，且以未達1405°C較佳、更佳者未達900°C、 更佳者未達800°C、尤佳者未達700°C、最佳者未達600°C。 與緩衝層形成步驟相同地，厚膜形成步驟可在大氣壓 〜真空下等任一環境中進行。處理例如在真空下進行時， ZnO源（例如二（低級）烷基鋅）之供應量以i〜100cc/分鐘較 佳，氧氣之供應量爲100〜10000cc/分鐘較佳。在真空下進 行處理時，成長壓力爲0.1〜l〇〇Pa較佳，例如約爲l.〇pa -18- 200844276 於厚膜形成步驟中所形成的單結晶ZnO層之厚度，可視各 種具體用途而定予以適當設定，沒有特別的限制，爲1 00 〜3 00/zm，就可使基板具有適當的強度、且可確保充分的 製造效果而言，通常爲較佳者。 並不一定爲必須，亦可使上述緩衝層形成步驟及厚膜 形成步驟中所形成的單結晶ZnO層6’ ，視其所需進行繼 後的緞燒處理。實施煅燒處理時，其條件係與有關緩衝層 之煅燒處理之上述條件相同。此時於煅燒處理時（特別是降 溫時）具有抑制基板產生彎曲的情形，此係對於形成高品質 之單結晶ZnO基板時特別有利。 經由以上述一連串適當範圍之條件的處理步驟，可形 成轉位殘缺密度107/cm2以下，較佳者爲106/cm2以下之單 結晶ZnO層6’ 。 以由Si/ Si〇2 /Si所形成的SOI基板作爲出發材料，所 製造的單結晶Zn〇基板（Zn〇/SiC/ Si〇2 /Si基板），可直接使 用作爲基板，亦可除去自裏面側至企求的位置之部分。除 去係可使用化學機械硏磨之該業者所習知的適當方法。順 序個別除去各層時，例如可使用下述之方法。 [矽基層之除去]In addition, in a semiconductor device, a substrate that reduces leakage current from the ruthenium layer, that is, reduces parasitic capacitance, and improves the performance of the transistor, is provided with an insulating layer [cerium oxide (Si 0 2) layer, etc. under a single crystal germanium layer. The SOI (矽••• insulating layer) substrate is known. In the method of forming a single crystal siC layer using an SOI substrate, it is proposed to heat the SOI substrate in a hydrocarbon gas to modify a single crystal ruthenium layer on the surface into a single crystal SiC layer, and SiC 200844276 is subjected to directional epitaxy on the layer. Method of growth (Patent Document 2). In addition, a method for preparing a single crystal ZnO substrate is proposed, which is characterized in that an SOI substrate is heated in a hydrocarbon gas atmosphere to modify a single crystal ruthenium layer on the surface into a single crystal SiC layer, which is required on the surface as needed. Orienting epitaxial growth of the SlC to grow the single crystal Si C layer, and subjecting the Zn 定向 to epitaxial epitaxial growth to form a single crystal ZnO layer (Patent Document 3, which is not disclosed when the present application is filed) ). However, as a result of the detailed review, the inventors of the present invention found that the method of Patent Document 3 was directly incorporated, and it was difficult to obtain a high-quality SiC layer, and a single-crystal Zn〇 substrate having a low indexing defect density could not be obtained by this method. . Therefore, there is still a demand for a technology for manufacturing a high quality single crystal Zn ruthenium substrate at a relatively low cost. In addition, it has been reported that a single crystal ruthenium layer on the surface of the SOI substrate is removed by sacrificing oxidation and hydrofluoric acid, and is extremely thinned to a thickness of 5 nm, and the object is heated in a hydrocarbon gas atmosphere to cause a single crystal of the surface. The layer is modified into a single-crystal SiC layer, and a high-quality single-crystal SiC substrate is obtained by growing the layer Sic by orientation-attached crystal growth (see Non-Patent Document 1). Patent Document 1: Japanese Patent No. 3 1 83939 Patent Document 2: JP-A-2006-228763 Patent Document 3: Japanese Patent Application No. 2005-297687 Non-Patent Document 丨: "Collection of Industry, University, and Government The purpose of the present invention is to provide a solution to the problems of the invention. In the above background, one of the objects of the present invention is to provide a solution to the problems of the inventions and the agencies of the Osaka University of Technology, February 28, 2008. A method of manufacturing a high quality single crystal Zn ruthenium substrate at a lower cost than conventionally known. Another object of the present invention is to provide a single crystal Ζ 〇 substrate which is a relatively low cost and high quality by this method as compared with the prior art. Means for Solving the Problems The present inventors have found that a surface of a single crystal ruthenium layer having a surface and a Si 〇 2 insulating layer provided under the surface are oxidized and removed to form a thin thickness of about several nm. a layer in which a hydrocarbon gas in a carrier is supplied under heating to convert a full layer into SiC, thereby obtaining a single crystal SiC layer having excellent flatness, by using a chemical vapor growth method on the flat SiC layer (CVD), a single crystal ZnO layer which is converted to an extremely low residual density can be easily formed under predetermined heating conditions. The present invention is based on this insight and is further incorporated into the review of the review. In other words, the present invention provides the following. A method for producing a single crystal ZnO substrate, which is a method for producing a single crystal zinc oxide substrate, comprising: (a) preparing a single crystal germanium containing a Si〇2 insulating layer and a constituent surface provided on the insulating layer a step of layering a semiconductor substrate, (b) a step of oxidizing a single crystal ruthenium layer of the semiconductor substrate from the surface side, and a single crystal ruthenium layer having a residual thickness of only 3 to 7 nm on the insulating layer, (c) a step ( b) a step of removing the surface side Si 〇 2 layer produced by the oxidation from the residual single junction 200844276 wafer layer, (d) heating on the remaining single crystal ruthenium layer, and supplying the carrier gas and the hydrocarbon gas a step of converting the entire layer of the residual single crystal ruthenium layer into a single crystal SiC layer, (e) growing by chemical vapor phase on the surface of the single crystal SiC layer to form a single thickness of 0.1 to 5//m a step of crystallizing the ZnO layer, (f) a step of calcining the single crystal ZnO layer formed in the step (e) at a predetermined temperature, ^ (g) step (f) by chemically oxidizing the surface of the single crystal ZnO layer Gas phase growth to form a single crystal ZnO layer, so that the entire single crystal ZnO layer The step of increasing layer thickness. 2. The method according to the above 1, wherein the step (d) is carried out at a substrate temperature of 125 ° C or higher and less than 1 405 ° C. 3. The method according to any one of the above 1 or 2, wherein the supply amount of the hydrocarbon gas in the step (d) is a volume ratio of 碳·1 〜0 · 8 % 〇4. In any one of the above 1 to 3, wherein the carrier gas is hydrogen. 5. The method according to any one of the above 1 to 4, wherein the formation of the single crystal Zn 〇 layer in the steps (e) and (g) is performed by heating the substrate and supplying the zinc source gas and the oxygen source gas therein. 6. The method according to the above 5, wherein the zinc source gas system is composed of a di(lower) alkyl zinc. 7. The method according to the above 5 or 6, wherein the oxygen source gas system is selected from the group consisting of oxygen, carbon dioxide, water, carbon monoxide, nitrogen dioxide, and nitrogen monoxide -10 - 200844276. 8. The method according to any one of the above 1 to 7, wherein the formation of the single crystal zn〇 layer in the step (e) is carried out at a substrate temperature of 300 ° C or more and less than 800 ° C. 9. The method according to any one of the above 1 to 8, wherein the calcination treatment in the step (f) is carried out at a substrate temperature of 500 ° C or more and less than i ° ° C. 10. The method according to any one of the above 1 to 9, wherein the formation of the single crystal Zn〇 layer in the step (g) is carried out at a substrate temperature of 400 ° C or higher and less than 900 ° C. 11. The method according to any one of the above 1 to 10, wherein the semiconductor substrate is ® containing a base layer for downloading the negative layer on the Si 2 layer. 12. The method according to the above 11, wherein the base layer is a single crystal or a multi-layered germanium layer. 13. The method according to the above 11 or 12, further comprising the base layer, the base layer and the Si〇2 layer, a single crystal formed from the base layer to the single crystal SiC layer, or from the base layer to the step (e) The entire layer of the ZnO layer is subjected to a step of removing a part of the thickness of the single crystal Zn layer 0 formed by the step (g) from the interface side with the single crystal SiC layer. 14. The method according to the above 13, wherein the portion has a thickness corresponding to a portion from the interface with the single crystal SiC layer to a thickness within 10/zm. 15. The method according to the above 13 or 14, which further comprises the step of forming a light reflecting layer in the remaining substrate by the removing. The method of the above-mentioned 14, wherein the light-reflecting layer is selected from the group consisting of aluminum, silver or alloys thereof. 17. The method according to the above 16, wherein at least the substrate is removed from the base layer to the Si 2 layer. -11 - 200844276 18, wherein the light reflection layer further comprises a weldable metal layer. step. The method of the above 18, wherein the weldable metal is formed by a metal selected from the group consisting of copper, nickel, and alloys thereof. A single crystal ΖηΟ substrate, which is obtained by any one of the above methods 1 to 19. 21. The single crystal ΖηΟ substrate according to 20 above, wherein the single crystal Ζη〇 has an indexing residual density of 107/cm2 or less. Advantageous Effects of Invention According to the present invention formed as described above, a high-quality single-crystal Zn〇 layer [surface (000 1) plane] can be formed. In addition to the fact that the lattice difference between the single crystal ΖηΟ and the single crystal SiC is smaller than that of the sapphire, the other factor is the single crystal 上 on the S i 0 2 insulating layer in the present invention. When the layer is formed into an ultra-thin film of 3 to 7 nm, the layer obtained by SiC-forming the entire layer can obtain an extremely flat SiC surface as compared with the case where the thick single-crystal layer is SiC-formed (by the present inventors, etc.) confirm). In other words, the present invention also finds the flatness of the surface of the ultra-thin film SiC (forming the (111) plane of 3C-SiC), and additionally, when the SiC is subjected to directional epitaxial growth to increase the layer thickness, it is proportional to the layer thickness. It becomes significantly rough, and the surface roughness increases by about 1 nm (RMS) each time the layer thickness is increased by 10 nm as compared with the original surface roughness of about 0.2 nm (RMS). Therefore, in the case where the single crystal ruthenium layer on the Si 〇 2 insulating layer is an ultrathin film of 3 to 7 nm, the layer obtained by SiC-forming the material is not extremely strong by its extremely thinness. When the SiC layer is not additionally laminated thereon to increase the thickness and strength, it is directly used for the growth of the single crystal ΖηΟ, and a single crystal Zn 〇 layer having an excellent quality of -12-200844276 can be obtained. Further, the ultra-thin film Sic layer is somewhat more elastic, and the Si〇2 insulating layer controlled from the lower layer of the layer is amorphous, and has flexibility in heating, and does not hinder the slight stretchability of the Sic layer. From this, it can be seen that the lattice unconformity between the ultrathin film SiC and the single crystal ZnO grown thereon can be alleviated by the stretching action of the crystal lattice of only the SiC layer. This is related to the high flatness of the surface of the ultra-thin film SiC layer, and the translocation density of the single crystal ZnO grown thereon can be remarkably lowered, and a high-quality single crystal ZnO layer can be imparted. Thus, the present invention can produce a high-quality single crystal substrate having a translocation density of 107/cm2 or less. Further, in the present invention, since the Si〇2 insulating layer and the single crystal germanium layer are laminated on the base layer formed of the single crystal or the polycrystalline germanium, the S 01 substrate which is obtained at a very low cost can be used as compared with the sapphire substrate. Therefore, it is possible to provide a high quality single crystal ZnO substrate which is much lower in cost than conventional ones. In addition, since the S 01 substrate which can obtain the ruthenium substrate at a low cost is larger than the substrate formed by the single crystal ZnO layer formed on the surface of the sapphire, it can be manufactured at a low cost and is far superior to the conventional one. A larger diameter and high quality single crystal ZnO substrate. Further, in the present invention, when a semiconductor substrate having a non-light transmissive base layer (single crystal ruthenium, polycrystalline ruthenium or the like) is used as a material, by removing the non-light permeable base layer, it is possible to manufacture a single crystal Ζ η having a light transmittance at low cost. 〇 substrate. Further, in the formation of the light-reflecting layer of the present invention, when the light-emitting diode is formed on the single crystal ZnO substrate obtained from the material, the light is emitted from the light-emitting layer to the light in the omnidirectional direction (solid angle 4 7 Γ) by The light at the rear (the inside direction of the machine in which the light-emitting diodes 13-200844276 is installed) is direction-shifted toward the front (solid angle 2 ττ ) to improve the light extraction efficiency, thereby preventing the temperature of the light-emitting diode from rising. Further, the reflective layer is extremely effective in the use of aluminum, silver or the like in the case of a metal having high reflection efficiency among visible light having a blue wavelength range. In addition, when a solderable metal layer is additionally provided on the reflective layer, the use of the object as an electrode under the light extraction efficiency can be improved, and the degree of freedom of the device using the light-emitting diode can be improved without damaging the light generation or removal. Improve efficiency. [Embodiment] The semiconductor substrate used in the production of the single crystal Ζ ι Ο substrate of the present invention in the best mode for carrying out the invention may be any SOI substrate in which the surface of the single crystal 矽 layer is controlled by the Si 〇 2 insulating layer. Special restrictions. A preferred example of the SOI substrate which is easy to obtain at a lower cost is a Si 2 insulating layer under the surface of the single crystal germanium substrate, and a germanium crystal layer having a base layer for controlling the layer underneath (Si/Si〇). 2/Si). At this time, in the present invention, since a substrate having a single crystal ruthenium layer formed on the insulating layer can be used, the underlayer located under the Si 〇 2 layer can be a single crystal or a polycrystalline sand. [Sacrificial Oxidation of Single Crystalline Layer on Surface] Fig. 1(a) is a cross-sectional illustration of the above-described example of an SOI substrate which can be obtained at a lower cost (and the thickness of each layer in the figure is independent of the actual thickness) . A typical example of the substrate is a single crystal germanium layer of about 45 nm formed on the Si 2 insulating layer 2 to constitute an (upper) surface of the semiconductor substrate. Below the Si〇2 insulating layer 2, there is a germanium crystal layer (single crystal or -14 - 200844276 polycrystal) which controls the base layer of the layer. The oxidation treatment of the single crystal ruthenium layer 1 on the upper side surface of the Si 2 insulating layer 2 can be treated as a sacrificial oxidation treatment by any method known in the art. For the single crystal ruthenium layer 1 on the surface of the S 01 substrate, the unoxidized single crystal ruthenium layer 1 ′ is oxidized by leaving a thickness of 3 to 7 nm on the Si 〇 2 insulating layer 2 (refer to the first (b) Figure). Therefore, the conditions of this oxidation step are appropriately set in the usual manner of the industry, and the adjustment is a daily work of the manufacturer. After the conditions are set, the material substrate can be processed under the same conditions. For example, the oxygen can be circulated at 1000 cc/min for about 110 minutes at atmospheric pressure and a substrate temperature of 1000 ° C, and then the oxygen is allowed to flow at 1000 cc/min at a substrate temperature of 1100 ° C for about 40 minutes. deal with. The temperature and oxygen supply and processing time are appropriately adjusted for the thickness of the single crystal layer of the visible surface. When the single crystal ruthenium is oxidized to form the Si 〇 2 layer, the layer thickness is increased by about 2.25 times. Therefore, the thickness of the oxidized layer can be determined from the thickness of the oxidized single crystal layer, and can be used as an index when the condition is set. [Removal of Sacrificial Oxide Layer] The Si 〇 2 sacrificial layer 4 on the surface generated by the above treatment may be removed, and any known method commonly used in the semiconductor industry to remove Si 〇 2 of the surface of a single crystal ruthenium may be used. get on. Typically, it can be carried out, for example, by immersion in hydrofluoric acid (having a HF concentration of, for example, 1 to 50%). The immersion time is related to the thickness of the Si〇2 sacrificial layer and the HF concentration of the hydrofluoric acid. However, when the thickness of the Si〇2 sacrificial layer is 100 nm and the HF concentration of the hydrofluoric acid is 10%, the immersion time may be about 1 at room temperature. 0 minutes. Alternatively, it is also possible to use a buffered hydrofluoric acid (a commercially available ammonia in an aqueous solution of H F. commercially available) in place of hydrofluoric acid. After washing, a substrate having a clean, thin single crystal ruthenium layer 1' of 3 to 7 nm on the surface was obtained (refer to Fig. -15-.200844276 1 (c)). [Single crystal 矽 layer is converted into a single crystal si C layer] The single crystal yttrium layer having a thickness of 3 to 7 nm on the surface obtained by the above treatment is converted into a single crystal SiC layer by allowing the substrate to be at 1 250 ° C. The above heating is carried out at a temperature of less than 1405 ° C, and a carrier gas (preferably hydrogen) is brought into contact with carbonized hydrogen. The single crystal ruthenium layer is a very thin thickness of 3 to 7 nm and the layer is only on the Si 〇 2 insulating layer 2, and it is easy to produce a very high quality single crystal SiC layer 5 (3C-SiC. The surface is ( 111) Face) (Refer to Figure 1 (d)). When the single crystal ruthenium layer is thicker than the layer, even if the layer is treated with a hydrocarbon/support, a flat Si C layer cannot be obtained, and even if the treatment time becomes long, SiC grows into a granular shape. The tendency to polycrystallize. The substrate temperature during the treatment is preferably 1 290 to 1 390 ° C, more preferably 1 320 to 1 3 80 ° C, for example, about 135 ° ° C. Further, the hydrocarbon gas to be used can be appropriately selected from those which are easily available, and is not particularly limited, and it is usually convenient to use propane. The treatment can be carried out at any pressure from atmospheric pressure to vacuum to carry out at φ atm. The volume ratio of hydrogen to the amount of the carrier gas is preferably from 0.1 to 0.8%, more preferably from 0.2 to 0.7%, and usually, for example, about 0.5%. The carrier gas and the hydrocarbon gas may be supplied in an amount of, for example, about 100 cc/min and 50 cc/min at atmospheric pressure. [Formation of Single Crystal ZnO Layer] A single crystal ZnO layer is formed by chemical vapor phase growth on the single crystal SiC layer 5 formed as described above, and a suitable material known to those skilled in the art can be used as a zinc source or an oxygen source. Special restrictions. A zinc source such as di(lower)alkyl zinc (herein, "lower grade" means a carbon number of 1 to 6). Specifically, for example, -16-200844276 dimethyl zinc, diethyl zinc 'diisopropyl zinc, dibutyl zinc, di(t-butyl) zinc, and the like. Oxygen sources such as oxygen, carbon dioxide, water, carbon monoxide, nitrogen dioxide, nitrogen monoxide, and the like. The formation of the single crystal Ζη layer is carried out based on the following steps (1) to (3). (1) Formation of a single crystal Ζη〇 buffer layer The formation of a single crystal Ζη〇 layer [surface (000 1 ) plane] is such that the single crystal ΖηΟ layer reaches a predetermined thickness in the range of 0.1 to 5 μm (to be appropriately set) Preferably, the substrate temperature is appropriately set, preferably 300 ° C or higher, more preferably 350 ° C or higher, and most preferably 500 ° C or higher, and less than 1200 ° C, preferably not It is 800 ° C, more preferably less than 750 ° C, and the best is less than 700 ° C (the step of forming the single crystal Ζ Ο layer is referred to as "buffer layer forming step") (see Fig. 1 (e)). A suitable example of the substrate temperature in the buffer layer forming step is, for example, about 500 °C. When the treatment is carried out in this temperature range, it is important to prevent the surface morphology of the single crystal Ζη layer (buffer layer 6) formed on the SiC layer 5 from being disordered. The buffer layer forming step can be carried out in any environment such as atmospheric pressure to vacuum. The treatment is carried out, for example, under vacuum, and the supply of ΖηΟ source (e.g., di(lower) alkyl zinc) is preferably 0.1 to 10 cc/min, and the supply of oxygen source is preferably 10 to 1000 cc/min. For example, the supply of ΖηΟ source is about 1 cc/min, and the supply of oxygen source is about 100 cc/min. Further, when the treatment is carried out under vacuum, the growth pressure is preferably 0.01 to 1 OPa, for example, about 0.1 Pa. (2) Calcination treatment The buffer layer 6 is subjected to a calcination treatment (Fig. 1(f)) in order to adjust the disorder in the crystal of the crystal ΖηΟ. The substrate temperature during calcination may be appropriately set to -17-200844276, preferably 500 ° C or higher, more preferably 600 ° C or higher, and less than 1405 ° C, preferably less than 1 200 ° C, more The best is less than l ° ° C, the best is less than 800 ° C. A suitable example of the substrate temperature at the time of calcination is 650 °C. The calcination treatment is preferably carried out under an oxygen atmosphere. The calcination treatment can be carried out in any environment such as atmospheric pressure to vacuum. When the calcination treatment is carried out under vacuum, the supply of oxygen is 100 to 1,000 cc / min, and the pressure is 0, 1 to l 〇〇 Pa. The calcination treatment is preferably carried out at a high temperature for a short period of time, for example, a lamp-heating type heat treatment furnace is preferred. Further, the 3丨〇2 layer from the Si/Si〇2/Si type SOI substrate has a case where the substrate is prevented from being bent during the calcination treatment (in particular, when the temperature is lowered), which is formed when a high-quality single crystal ZnO substrate is formed. Particularly advantageous. (3) Formation of thick film of single crystal ZnO After the buffer layer 6 is subjected to a calcination treatment, a single crystal ZnO layer is additionally formed by chemical vapor deposition to perform a thick film formation process (this step is referred to as a "thick film formation step") ( Figure 1 (g)). By this step, a single crystal ZnO layer 6' [surface (0001) plane] having a thick film of the buffer layer 6 formed first is formed. In the thick film forming step, the substrate temperature can be appropriately set, and the growth of the single crystal ZnO layer can be performed (see Fig. 1(g)). The substrate temperature is preferably 400 ° C or higher, more preferably 500 ° C or higher, and preferably less than 1405 ° C, more preferably less than 900 ° C, and even less than 800 ° C, especially preferably Up to 700 ° C, the best is less than 600 ° C. The thick film forming step can be carried out in any environment such as atmospheric pressure to vacuum, as in the buffer layer forming step. The treatment is carried out, for example, under vacuum, and the supply of the ZnO source (e.g., di(lower) alkyl zinc) is preferably from i to 100 cc/min, and the oxygen supply is preferably from 100 to 10,000 cc/min. When the treatment is carried out under vacuum, the growth pressure is preferably 0.1 to 1 〇〇Pa, for example, about 1. 〇pa -18- 200844276. The thickness of the single crystal ZnO layer formed in the thick film formation step can be used for various specific purposes. The amount is appropriately set, and is not particularly limited, and is preferably from 00 to 3 00/zm, and it is usually preferable because the substrate can have an appropriate strength and a sufficient manufacturing effect can be ensured. It is not necessarily necessary, and the above-described buffer layer forming step and the single crystal ZnO layer 6' formed in the thick film forming step may be subjected to subsequent satin burning treatment as needed. When the calcination treatment is carried out, the conditions are the same as those described above for the calcination treatment of the buffer layer. At this time, it is possible to suppress the occurrence of warpage of the substrate at the time of the calcination treatment (especially when the temperature is lowered), which is particularly advantageous for forming a high-quality single crystal ZnO substrate. The single crystal ZnO layer 6' having an indexing residual density of 107/cm2 or less, preferably 106/cm2 or less, can be formed by a treatment step under the above-described conditions of a series of appropriate ranges. A single crystal Zn〇 substrate (Zn〇/SiC/Si〇2/Si substrate) produced by using an SOI substrate formed of Si/Si〇2/Si can be used as a substrate or removed. Inside the side to the part of the desired position. In addition to the system, a suitable method known to the practitioner of chemical mechanical honing can be used. When the layers are individually removed in order, for example, the following method can be used. [Removal of base layer]
藉由除去不透明的裏面側之矽結晶層3(基層：厚度通 常與所使用的晶圓之口徑有關，爲200〜800 # m)，可製得 對光而言透明的單結晶 Zn〇基板（Zn〇/SiC/ Si〇2)(參照第 2(h)圖）。矽結晶層3之除去，可使用K0H水溶液予以進行， 例如藉由較佳者爲5〜50重量％，更佳者爲20重量％之K0H 19- 200844276 水溶液中、60〜95 °C (較佳者爲80°C )下浸漬予以進行。對 直徑8吋之SOI基板（矽層厚：約800 // m)而言，使用20重 量％之K0H水溶液（80°C )時，基板之浸漬時間約爲800分 鐘（鈾刻速度：約1 // m/分鐘）。而且，預先藉由K0H水溶液 進行處理，進行硏磨（例如化學機械硏磨），亦可使矽層硏 磨至例如約1 00 V m之厚度爲止。 [SiCh絕緣層之除去] | 除矽結晶層外，亦可另外除去Si〇2絕緣層2。由於藉 由除去SiCh絕緣層2所得的單結晶ZnO基板之裏面爲SiC 面（第2(i)圖），故形成導電性，可直接在裏面接合電極。si〇2 層之除去方法，係與有關SiCh犧牲層之除去方法的上述者 相同。現在市售的 SOI基板中Si〇2絕緣層之厚度爲約 150nm，在10 %氟酸中浸漬時，可在約15分鐘內除去。 [SiC層之除去] 視其所需，亦可另外除去SiC層5，藉此可製得僅由單 φ 結晶ZnO所形成的基板（參照第2(j)圖）。SiC層5之除去， 例如可使用乾式蝕刻處理。乾式鈾刻處理例如在真空中使 CF4氣體僅以0.1〜lOOcc/分鐘（例如i〇cc/分鐘）之供應量供 應給SiC層5，且藉由並行平板進行電弧放電處理。此時， 反應室之真空値可爲10〜lOOOOPa，較佳者爲約100Pa。而 且’亦可藉由硏磨（例如化學機械硏磨）取代乾式蝕刻處 理，以除去SiC層。 [單結晶ZnO層之部分除去] 另外’視其所需亦可僅除去單結晶Zn〇層6，之裏面 -20- .200844276 側具有的厚度。除去的厚度係以含有原有的緩衝層6之部 分作條件，止於1 〇 m以內。亦可除去大於1 〇 # m，惟藉 由1 0 // m以內之除去，可使已經充分的高品質之裏側呈 現，故不需進一步除去至大於該範圍且沒有效益可言。單 結晶ZnO層6’之裏面側的除去，例如可藉由化學機械硏 磨予以進行。 [反射層、電極層之形成] 至少於除去不透明層（矽結晶層3)後之上述單結晶Zn〇 基板的裏面，亦可形成反射層。反射層形成材料，以金屬 較佳，以銘、銀或此等之合金更佳。由金屬所成的反射層 之形成，例如可使用濺射法，由於該方法爲該業者所習知 慣用的方法，故可適當設定操作條件等。至少除去至Si〇2 絕緣層2之裏面形成金屬層時，金屬層爲反射層時，同時 可使用作爲電極層。另外，由於可於由鋁、銀或此等之合 金所成的金屬層表面上進行焊接，故可另外形成更適合於 I 該物之金屬層。該金屬之典型例，如銅、鎳或此等之合金。 同時可容許含有可焊接的除此等金屬外之金屬爲使可焊接 的金屬層形成時，與反射層之形成相同地，例如可使用濺 射處理。 實施例 於下述中，參照實施例更具體地說明本發明，惟本發 明不受此等實施例所限制。 (1) SOI基板之表面層上氧化膜的形成與除去 使用市售的SOI基板[UNIB0ND(註冊商標）、信越半導 -21- 200844276 體（股）製、直徑200nm、表面單結晶矽層厚45nm]。使其置 於電氣爐，在1000 °C下進行加熱，以1氣壓、使〇2氣體以 lOOOOcc/分鐘之供應量流通180分鐘。自電氣爐取出SOI 基板，在HF水溶液（5重量％)中、室溫下浸漬10分鐘。使 基板以超純水、藉由常法進行洗淨、乾燥。使Si〇2絕緣層 上之單結晶矽層之厚度爲5nm(藉由分光橢圓對稱法予以測 定）。 (2) 表面Si層改性成SiC層 藉由使實施有上述處理之SOI基板置於燈加熱型處理 爐中，於1 350 °C下使丙烷以氫氣進行稀釋所形成的氣體環 境（對氫而言丙烷爲0.5體積％)中保持15秒鐘，使表面單結 晶矽層全層變換成SiC層。所得的單結晶SiC層之厚度爲 7nm 〇 (3) 在SiC層上形成ZnO緩衝層 使上述改性後之基板置於CVD裝置中，以二乙基鋅 (lcc/分鐘）作爲Zn源，且以氧氣（l〇cc/分鐘）作爲氧源，以 基板溫度500°C、氣壓O.lPa進行處理5分鐘，且在單結晶 SiC表面上使厚度約0.3 // m之ZnO膜成長。 (4) 煅燒處理 其次’在燈型加熱處理爐中使基板在650°C下進行加 熱，以1氣壓、lOOOOcc/分鐘之氧氣供應量下進行緞燒處理 1分鐘。 (5) 在_Zn〇緩衝層上形成厚膜Zn〇層 繼續上述（3)之以二乙基鋅（l〇CC/分鐘）作爲Zll源，且 -22- ,200844276 以氧氣（lOOcc/分鐘）作爲氧源，以基板溫度600°C、氣壓IPa 進行處理240分鐘，且在Zn〇緩衝層上使厚度約200 /z m 之ZnO單結晶層成長。藉此可得轉位殘缺密度爲ixi〇7/cm2 之Zn〇卓結晶基板。 有關以上述（3)所形成的ZnO緩衝層（試料ZnO-1)、經 由上述（4)之锻燒處理之緩衝層（試料Zn0-2)、及上述（5)之 厚膜ZnO層的形成步驟中使層厚成長至約4 // m之階段的 $ Zn〇層（試料ZnO-3)，各藉由X光繞射測定結晶性。結果如 第3圖所示。於圖中，縱軸係表示半値寬度。由圖可知， 緩衝層形成後，藉由煅燒處理使結晶性迅速提高，然後藉 由ZnO之積層處理更爲提高結晶性予以進行。而且，第4 圖及第5圖係爲各表示試料Zn0-1及ZnO-3之截面的圖面 代用照片。藉由此等圖，可確認於緩衝層煅燒後，藉由進 行ZnO單結晶之積層處理，可形成均質且平坦的ZnO層。 (6)矽層等之除去 φ 有關藉由上述所得的ZnO單結晶基板（Zn〇/SiC/By removing the opaque inner side of the germanium crystal layer 3 (base layer: thickness generally related to the diameter of the wafer used, 200 to 800 # m), a single crystal Zn〇 substrate transparent to light can be obtained ( Zn〇/SiC/ Si〇2) (refer to Fig. 2(h)). The removal of the ruthenium crystal layer 3 can be carried out using an aqueous solution of K0H, for example, preferably from 5 to 50% by weight, more preferably from 20% by weight, in an aqueous solution of K0H 19-200844276 at 60 to 95 ° C (preferably The impregnation was carried out at 80 ° C. For a SOI substrate with a diameter of 8 矽 (矽 layer thickness: about 800 // m), when a 20% by weight aqueous solution of K0H (80 ° C) is used, the immersion time of the substrate is about 800 minutes (uranium engraving speed: about 1) // m/min). Further, honing (e.g., chemical mechanical honing) may be carried out by treatment with an aqueous solution of K0H in advance, or the ruthenium layer may be honed to a thickness of, for example, about 100 V m. [Removal of SiCh insulating layer] | In addition to the germanium crystal layer, the Si〇2 insulating layer 2 may be additionally removed. Since the inside of the single crystal ZnO substrate obtained by removing the SiCh insulating layer 2 is a SiC surface (Fig. 2(i)), conductivity is formed, and the electrodes can be directly bonded to the inside. The method of removing the si〇2 layer is the same as the above method for removing the SiCh sacrificial layer. The thickness of the Si 2 insulating layer in the commercially available SOI substrate is about 150 nm, and it can be removed in about 15 minutes when immersed in 10% fluoric acid. [Removal of SiC Layer] The SiC layer 5 may be separately removed as needed, whereby a substrate formed of only φ crystalline ZnO can be obtained (see Fig. 2(j)). The removal of the SiC layer 5 can be performed, for example, by a dry etching process. The dry uranium engraving treatment supplies the CF4 gas to the SiC layer 5 only in a supply of 0.1 to 100 cc / min (e.g., i 〇 cc / min) in a vacuum, and is subjected to an arc discharge treatment by a parallel plate. At this time, the vacuum chamber of the reaction chamber may be 10 to 100 PaPa, preferably about 100 Pa. Moreover, the dry etching process can be replaced by honing (e.g., chemical mechanical honing) to remove the SiC layer. [Partial removal of single crystal ZnO layer] Further, it is also possible to remove only the single crystal Zn〇 layer 6, which has a thickness of -20-.200844276 side. The removed thickness is based on the portion containing the original buffer layer 6 and is within 1 〇 m. It is also possible to remove more than 1 〇 #m, but by removing it within 10 // m, it is possible to present a sufficiently high-quality inner side, so that it is not necessary to further remove it to be larger than the range and there is no benefit at all. The removal of the inner side of the single crystal ZnO layer 6' can be carried out, for example, by chemical mechanical honing. [Formation of Reflective Layer and Electrode Layer] A reflective layer may be formed on at least the inside of the single crystal Zn? substrate after removing the opaque layer (矽 crystal layer 3). The reflective layer forms a material, preferably a metal, preferably an alloy of the name, silver or the like. For the formation of the reflective layer made of a metal, for example, a sputtering method can be used. Since this method is a conventional method known to those skilled in the art, the operating conditions and the like can be appropriately set. When the metal layer is formed by removing at least the inside of the Si 2 insulating layer 2, when the metal layer is a reflective layer, it can be used as an electrode layer. Further, since the soldering can be performed on the surface of the metal layer formed of aluminum, silver or the like, a metal layer more suitable for the object can be additionally formed. Typical examples of such metals are copper, nickel or alloys thereof. At the same time, it is possible to allow the metal other than the metal to be soldered to form a weldable metal layer, and the sputtering treatment can be used, for example, in the same manner as the formation of the reflective layer. EXAMPLES Hereinafter, the present invention will be specifically described with reference to examples, but the present invention is not limited by the examples. (1) The formation and removal of the oxide film on the surface layer of the SOI substrate are performed using a commercially available SOI substrate [UNIB0ND (registered trademark), Shin-Etsu Semiconductors-21-200844276 body (strand), diameter 200 nm, surface single crystal layer thickness 45nm]. This was placed in an electric furnace, and heated at 1000 ° C to circulate the gas of 〇 2 gas at a pressure of 100 cc / min for 180 minutes at 1 atmosphere. The SOI substrate was taken out from the electric furnace, and immersed in an aqueous HF solution (5% by weight) at room temperature for 10 minutes. The substrate is washed and dried by ultra-pure water by a usual method. The thickness of the single crystal germanium layer on the Si 2 insulating layer was 5 nm (measured by spectroscopic ellipsometry). (2) Surface Si layer is modified into SiC layer. The gas environment formed by diluting propane with hydrogen at 1350 °C by placing the SOI substrate subjected to the above treatment in a lamp heating type treatment furnace (hydrogen pair) In the case of propane (0.5 volume%), it was kept for 15 seconds, and the surface single crystal ruthenium layer was completely converted into a SiC layer. The thickness of the obtained single crystal SiC layer is 7 nm. (3) A ZnO buffer layer is formed on the SiC layer, and the modified substrate is placed in a CVD apparatus with diethylzinc (lcc/min) as a Zn source, and Oxygen (10 cc/min) was used as an oxygen source, and the substrate temperature was 500 ° C and the gas pressure of 0.1 Pa to be treated for 5 minutes, and a ZnO film having a thickness of about 0.3 // m was grown on the surface of the single crystal SiC. (4) Calcination treatment Next, the substrate was heated at 650 ° C in a lamp type heat treatment furnace, and satin-fired for 1 minute at an oxygen supply of 1 atm and 100 cc / minute. (5) Forming a thick film Zn layer on the _Zn buffer layer, continuing the above (3) with diethylzinc (l〇CC/min) as the Zll source, and -22-, 200844276 with oxygen (100 cc/min) As an oxygen source, the substrate was treated at a substrate temperature of 600 ° C and a gas pressure of IPa for 240 minutes, and a ZnO single crystal layer having a thickness of about 200 /zm was grown on the Zn buffer layer. Thereby, a Zn〇zhuo crystal substrate having a transposed residual density of ixi 〇7/cm 2 can be obtained. The formation of the ZnO buffer layer (sample ZnO-1) formed by the above (3), the buffer layer (sample Zn0-2) subjected to the calcination treatment of the above (4), and the thick film ZnO layer of the above (5) In the step, a layer of Zn 〇 (sample ZnO-3) having a layer thickness of about 4 // m was grown, and the crystallinity was measured by X-ray diffraction. The result is shown in Figure 3. In the figure, the vertical axis represents the width of the half turn. As can be seen from the figure, after the formation of the buffer layer, the crystallinity is rapidly increased by the calcination treatment, and then the crystallinity is further improved by the lamination treatment of ZnO. Further, Fig. 4 and Fig. 5 are photographs of the drawings showing the cross sections of the samples Zn0-1 and ZnO-3. From this graph, it was confirmed that a uniform and flat ZnO layer can be formed by laminating the ZnO single crystal after the buffer layer is fired. (6) Removal of ruthenium layer, etc. φ About ZnO single crystal substrate obtained by the above (Zn〇/SiC/
Si〇2/Si)，以下述方法視其所需除去Si層、Si層及Si〇2層、 自Si層至SiC層、或進一步至部分ZnO層。 (a) Si層之除去：使上述ZnO卓結晶基板在80°C下浸漬於 20重量％之K0H水溶液中（蝕刻速度約爲1 μ m/分鐘）。另 外，使S i層藉由化學機械硏磨予以除去作爲取代。 (b) Si〇2層絕緣層之除去：使Si層除去後之單結晶ZnO 基板在室溫下浸漬於1〇重量％之HF水溶液中（除去速度約 1 0 n m /分鐘）。另外，使s i 0 2絕緣層藉由化學機械硏磨予以 -23- 200844276 除去、或倂用兩方法作爲取代。 (c) SiC層之除去：SiC層係指藉由乾式飩刻處理，使CF4 氣體僅以10cc/分鐘導入真空中（例如1〇〇Pa)，藉由平行平 板進行電弧放電處理。另外，藉由化學機械硏磨以除去SiC 層、或倂用兩方法作爲取代。 (d) 使ZnO層之裏側面僅約爲8 # m厚度下、藉由化學機 械硏磨予以除去。 【產業上之利用價値】 藉由本發明’可製造轉位缺陷密度極低的單結晶Zn〇 基板。另外’可製造全層爲光透過性之單結晶Zn0基板、 或裏面具備反射層及/或電極層、轉位殘缺密度極低的單結 晶ZnO基板。此外，可製造極爲低價且大口徑、且轉位殘 缺密度極低的單結晶ZnO基板。 【圖式簡單說明】 第1圖係表不由S ΟI基板所成的Ζ η〇基板的製造方法 之槪念圖。 第2圖係表示除去裏面側層之ZnO基板的製造方法之 槪念圖。 第3圖係表示試料ΖηΟ·1、ZnO-2及ZnO-3之X光繞射 測定結果圖。 第4圖係表示試料ZnO-Ι之截面的圖面代用照片。 第5圖係表示試料ZnO-3之截面的圖面代用照片。 【主要元件符號說明】 1，1 ’ 單結晶矽層 -24- 200844276 2 S i Ο 2絕緣層 3 矽結晶層 4 Si〇2犧牲層 5 單結晶SiC層 6,6’，6” 單結晶ZnO層Si〇2/Si), the Si layer, the Si layer and the Si〇2 layer, the Si layer to the SiC layer, or further to the partial ZnO layer are removed as needed in the following manner. (a) Removal of Si layer: The above ZnO crystal substrate was immersed in a 20 wt% aqueous solution of KOH at 80 °C (etching rate was about 1 μm/min). Further, the Si layer is removed by chemical mechanical honing as a substitute. (b) Removal of Si 2 insulating layer: The single crystal ZnO substrate obtained by removing the Si layer was immersed in a 1 wt% aqueous HF solution at room temperature (removal rate was about 10 n /min). Further, the s i 0 2 insulating layer is removed by chemical mechanical honing -23-200844276, or by two methods. (c) Removal of SiC layer: The SiC layer means that CF4 gas is introduced into a vacuum (e.g., 1 〇〇Pa) at 10 cc/min by dry etching, and arc discharge treatment is performed by a parallel plate. In addition, the SiC layer is removed by chemical mechanical honing, or the two methods are used as a substitute. (d) The inner side of the ZnO layer is removed by chemical mechanical honing at a thickness of only about 8 m. [Industrial Utilization Price] By the present invention, a single crystal Zn? substrate having an extremely low index defect density can be produced. Further, it is possible to manufacture a single crystal Zn0 substrate having a light transmittance in all layers, or a single crystal ZnO substrate having a reflective layer and/or an electrode layer therein and having an extremely low indexing defect density. Further, it is possible to manufacture a single crystal ZnO substrate which is extremely inexpensive and has a large diameter and an extremely low translocation density. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view showing a method of manufacturing a 〇 〇 substrate which is not formed of a S Ο I substrate. Fig. 2 is a view showing a method of manufacturing a ZnO substrate from which the inner layer is removed. Fig. 3 is a graph showing the results of X-ray diffraction measurement of the samples ΖηΟ·1, ZnO-2 and ZnO-3. Fig. 4 is a photograph showing a substitute of the cross section of the sample ZnO-Ι. Fig. 5 is a photograph showing a substitute of the cross section of the sample ZnO-3. [Description of main component symbols] 1,1 'Single crystal germanium layer-24- 200844276 2 S i Ο 2 insulating layer 3 germanium crystal layer 4 Si〇2 sacrificial layer 5 single crystal SiC layer 6,6',6" single crystal ZnO Floor
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