200841814 九、發明說明· 【發明所屬之技術領域】 本發明有關一種降低時脈訊號電磁干擾方法，尤其是 關於ic半導體晶片中降低時脈訊號所產生電磁干擾的方 【先前技術】 隨著數位科技的發達，數位系統為了能夠支援高密度 及高速度的資訊傳輸，需要一可靠及精確的時脈產生器以 產生高頻的時脈訊號，作為資料訊號傳輸速率的參考。典 型系統計時時脈的產生與分配，係由一系列功能元件所組 成’這一系列功能元件可為元件晶片組或獨立封裝高度整 合元件等1C半導體晶片，而該等1C半導體晶片對於電·磁 干擾（Electrical Magnetic Interference，簡稱 EMI)十 分敏感。 _ 由於時脈產生器所產生高頻時脈訊號，經常對時脈產 生器或數位系，内的IC半導體晶片，造成電磁干擾，影響 系統的可靠度及性能。為了降低高頻時脈訊號所產生 能量，以避免電磁干擾，本國第〇9112〇699號「降低電磁 干擾之鎖相回路」專利申請案，利用降低電磁干擾之鎖相 控制具有相位差之―些訊號，其為η倍於電壓控制震 盥器的輸出訊號之基本延遲時間，決定調變率，以降低電 Ϊ干ΐ二巧第_7404號「界面電路及液晶驅動電 案，則提出利用遽波電路及複數個比較電路 對數位訊號^行位準變換，以減低電磁干擾。 降低先前技術均需增加額外的線路，才能達到 件製、效果，不僅降低元件佈局空間，且增加元 上：有問題轉因此，習知時脈訊號在降低電磁干擾 200841814 【發明内容】 、^發明之一目的在提供一種降低時脈訊號電磁干擾方 法’藉由將時脈訊號函數轉換為單位函數，降低時脈所產 生的能量，以減少電磁干擾。 、 本發明另一目的在提供一種降低時脈訊號電磁干擾方 法，利用至少一單位函數之運算產生一個有效的頻率，以 提供適當的時脈訊號。 、本發再一目的在提供一種降低時脈訊號電磁干擾方 _ 法，利用邏輯運算方式產生低能量的時脈訊號，降低電磁 干擾及產品成本。 ^了達到前述發明的目的，本發明之降低時脈訊號電 ίΤ擾ί法，首先由-時脈產生器產生—時脈訊號，擷取 訊遽，形成一時脈函數，再將時脈函數進行拉氏轉換 成接著以至少—單位函數之運算，賴有效時脈 土农後輸自有效時脈訊號，作為數m傳輸資料訊號的計 時參考。 【實施方式】 有關本發明為達成上述目的’所採用之技術手段及其 β功效，茲舉較佳實施例，並配合圖式加以說明如下。 請參考圖1 ’為一時脈產生器所產生脈衝的時脈訊號， 該時脈訊號的能量較大，如未加處理，將 元件產生電磁干擾。為降低時脈訊號的能量 號時，f先將時脈訊號形成一時脈函數並定義該時腯 函數<5 (t)為： 〇〇 ⑴ 6 200841814 其中，t為時間。 再將前述（1)式之時脈函數5 (t)，利用拉氏轉換 (Laplace Transform)進行轉換，轉換的運算如下：200841814 IX. The invention relates to a method for reducing electromagnetic interference of a clock signal, in particular to a method for reducing electromagnetic interference generated by a clock signal in an ic semiconductor chip. [Prior Art] With Digital Technology In order to support high-density and high-speed information transmission, digital systems require a reliable and accurate clock generator to generate high-frequency clock signals as a reference for data signal transmission rate. The generation and distribution of typical system timing clocks is made up of a series of functional components. This series of functional components can be 1C semiconductor wafers such as component chipsets or individually packaged highly integrated components, and these 1C semiconductor wafers are for electrical and magnetic Electrical Magnetic Interference (EMI) is very sensitive. _ Due to the high-frequency clock signal generated by the clock generator, electromagnetic interference is often caused to the IC semiconductor chip in the clock generator or digital system, which affects the reliability and performance of the system. In order to reduce the energy generated by the high-frequency clock signal to avoid electromagnetic interference, the national patent application No. 9112〇699 “Reducing the phase-locked loop of electromagnetic interference” uses the phase-locking control to reduce the electromagnetic interference to have a phase difference. The signal, which is η times the basic delay time of the output signal of the voltage control oscillator, determines the modulation rate, and reduces the use of the interface circuit and the liquid crystal drive circuit. The wave circuit and the plurality of comparison circuits perform digital signal level conversion to reduce electromagnetic interference. Lowering the prior art requires adding additional lines to achieve the component system and effect, not only reducing the component layout space, but also increasing the number of elements: Therefore, the conventional clock signal is reducing electromagnetic interference. 200841814 [Invention] The purpose of the invention is to provide a method for reducing the electromagnetic interference of the clock signal by reducing the clock by converting the clock signal function into a unit function. The generated energy to reduce electromagnetic interference. Another object of the present invention is to provide a method for reducing electromagnetic interference of a clock signal, An effective frequency is generated by the operation of at least one unit function to provide an appropriate clock signal. Further, the present invention provides a method for reducing the electromagnetic interference of the clock signal, and using a logic operation to generate a low-energy clock. Signal, reducing electromagnetic interference and product cost. ^ For the purpose of the foregoing invention, the reduced clock signal of the present invention is first generated by a clock generator, and the signal is generated to form a moment. The pulse function converts the clock function into Lagrangian and then calculates the operation by at least the unit function. The effective clock is transmitted from the effective clock signal as a timing reference for transmitting the data signal by several millimeters. For the technical means and the β-efficiency of the present invention for achieving the above object, the preferred embodiment will be described below with reference to the following figures. Please refer to FIG. 1 for the pulse signal of the pulse generated by a clock generator. The energy of the clock signal is large, and if it is not processed, the component generates electromagnetic interference. In order to reduce the energy number of the clock signal, f firstly signals the clock signal. Forming a clock function and defining the time 腯 function <5 (t) is: 〇〇(1) 6 200841814 where t is time. Then the clock function 5 (t) of the above formula (1) is transformed by Laplace Laplace Transform) performs the conversion, and the conversion operation is as follows:
ε-^Q L{S(t)}=： 啦:灿dt ε lim —「{w(/) — w(/ — £〇}汾 ε-^Q β J〇 lim — {L{u(t)} - L{u(t - ε)} } s Φ lim £*->0 -一 -Qs sc -65 1 v l-e^s 0 —lim-λ — S s 0 lim se •s S 1 (2) 其中，S為S域（domain)函數； s為很小的時間， u(t)為單位函數。 由（2)式的轉換，將時脈函數5(t)轉換為一單位函數 u(t)，並定義單位函數u(t)為： 广 1 t = 0 n(t)E < (3)Ε-^QL{S(t)}=: 啦:candt ε lim —“{w(/) — w(/ – £〇}汾ε-^Q β J〇lim — {L{u(t) } - L{u(t - ε)} } s Φ lim £*->0 -1 - Qs sc -65 1 v le^s 0 —lim-λ — S s 0 lim se •s S 1 (2 Where S is the S domain function; s is a small time, u(t) is a unit function. By the transformation of (2), the clock function 5(t) is converted into a unit function u ( t), and define the unit function u(t) as: wide 1 t = 0 n(t)E < (3)
其中，t為時間。 如圖2所示，時脈函數5 (t)即可轉換為單位函數u(t)。 200841814 =)5有對應料位函數u⑴，讓時脈訊號脈衝 擾的能量，度使時脈訊號產生電磁干 呼主取低，達到減少電磁干擾的目的。 單位函數的m時脈喊所需之縣，可*二或多個的 -，15 -山產生一合適單位函數作為時脈訊號。如圖3所 :二個單位函數之差所形成時脈訊號’其中單位函數 必-1)及早似數u(t_2)的㈣絲為： “歎 u(t-l) ⑷ t <Where t is time. As shown in Figure 2, the clock function 5 (t) can be converted to the unit function u(t). 200841814 =)5 has the corresponding material level function u(1), so that the energy of the pulse signal of the clock signal causes the clock signal to generate electromagnetic dry call to take the low to achieve the purpose of reducing electromagnetic interference. The m-clock of the unit function calls the desired county, and can be *two or more -, 15- mountain produces a suitable unit function as the clock signal. As shown in Figure 3: the difference between the two unit functions is formed by the clock signal 'where the unit function is -1) and the early number u(t_2) is the fourth wire: "sigh u(t-l) (4) t <
(5) r u(t-2) Ξ(5) r u(t-2) Ξ
f中，t為時間。由式（4)單位函數乂卜丨）減式（5) m 位函數u(t—2)，即可經由簡單的運算產生式（3)的單位 u(t)，以作為時脈訊號。 裝 於酱ί圖4所示，為本發明降低時脈訊號電磁干擾方法之 二机程，該流程具體顯示本發明降低時脈訊號電磁干 之步驟，詳細步驟說明如下： 欠 g π S1 :由一時脈產生器產生時脈訊號，作為數位系 、、充傳輸資料訊號的計時參考。 /、 步驟S2 :擷取時脈產生器所產生之時脈訊號’形成— 時脈函數d(t)。 步驟S3 :將時脈函數d (t)進行拉氏轉換運算。 ⑴。步驟S4:時脈函數(5 (t)進行拉氏轉換後，形成單位函數^ 200841814 % -In f, t is time. By the equation (4) unit function 丨 丨 减) minus the (5) m-bit function u(t - 2), the unit u(t) of the equation (3) can be generated as a clock signal by a simple operation. FIG. 4 is a second process for reducing the electromagnetic interference of the clock signal according to the present invention. The flow specifically shows the steps of reducing the electromagnetic pulse of the clock signal according to the present invention. The detailed steps are as follows: gg π S1 : The clock generator generates a clock signal as a timing reference for the digital system and the data signal to be transmitted. /, Step S2: The clock signal generated by the clock generator is formed to form a clock function d(t). Step S3: Perform a Lagrangian conversion operation on the clock function d (t). (1). Step S4: The clock function (5 (t) after the Lagrangian transformation, forming a unit function ^ 200841814 % -
步驟S5 · & $ I · 時脈訊號。.至父―單位函數，形成有效的單位函數，作為 傳輪之計時表考，有放的¥脈訊號輸出，作為數位系統資料訊號 即可步驟，本發明降低時脈訊號電磁干擾方法， 少〜級之。^^脈訊號之函數轉換為單位函數，同時利用至 率，作里=位函數之簡單運算產生一個合適的單位函數頻 少電"、蚪脈訊號頻率，使時脈所產生的能量降低，以減 . 係以〉干擾。此外，本發明之降低時脈訊號電磁干擾方法， _ 可以函數的轉換及邏輯運算方式產生低能量的時脈訊號， 電磁軔體方式完成，無需額外增加線路及零件，除可降低 包嗞干擾，亦可降低產品的製造成本。 ·一 本以上所述者，僅用以方便說明本發明之較佳實施例， ^之範圍不限於該等較佳實施例，凡依本發明所做的 ;可變更，於不脫離本發明之精神下，皆屬本發明申請專 利之範圍。 9 200841814 , 【圖式簡單說明】 " 圖1為一時脈產生器所產生脈衝的時脈訊號。 、 圖2為本發明將時脈函數轉換為單位函數訊號。 圖3為本發明由二組單位函數之差所形成時脈訊號。 圖4為本發明降低時脈訊號電磁干擾方法之流程圖。 【主要元件符號說明】 S1產生時脈訊號步驟 S2擷取時脈訊號步驟 Φ S3拉氏轉換運算步驟 S4轉換單位函數步驟 S5形成有效時脈訊號步驟 S6輸出時脈訊號步雜Step S5 · & $ I · Clock signal. To the father-unit function, form a valid unit function, as a chronograph test of the transfer wheel, there is a pulse signal output, which can be used as a digital system data signal. The present invention reduces the electromagnetic interference method of the clock signal, less~ Level. ^^ The function of the pulse signal is converted into a unit function, and the simple operation of the ==bit function is used to generate a suitable unit function, which is less frequent, and the frequency of the pulse signal is reduced, so that the energy generated by the clock is reduced. To reduce. In addition, the method for reducing the electromagnetic interference of the clock signal of the present invention, _ can be converted by a function and logically operated to generate a low-energy clock signal, and the electromagnetic body is completed without additional lines and parts, in addition to reducing the interference of the package. It can also reduce the manufacturing cost of the product. The above description is only for the convenience of the description of the preferred embodiments of the present invention, and the scope of the present invention is not limited to the preferred embodiments, and may be modified according to the present invention without departing from the invention. In the spirit, it is within the scope of the patent application of the present invention. 9 200841814 , [Simple diagram of the diagram] " Figure 1 is the pulse signal of the pulse generated by a clock generator. 2 is a diagram of the present invention for converting a clock function into a unit function signal. 3 is a clock signal formed by the difference between two sets of unit functions in the present invention. 4 is a flow chart of a method for reducing electromagnetic interference of a clock signal according to the present invention. [Main component symbol description] S1 generates clock signal step S2 captures clock signal step Φ S3 Laplace conversion operation step S4 converts unit function step S5 forms effective clock signal step S6 outputs clock signal step