200841321 九、發明說明： ^ 【發明所屬之技術領域】 * 本發明係有關於—種影像敏之電路及方法，_是指-種影像調整 電路及其内插電路與内插方法。 【先前技術】 隨著數位顯示器之技術快速發展，數位顯示器之畫質已大幅提升，而 漸漸取代傳統顯不器。現今的數位顯示器，如液晶顯示器、電裝顯示器等， 其4f的好壞取祕影像的騎度。數位齡ϋ的畫Φ是由許？光點所構 成的，這些光點稱為像素（pixel)。而數位顯示器之解析度代表的就是這 些像素的數量。例如··-般常說顯示器的解析度為腦χ768，意味著領示 : 器於顯示畫面時，畫面具有漏條垂直線，每一條垂直線具有腦點水平 像素，所以顯示器所顯示之畫面的總像素數即為漏條垂直線與醜點水 平像素的乘積。 數位顯示衫瞒，㈣傳敏紐顯㈣讀人影像的解析 度兩相今於數位顯示器顯示影像之解析度，所以數位顯示器大都會放大或 縮顿接收狀輸人册，也歧調整輸福像之解析度，⑽合目前數 • 位顯不器顯示影像之解析度。數位顯示器於調整影像時，必須利用内插方 式，以放大或是縮小輸入影像。 請參哪-圖，其為習知影像放大的調整示意圖；如圖所示，假設輸 人影像A所包含的像素點駿為4點’ t輸入影像A進行放大峨產生包 含有8像素點之輸出影像B時’則需要_ _方式產生新像素點而產生 輸出雜B。產錄像素·畴，必就計算出新像素狀位置，之後再後據 輸入影像A之原像素點之值糊_法求出新像點之值。f知技術之内 插方式，係以虛擬點或是虛擬距離參數進行内插，以產生所需的内插點。 習知技術上财式產生這些_點’實際上需魏外的硬體計算電路 進行計算，因而增加數郷像顯示H的製作成本，且影響調㈣像之效率。 200841321200841321 IX. Description of the invention: ^ [Technical field to which the invention pertains] * The present invention relates to a circuit and method for image sensitivity, and _ refers to an image adjustment circuit, an interpolation circuit thereof and an interpolation method. [Prior Art] With the rapid development of digital display technology, the quality of digital displays has been greatly improved, and gradually replaced the traditional display. Today's digital display, such as liquid crystal display, electric display, etc., its 4f is good or bad to capture the image of the secret. How many digital paintings Φ are made by Xu? The spots formed by the spots are called pixels. The resolution of a digital display represents the number of these pixels. For example, it is common to say that the resolution of the display is χ 768, which means that when the display screen is displayed, the screen has a vertical line of leaks, and each vertical line has horizontal pixels of the brain point, so the screen displayed by the display The total number of pixels is the product of the vertical line of the missing bar and the horizontal pixel of the ugly point. Digital display shirt, (4) Transmitting New Zealand (4) Resolution of reading images Two phases of digital display display resolution of the image, so the digital display will magnify or shrink the receiving input book, and adjust the image The resolution, (10) and the current number • The display shows the resolution of the image. When the digital display is adjusted, you must use the interpolation method to enlarge or reduce the input image. Please refer to the figure, which is a schematic diagram of the adjustment of the conventional image enlargement; as shown in the figure, it is assumed that the input image A contains a pixel point of 4 points. The input image A is enlarged and generated to include 8 pixels. When outputting image B, 'the __ method is required to generate a new pixel and produce an output B. When a pixel/domain is produced, a new pixel-like position is calculated, and then the value of the new pixel is obtained by the value of the original pixel of the input image A. The interpolation method is interpolated by virtual point or virtual distance parameters to generate the required interpolation points. The conventional technique of generating these _points actually requires the calculation of the hardware calculation circuit of Wei, thus increasing the production cost of the digital image display H and affecting the efficiency of the image. 200841321
【發明内容】 本發月之目的在於提供—種影像調整電路及其膽電路及方法， 由提供内插對照值，而依據内插對照值對輸人影像進行内插運算而產= 出々像如此可使數位顯不器不需額外的硬體計算電路即可決定内插點位SUMMARY OF THE INVENTION The purpose of this month is to provide an image adjustment circuit and a biliary circuit and method thereof. By providing an interpolation control value, an interpolation operation is performed on the input image according to the interpolation control value. This allows the digital display to determine the interpolation point without additional hardware calculation circuitry.
^不但減少數位影像顯示器的製造成本，更提昇調整影像的速率，進而 提昇數位顯示器之效能。 本發明之影像調整電路包含―垂直内插電路與—水平喃電路，兩内 插電路皆包含複數資料移位循環電路、—控制器、—選擇單摘一運算電 路，每-資料移位循環電路皆儲存有複數資料旗標，#該些資料移位循環 電路之又控制器驅動時，則會依序循環輸出該些資料旗標；控制器依據 -輸入影像之-原始解析度與一目標顯示器解析度而發出相對應之一選擇 訊號與-鶴職，鶴峨胁轉該缝料雜觀電路之一，而選 擇訊號則發送至娜單* ,以供選料元依據選擇訊號對應輸出 -内插對 照值，内姆照鶴受轉之簡移賴職路姆應；運算電路依序依 據資料旗標並對翻插_值，_輸人影絲彻插運算，而產生對應 目標顯示器解析度之一輸出影像。 本發明之影像調魏路之嶋紐主要包括n輸人影像之一原 始解析度與-目標_輯析度，選擇姆應之-_對難與複數資料 旗標；以及2序依據_雜旗標麟舰浦韻值,職輸入影像 進行内插運异，產生對麟目標顯示轉析度之__難影彳卜 【實施方式】 請參閱第二圖’其為本發明之影像調整電路之方塊圖。如圖所示，影 像調整電路1G包含有-铜電路12，其用以偵測—輸人影像，以得知輸入 200841321 f彡狀H崎度並麟jL-妓嶋祕丨續—斜嘯魏16，< - 後再藉由影像調整電路H)之垂直_電路14與水平内插電路16，依據輸 、 人雜之賴崎度與_示潍之-目觀示器解析度，_輸入影像 做内插運算’以產生符合目標顯示器解析度之一輸出影像，並傳送至 示單元18以顯示影像。 ° 垂直内插電路14钱依據輸人影像之賴解析度的垂直解析度盘目样 顯示器解析度之垂直解析度對輸入影像之垂直晝素資料進行内插運算而^ 生新畫素資料。之後’錄嶋· 14會減晝素諸傳輸至水平内插電 路16讓水平内插電路16依據目標顯示器解析度之水平解析度對新畫素 參料之水平畫素資料進行内插運算，而產生符合目標顯示器解析度之輸出影 像。 由於現今-般所使用之影像解析度大都為特定幾種解析度，例如水平 解析度為640、720、800、1024、1152、1280與1440等，而垂直解析产為 、、480、600、768、864、與腦等，所以本發明係依據^幾 種解析度㈣先建立複數喃對雌，以健直内插電路14與水平内插電 路16對照相對應之内插對照值進行内插運算，如此只需對照内插對,昭值即 可得=插點^位置而不需再另外計算，故可解決習用技術所遭遇的問題。 請參閱第三圖，其為本發明之一較佳實施例之内插對照值。以下係以 罾調整原始水平解析度為麵之影像為侧作為例子，而對本發明進行詳 盡說明。如圖所示，此内插對照值為原财平解析度為腦而欲調整為簡 之内插值。本㈣之_對難包含有—原雜資訊、—嶋點健 資訊、-預測點資訊、-取樣點資訊、一資料旗標資訊、一輸出點資訊以 及一運算點資訊。 、 本發明之内插對照值是藉由第—比例因子與第二比例因子所建立成。 原始解析度與第-關因子之乘積料於目標顯示器解析度與第二比例因 子之乘積。第-_因子與第二比姻子分職内插對照值中之内插點個 數資訊與取樣關隔資訊（圖未示）。第三圖之喃韻值之第―比例因子 200841321^ Not only reduces the manufacturing cost of digital image displays, but also increases the rate of image adjustment, thereby improving the performance of digital displays. The image adjustment circuit of the invention comprises a vertical interpolation circuit and a horizontal circuit, and both interpolation circuits comprise a plurality of data shift cycle circuits, a controller, a selection single operation circuit, and a data shift cycle circuit. All of them store a plurality of data flags. When the controllers of the data shifting loop circuit are driven by the controller, the data flags are sequentially outputted in sequence; the controller is based on the input image - the original resolution and a target display The resolution is sent to correspond to one of the selection signals and the crane, and the crane signal is transferred to one of the sewing circuit, and the selection signal is sent to the Nadan* for the selection of the material according to the selection signal. Incorporate the control value, and the internal circuit is replaced by the simple shift of the job. The arithmetic circuit is based on the data flag and interpolates the _ value, _ input shadow, and generates the corresponding target display resolution. An output image. The image of the invention is mainly composed of one of the original input resolutions of the n-input images and the target-degree analysis degree, and the selection of the M-Yi---the difficulty and the plural data flag; and the 2 order basis_the flag According to the Pu Yun value of the standard ship, the input image is interpolated and transferred, and the conversion degree of the display of the target is generated. _ _ 难 【 【 [Implementation] Please refer to the second figure, which is the image adjustment circuit of the present invention. Block diagram. As shown in the figure, the image adjusting circuit 1G includes a copper circuit 12 for detecting and inputting an image to know the input 200841321 f-shaped H-salience and Lin jL-妓嶋秘丨- 16, < - then by the image adjustment circuit H) vertical_circuit 14 and horizontal interpolation circuit 16, according to the input, the human ambiguity and the _ 潍 潍 目 目 解析 解析 解析 , , The image is interpolated to generate an output image that conforms to one of the resolutions of the target display and is transmitted to the display unit 18 to display the image. ° Vertical interpolation circuit 14 The vertical resolution of the input image depends on the vertical resolution of the display resolution. The vertical resolution of the input image is interpolated to generate new pixel data. After that, the recording and subtraction of the elements into the horizontal interpolation circuit 16 causes the horizontal interpolation circuit 16 to interpolate the horizontal pixel data of the new pixel reference according to the horizontal resolution of the target display resolution. Produces an output image that matches the resolution of the target display. Since the image resolution used today is mostly a certain degree of resolution, for example, the horizontal resolution is 640, 720, 800, 1024, 1152, 1280, and 1440, and the vertical resolution is 480, 600, 768. 864, and the brain, etc., the present invention is based on a plurality of resolutions (4) to first establish a complex number of females, and the interpolation process is performed by the vertical interpolation circuit 14 and the horizontal interpolation circuit 16 in accordance with the corresponding interpolation values. In this way, it is only necessary to compare the interpolation pair, and the value can be obtained = the position of the interpolation point without additional calculation, so that the problems encountered in the conventional technology can be solved. Please refer to the third figure, which is an interpolation control value according to a preferred embodiment of the present invention. Hereinafter, the present invention will be described in detail by taking the image in which the original horizontal resolution is adjusted as the side. As shown in the figure, this interpolated control value is the interpolated value that the original financial resolution is the brain and is intended to be adjusted to be simple. The _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The interpolation control value of the present invention is established by the first scale factor and the second scale factor. The product of the original resolution and the first-off factor is the product of the target display resolution and the second proportional factor. The number of interpolated points in the first-_factor and the second-in-law sub-interpolation control value and the sampling interval information (not shown). The third figure is the first value of the rhyme value - scale factor 200841321
與第二比例因子分別為10與8，也就是1〇24X1()等於128〇χ8。所謂内振點 個數資訊就是輸入影像之每資料必須調整之數量。以第三圖之内插對照值 為例，每原始水平像素點必須調整擴大為10點像素點。 上述所謂取樣間隔資訊為取樣前述調整後之像素點的間隔數；以第三 圖之內插對照值為例，由於喃闕隔冑訊為8，也戯^每_ 8則取樣一 點。如第三圖之内插對照值之取樣點資訊與輸出點資訊所示，第i輸出點 也就是第1個取樣點，其係取樣調整第1原始像素點後之像素點的第1點； 第2輸出點也就是第2個取樣點，其係取樣調整第i原始像素點後之像素 點的第9點’第1取樣點與第2取樣點相間隔為8，也就是為取樣間隔資訊； 第3輸出點也就是第3個取樣點，其係取樣調整第2原始像素點後之像素 點的第3點，町轉點餘鋪推。本發日狀嘯賴值的資料旗標資 訊係與輸出點資訊相對應。 ”、 由於本發明之内插對照值之第一比例因子與第二比例因子之比為整數 比，於此實施例來說也就是1〇 : 8，所以每當間隔8個内插像素點之後，即 取樣第9個像素點，而取樣之像素點對應之相關資訊係關於此第9個像素 點。此實施例於進行内插運算時，係一次跳過8個内插預測資料進行資料 循環，即一次跳過8個調整後之像素點，而依據查表内插運算得到輪出點 後再，續跳過8個内插細資料，上次最後-個資料為接續_之第i個 起始貝料，也就是會以此次所取樣的資料為接續内插之第丨個起始資料。 此外’内插對照值中之預測點資訊則用於表示取樣調整原始像素點傻 素點所剩餘的像素點。 當獲知取樣點位置後，即依據對應之運算點資訊進行内插運算，以得 知取樣點之練。糊絲，帛1個取無之卿鎌賴叙運算點f 訊（1曰)進行内插運算所得之值，由於第i個取樣點對應之運算點資訊為1， 不第1取樣點之值即為第1原始像素點之值。第2個取樣點所對 應連雜資訊為〗，2，也就是說第2個取樣點位於第1原始像素點與第2 原始像素點之間，靠第2個取獅之值必馳據第！原始像素點★、第、 200841321 原始像素點之值進;f亍内插運算而得知。 、·The second scale factor is 10 and 8, respectively, that is, 1〇24X1() is equal to 128〇χ8. The so-called internal vibration point number information is the amount that each data of the input image must be adjusted. Taking the interpolation value of the third figure as an example, each original horizontal pixel must be adjusted to be enlarged to 10 pixels. The so-called sampling interval information is the number of intervals for sampling the adjusted pixel points; taking the interpolation control value of the third figure as an example, since the 阙 阙 胄 为 为 is 8 , it is also sampled every _ 8 . As shown in the third figure, the sampling point information and the output point information of the interpolation value are shown, the ith output point is also the first sampling point, which is the first point of the pixel after the first original pixel point is sampled; The second output point is also the second sampling point, which is the 9th point of the pixel after the adjustment of the i-th original pixel point. The first sampling point is spaced apart from the second sampling point by 8, which is the sampling interval information. The third output point is also the third sampling point, which is the third point of the pixel after the second original pixel is sampled and adjusted. The data flag information system of the daily whistle-blowing value corresponds to the output point information. Because the ratio of the first scale factor to the second scale factor of the interpolation control value of the present invention is an integer ratio, in this embodiment, it is 1〇: 8, so after every 8 interpolation pixels That is, the 9th pixel is sampled, and the related information corresponding to the sampled pixel is related to the ninth pixel. This embodiment skips 8 interpolation prediction data for data loop at the time of interpolation operation. , that is, skipping 8 adjusted pixel points at a time, and then obtaining the round-out point according to the interpolation operation of the look-up table, and then skipping 8 interpolated fine materials, the last last data is the ith of the next _ The starting bead material, that is, the data sampled by this time is the first starting data of the subsequent interpolation. In addition, the prediction point information in the interpolated control value is used to indicate that the sampling adjusts the original pixel point. After the location of the sampling point is known, the interpolation operation is performed according to the corresponding operation point information, so as to know the practice of the sampling point. (1曰) the value obtained by the interpolation operation, because the ith is taken The operation point information corresponding to the sample point is 1, and the value of the first sampling point is the value of the first original pixel point. The second sampling point corresponds to the mixed information of 〖, 2, that is, the second sampling point. Between the 1st original pixel point and the 2nd original pixel point, the value of the second lion will be based on the value of the original pixel point ★, the first, the 200841321 original pixel point; the f亍 interpolation operation Know.
此外’在細缝運料，係必麵知轉輯對應之權重值，方 利用内插方程式求得取樣點之值。本發明即依據取樣 照圖，以得知相對應之-權重值，而代人_方程式進而運算得知取樣= =不同内插法所相對應之權重對照圖係不相同，一般常用之内插有 ^ ^ (Linear Interpolation) ^ ^ ^ # (Si^ γπχ> atlon)以及一立方迴旋插補法似心In addition, when the material is transported in the slit, it is necessary to know the weight value corresponding to the transfer, and the value of the sampling point is obtained by using the interpolation equation. The invention is based on the sampling picture to know the corresponding-weight value, and the generation_the equation is further calculated to learn the sampling == the weight corresponding to the different interpolation method is different from the picture system, and the commonly used interpolation There are ^ ^ (Linear Interpolation) ^ ^ ^ # (Si^ γπχ> atlon) and a cubic convolution interpolation method
Interpolation)。 明多閱第四圖，其為本發明進行内插運算所用之權重對照圖之實施例 之一。第四圖所示之權重對照圖為線性插補法所對應之權重對照圖。假咬 本發明運用線性插補法進行内插運算而得知輸出點之值。當内插運算第i 輸出點時，依據第1輸出點所對應之取樣點資訊⑴而對照權重對=圖即 可得知相對應之權重值為i;内插運算第2輸出點時，則依據第2輸出點所 對應之取樣點資訊（9)輯照權重對關即可得知祖對應之權重值為 0.11 ’同理’運算其餘輸出點時，皆可依據所對應之取樣點資訊而對照權 重對照圖表即可得知對應之權重值。 、由於本發明之内插對照值是藉由第一比例因子與第二比例因子所建立 成’而原始解析度與第—比例目子之乘積會等於目標顯㈣解析度與第二 比例因子之乘積，所財發^瞻對照值可概触。料三圖之實施 例來說於取樣帛5個取樣點後，依照腳栖資訊所^係會剩下7侧整 後之像素點，又進行6次取鱗會以第5個取樣點為接續内插之第丨個起 始像素點，所以間隔8個像素點後所取樣到之第6個取樣像素點會是第5 個原始像素點、，故第5個原始像素鱗可作為接軸插運算之第丨個原始 像素點，而依照此内插對照值接續進行内插運算。上述之内插對照值的循 環起始點會隨著麟度之不同而細不同，也就是關關因子會有不同 之循環起始點。 本發明由於預先提供複數内插對照值，所以於進行内插運算時，可立 200841321 即對照内插對照值而得知相對應的資訊，以方便内插運算輸入影像而產生 輸出影像，所以可簡化用於調整影像之調整電路，而降低計算電路的成本， ^ 並可提高調整影像之效率，且可循環對照進行内插運算。另外，由於本發 明之内插對照值中的資訊皆為整數，所以於進行内插運算時可簡化運算， 如此可不需使用複雜之運算電路即可進行内插運算，以達增進調整影像之 效率的目的。 請參閱第五圖，其為本發明之内插電路之較佳實施例的方塊圖。第五 圖所示之内插電路2G係運用於第二圖之垂直内插電路14與水平内插電路 16。如圖所示，本發明之内插電路2〇，其包含一儲存單元3〇、複數資料移 攀賴環電路40、一控制器50、一選擇單元6〇、一運算電路7〇、一時脈產 生器80與一影像線暫存器90。儲存單元3〇肖以儲存複數内插對照值，不 同之mt對難分珊應不同麟度。該些資料雜循環電路4()各儲存有 一組資料旗標，每組資料旗標皆有差異而對應於不同之内插對照值，每組 1料旗標皆包含有複數資料旗標，而對應於内插對照值的資料旗標。該些 貪料移位循環電路40之任一受控制器50驅動時，將會依序循環輸出該等 資料旗標。 " 控制器50 ’其依據目標顯示器解析度與偵測電路12所傳送之原始解析 φ 度，而分別發出相對應之一選擇訊號與一驅動訊號至選擇單元60與該些資 料雜魏電路40之-。選鮮元6G會絲麟喊卿輸_存單元 30之内插對照值至運算電路70。控制器5〇所發送之驅動訊號係用於驅動 該等資料移位循環電路4〇之一，控制器50所驅動之資料移位循環電路4〇 係對應於選擇單元60所輸出之内插對照值。時脈產生器8〇，用於產生一同 步脈波訊说並傳送至該等資料移位循環電路妨與運算電路。 承接上述，資料移位循環電路4〇會依據同步脈波訊號依序輸出資料旗 標至運异電路70,而運算電路70會依據同步脈波訊號内插運算影像線暫存 器90所暫存之輸入影像，而產生輸出影像。運算電路7〇於内插運算輸入 影像時’係依序根據資料移位循環電路4〇所輸出之資料旗標與選擇單元⑼ 200841321 輸出之内插賴值，而喃運算觀影像崎合目標顯示器解析度之影像 需求規格。舉例來說，當運算電路70接收的資料旗標為i時，即依據資料 f標為1所對應之内插對照值進行内插運算；當運算電路7〇接收的資料旗 標為2時，即依據資料旗標為2所對應之内插對照值進行内插運算。本發 明之運算電路7〇依據-、線性插補法(Linear Interp〇lati〇n)、一正弦函數 插補法(Sine Interpolation)以及一立方迴旋插補法（Cubic c〇nv〇luti()n Interpolation)之其中之一進行内插運算。 第五圖實施例之内插電路20係運用於水平内插電路16(參閱第二圖）， 所以影像線暫存器90所儲存的資料為垂直内插電路14(參閱第二圖)所傳送 之新畫素讀，破算電路Μ所產生之雜資料即傳送至齡單元，進 而顯示。運用於垂直内插電路14之内插電路2〇，其影像線暫存器9〇所暫 存的影像資料為傳it至顯示H賴示的輸人影像資料，_算電路7〇所產 生之輸峰像為垂直畫素龍，且會傳送至水平嶋電路丨㈣暫存於水平 内插電路16之影像線暫存器90。此外，垂直内插電路Η之運算電路7〇於 進仃内插運算時’係依據輸人影像之原始解析度的垂直解析度與目標顯示 器解析度義雜析錢麟對狀嶋對照值與韻旗標，而水平内插 電路1口6乂運算電路70雜據輸人影像之原始解析度的水平解析度與目標 顯示器解析度的水平解析度猶擇對應之__值與資料旗標。、、 咐多閱第/、圖，其為本發明較佳實施例之流程圖。如圖所示，根據本 發月之心像調整之内插方法，首先，如步驟s〇所示，提供複數内插對照值 與相對應之複數_料旗標，每_舰财包含有複數資料旗標，即複 數資料移位循環電路40所儲存之資料旗標；之後，偵測電路12進行步驟 S1偵。测輸入衫像而得知輸入影像之原始解析度並傳送至控制器;隨後， ，制器、5ΰ進仃步驟S2，依據輸人影像之原始解析度與目標顯示器解析度， 分別發达姆應之麵纖與鷄觸^獅科6()與鱗雜移位循環 電路40之一，以選擇相對應之内插對照值與複數資料旗標。 然後’運算電路70進行步驟S3，依序依據該些資料旗標並對照内插對 200841321 照值，而對輸入影像進行内插運算，產生符合目標顯示器解析度之輸祕 _ 像。此外，為了避免該些資料移位循環電路40輸出資料旗標之時序與運算 - 電路7㈣插運算輸人影像之時序沒有同步，所以於運算電路70進行此步 驟時，時脈產生器80會產生同步時脈訊號並傳送至該些資料移位循環電路 40與運算電路70，如此資料移位循環電路4〇即會依據同步時脈訊號依序 輸出資料旗標，運算電路70則會依據同步時脈訊號同步根據資料旗標與内 插對照值，而運算輸入影像以產生輸出影像。 綜上所述，本發明影像調整電路之内插電路及内插方法，其藉由控制 器依據目標顯示器解析度與輸入影像之原始解析度發出相對應之選擇气穿 丨· 與驅動訊號至選擇單元與複數資料移位循環電路，以選擇相對應之内插對 照值與複數資料旗標，讓運算電路依據依序輸出之資料旗標並對照内插 值，而對輸入影像進行内插運算以產生符合目標顯示器解析度之輸出影 ' 像，如此即可快速調整影像，提高調整影像之效率。 | 以上所述者，僅為本發明之較佳實施例而已，並非用來限定本發明之 範圍，舉凡依本發明申請專利範圍所述之形狀、構造、特徵及精神所為之 均等變化與修飾，均應包括於本發明之權利範圍内。 i 、 :⑩ 【圖式簡單說明】 第一圖為習知影像放大的調整示意圖。 第二圖為本發明之影像調整電路之方塊圖。 ， 第三圖為本發明較佳實施例之内插對照值。 I 第四圖為本發明較佳實施例之權重對照圖。 I 第五圖為本發明之内插電路之較佳實施例的方塊圖。 第六圖為本發明較佳實施例之流程圖。 【主要元件符號說明】 10 影像調整電路 12 200841321 12 偵測電路 14 垂直内插電路 16 水平内插電路 18 顯示單元 20 内插電路 30 儲存單元 40 資料移位循環電路 50 控制器 60 選擇單元 70 運算電路 80 時脈產生器 90 影像線暫存器Interpolation). Ming Duo explained the fourth figure, which is one of the embodiments of the weight comparison diagram used for the interpolation operation of the present invention. The weight comparison chart shown in the fourth figure is a weight comparison chart corresponding to the linear interpolation method. False bite The present invention uses a linear interpolation method to perform an interpolation operation to know the value of the output point. When the i-th output point is interpolated, the corresponding weight value is i according to the sampling point information (1) corresponding to the first output point and the weight pair = map; when the second output point is interpolated, According to the sampling point information corresponding to the second output point (9), the weight of the ancestor corresponding to the weight of the ancestor is 0.11 'the same reason', the rest of the output points can be based on the corresponding sampling point information. The corresponding weight value can be known by comparing the weights with the chart. Since the interpolation control value of the present invention is established by the first scale factor and the second scale factor, the product of the original resolution and the first scale factor is equal to the target display (four) resolution and the second scale factor. Product, the financial output ^ look at the control value can be touched. In the example of the three figures, after sampling 5 sampling points, according to the foot information, there will be 7 pixels remaining in the left side, and 6 times of scaling will be continued with the 5th sampling point. Interpolating the first starting pixel, so the sixth sampling pixel that is sampled after 8 pixels is the 5th original pixel, so the 5th original pixel scale can be used as the axis The first original pixel of the operation is performed, and the interpolation operation is continued according to the interpolation control value. The cycle starting point of the above interpolated control value will be different with the difference of the ridge degree, that is, the clearance factor will have different cycle starting points. In the present invention, since the complex interpolation control value is provided in advance, when the interpolation operation is performed, the corresponding information can be obtained by comparing the interpolated control values with the 200841321, so as to facilitate the interpolation of the input image to generate an output image, so Simplify the adjustment circuit for adjusting the image, reduce the cost of the calculation circuit, and improve the efficiency of the image adjustment, and can perform interpolation operations in a loop. In addition, since the information in the interpolation control value of the present invention is an integer, the operation can be simplified when performing the interpolation operation, so that the interpolation operation can be performed without using a complicated operation circuit, so as to improve the efficiency of adjusting the image. the goal of. Please refer to the fifth figure, which is a block diagram of a preferred embodiment of the interpolation circuit of the present invention. The interpolation circuit 2G shown in the fifth diagram is applied to the vertical interpolation circuit 14 and the horizontal interpolation circuit 16 of the second figure. As shown in the figure, the interpolation circuit 2 of the present invention comprises a storage unit 3, a complex data climbing loop circuit 40, a controller 50, a selection unit 6A, an arithmetic circuit 7A, and a clock. The generator 80 is coupled to an image line register 90. The storage unit 3 is used to store the complex interpolation values, and different mt pairs are difficult to distinguish. Each of the data miscellaneous loop circuits 4 () stores a set of data flags, each of which has a difference in correspondence and corresponds to a different interpolated control value, and each of the 1 material flags includes a plurality of data flags, and A data flag corresponding to the interpolated control value. When any of the grazing shift cycle circuits 40 is driven by the controller 50, the data flags are sequentially outputted in sequence. " the controller 50' respectively sends a corresponding one of the selection signal and a driving signal to the selection unit 60 and the data Weiwei circuit 40 according to the target display resolution and the original resolution φ transmitted by the detecting circuit 12. -. The fresh element 6G will insert the comparison value into the arithmetic circuit 70. The driving signal sent by the controller 5 is used to drive one of the data shifting loop circuits 4, and the data shifting loop circuit 4 driven by the controller 50 corresponds to the interpolation control output by the selecting unit 60. value. The clock generator 8 is configured to generate a synchronizing pulse signal and transmit it to the data shifting loop circuit and the arithmetic circuit. According to the above, the data shifting loop circuit 4 outputs the data flag to the transport circuit 70 in sequence according to the synchronous pulse signal, and the arithmetic circuit 70 temporarily stores the image line register 90 according to the synchronous pulse signal interpolation operation. The input image is generated to produce an output image. When the operation circuit 7 interpolates the input image, the data flag and the selection unit (9) 200841321 outputted by the data shifting loop circuit 4 are sequentially inserted, and the image processing target image display is performed. Resolution image requirements specifications. For example, when the data flag received by the operation circuit 70 is i, the interpolation operation is performed according to the interpolation control value corresponding to the data f flag; when the data flag received by the operation circuit 7 is 2, That is, the interpolation operation is performed according to the interpolated control value corresponding to the data flag of 2. The arithmetic circuit 7 of the present invention is based on -, linear interpolation (Linear Interp〇lati〇n), a sine interpolation method (Sine Interpolation), and a cubic convolution interpolation method (Cubic c〇nv〇luti()n One of the Interpolation) performs an interpolation operation. The interpolation circuit 20 of the fifth embodiment is applied to the horizontal interpolation circuit 16 (refer to the second figure), so the data stored in the image line register 90 is transmitted by the vertical interpolation circuit 14 (refer to the second figure). The new picture is read, and the miscellaneous data generated by the circuit is transmitted to the age unit and displayed. The image data stored in the vertical interpolation circuit 14 is stored, and the image data temporarily stored in the image line register 9 is transmitted to the display image of the display H, and the circuit 7 is generated. The peak image is a vertical pixel dragon and is transmitted to the horizontal line circuit (4) temporarily stored in the image line register 90 of the horizontal interpolation circuit 16. In addition, the vertical interpolation circuit 运算the arithmetic circuit 7 is used in the interpolation operation. The vertical resolution of the original resolution of the input image and the resolution of the target display are mixed. The flag, and the horizontal interpolation circuit 1 port 6 乂 operation circuit 70 according to the original resolution of the input image of the horizontal resolution and the target display resolution of the horizontal resolution of the corresponding __ value and data flag. And FIG. 3 is a flow chart of a preferred embodiment of the present invention. As shown in the figure, according to the interpolation method of the heart image adjustment of the present month, first, as shown in step s〇, the complex interpolation control value and the corresponding plural number flag are provided, and each _Fleet contains multiple data. The flag, that is, the data flag stored by the complex data shifting loop circuit 40; thereafter, the detecting circuit 12 performs the step S1. After measuring the input shirt image, the original resolution of the input image is obtained and transmitted to the controller; then, the controller, 5ΰ, step S2, according to the original resolution of the input image and the target display resolution, respectively The face fiber and the chicken touch ^ lion 6 () and the scaly shift cycle circuit 40 to select the corresponding interpolated control value and the complex data flag. Then, the arithmetic circuit 70 proceeds to step S3 to sequentially interpolate the input image according to the data flags and the interpolation value of the 200841321, and generate a secret image that conforms to the resolution of the target display. In addition, in order to avoid the timing of the data shifting of the data shifting loop circuit 40 and the timing of the operation-circuit 7 (four) interpolating the input image, the clock generator 80 is generated when the operating circuit 70 performs this step. The synchronous clock signal is transmitted to the data shifting loop circuit 40 and the arithmetic circuit 70, so that the data shifting loop circuit 4 outputs the data flag in sequence according to the synchronous clock signal, and the arithmetic circuit 70 is based on the synchronization time. The pulse signal synchronization calculates the input image to generate an output image based on the data flag and the interpolated control value. In summary, the interpolating circuit and the interpolating method of the image adjusting circuit of the present invention, by the controller, according to the resolution of the target display and the original resolution of the input image, the selected gas puncturing and driving signals are selected. The unit and the complex data shifting loop circuit select the corresponding interpolated control value and the complex data flag, so that the arithmetic circuit interpolates the input image according to the output data flag and the interpolated value. The output image that meets the resolution of the target display can be used to quickly adjust the image and improve the efficiency of image adjustment. The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and the variations, modifications, and modifications of the shapes, structures, features, and spirits described in the claims of the present invention. All should be included in the scope of the invention. i , :10 [Simple description of the diagram] The first picture is a schematic diagram of the adjustment of the conventional image magnification. The second figure is a block diagram of the image adjustment circuit of the present invention. The third figure is an interpolation control value of the preferred embodiment of the present invention. The fourth figure is a weight comparison diagram of a preferred embodiment of the present invention. I Figure 5 is a block diagram of a preferred embodiment of the interpolation circuit of the present invention. Figure 6 is a flow chart of a preferred embodiment of the present invention. [Main component symbol description] 10 Image adjustment circuit 12 200841321 12 Detection circuit 14 Vertical interpolation circuit 16 Horizontal interpolation circuit 18 Display unit 20 Interpolation circuit 30 Storage unit 40 Data shift cycle circuit 50 Controller 60 Selection unit 70 Operation Circuit 80 clock generator 90 video line register