TW200839908A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
TW200839908A
TW200839908A TW096148508A TW96148508A TW200839908A TW 200839908 A TW200839908 A TW 200839908A TW 096148508 A TW096148508 A TW 096148508A TW 96148508 A TW96148508 A TW 96148508A TW 200839908 A TW200839908 A TW 200839908A
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Taiwan
Prior art keywords
solder
wiring substrate
manufacturing
semiconductor device
semiconductor wafer
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TW096148508A
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Chinese (zh)
Inventor
Kenji Hanada
Ryosuke Kimoto
Masaki Nakanishi
Jumpei Konno
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Renesas Tech Corp
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Publication of TW200839908A publication Critical patent/TW200839908A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

The manufacturing method for semiconductor device of the present invention is provided to improve wettability of solder in making flip-chip connection with gold-solder connection. A heat treatment is performed, and subsequently the flip-chip connection is made with gold-solder connection to remove organic materials (e.g., carbon) attached to the surface of the solder 6, thereby ensuring wettability of the solder 6 so that a gold-solder connection can be made. In the aforementioned heat treatment, a flame 14 formed by burning mixed gas of hydrogen and dried air is irradiated to a solder 6 on a plurality of flip terminals on a package substrate 3 via a mask 12 arranged between a torch 13 and the package substrate 3 such that a surface temperature of the package substrate 3 is in the range of 160 to 170 DEG C .

Description

200839908 九、發明說明： 【發明所屬之技術領域】 本發明關於一種半導體製造技術，尤其關於一種適用於 金-焊錫連接之焊錫改性製程的有效的技術。 【先前技術】 對於經由焊錫凸塊將裸晶片連接至安裝基板上之電子零 件之安裝，有使用刮擦式清潔器來機械性、物理性地除去200839908 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor fabrication technique, and more particularly to an efficient technique for a solder-modified process for gold-solder connections. [Prior Art] For the mounting of an electronic component to which a bare die is attached to a mounting substrate via solder bumps, a scraper cleaner is used for mechanical and physical removal.

形成於焊錫凸塊表面上之氧化膜之技術（例如，參照專利 文獻1)。 又，對於具有藉由成型樹脂而密封之封裝之表面安裝型 半導體裝置，有對封裝背面照射雷射光以除去成型樹脂表 面之蠟成分之技術（例如，參照專利文獻2)。 [專利文獻1] 曰本專利特開2002-203872號公報 [專利文獻2] 曰本專利特開平1 1-68004號公報 【發明内容】 [發明所欲解決之問題] 將半V體晶片覆晶接合於佈 ，預先於搭載有半導體晶片 當裝配藉由金-焊錫連接而 線基板上而成之半導體裝置時 之佈線基板之電極上塗佈焊錫 然而，因於該焊錫之表面上形成有氧化膜及有機 膜，故會使焊錫之潤濕性（對形成於半導體晶片上 ’、 之潤濕性）降低，或使潤濕性產生不 7 之凸塊 J LJ此，當將半導 127604.doc 200839908 體晶片覆晶接合於佈線基被μ㈣/ 攸上金-焊錫連接），首先，預 先對佈線基板進行烘烤，谁& ^ 向’進行Ar電漿處理，但僅藉 由該Ar電槳處理，無法除去揑 于舌年錫表面之有機膜。因此，為 了提高焊錫之潤濕性（對焊踢之声 两之表面進行改性），已設計出 了各種方法。 人研究出之用以提高 以下所示之1)〜5)係本申請案發明 烊錫潤濕性之方法及其問題點。A technique of forming an oxide film on the surface of a solder bump (for example, refer to Patent Document 1). Moreover, the surface mount type semiconductor device having a package sealed by a molding resin has a technique of irradiating the back surface of the package with laser light to remove the wax component of the surface of the molded resin (for example, see Patent Document 2). [Patent Document 1] JP-A-2002-203872 [Patent Document 2] Japanese Patent Laid-Open Publication No. Hei No. Hei No. Hei No. Hei. Bonding the cloth to the electrode of the wiring substrate in which the semiconductor wafer is mounted on the wire substrate by the gold-solder connection, but the oxide film is formed on the surface of the solder. And the organic film, so that the wettability of the solder (the wettability formed on the semiconductor wafer) is reduced, or the wettability is not caused by the bump J LJ, when the semi-conductive 127604.doc 200839908 The wafer is flip-chip bonded to the wiring substrate by μ (four) / 攸 gold-solder connection), first, the wiring substrate is baked in advance, who & ^ to Ar plasma treatment, but only by the Ar electric paddle The organic film that is pinched on the tin surface of the tongue cannot be removed by treatment. Therefore, in order to improve the wettability of the solder (modification of the surface of the welding kick), various methods have been devised. The method for improving the wettability of bismuth tin and the problems thereof which have been developed by the present invention to improve the following 1) to 5).

υ-種於佈線基板之電極上之烊錫預㈣上塗佈助㈣ 而安裝半導體晶片之方法。對於該方法而言，助焊劑中含 有函物質’可藉由該除去形成於佈線基板之焊錫表 面上之氧㈣及有機污染臈。此時’ & 了不會再次於佈線 基板之焊錫之表面上形成氧化膜及有機污染膜，於殘存有 鹵物質之狀態下’將半導體晶片安裝於佈線基板上。然 而’若於將半導體晶片安裝^佈線基板上後仍殘留有助焊 :’則該助焊劑會腐蝕形成於半導體晶片之主面上之鋁製 、干.占(表面電極)。因此，於利用助焊劑除去形成於佈線基 板之焊錫之表面上之氧化膜及有機污染膜後，例如必須藉 由清洗除去該助焊劑。 曰 然而，當應用覆晶接合時，難以進行上述清洗步驟。其 理由在於，當進行金-焊錫連接時，形成於半導體晶片上 之金凸塊與佈線基板之電極之接合強度相對較低，因此， 有必要於半導體晶片與佈線基板之間填充底層填料。該底 运真=肩於不降低安裝半導體晶片時之溫度之狀態下填 *進行巧洗步驟，則必須於填充底層填料之前進行、、主 127604.doc 200839908 洗為了進行清洗，必須將p /士治廿 貝將上述佈線基板暫時自載物台 (…、态）卸下。然而，若自載物A 4 ^ 右目戟物台卸下上述佈線基板，則 會引起如下問題，即，因冷 產生之熱收縮應力會破壞 于踢之連接部。因此，盔曰 ..匕 …、於覆日日接合後實施助焊劑清 洗，故塗佈助焊劑之1)之方法不可行。 2)-種使叫電㈣㈣進行清潔之方法法係 可有效地除去有機物之方法 “ 錢之m而，於佈線基板上之作為 (' X, 絶緣μ之阻焊劑中含有齒物質， ^ ^ 、右對佈線基板照射〇2雷 水’則會自阻焊劑釋放出大量 表声中殘…雜 大里之齒離子。若於佈線基板之 門離子之狀態下進行樹脂成形，則會有如下 即’於耐濕性之偏誤測試中，函離 響，於各個部位發生腐钱現象。即，自產品（半導體裝置 之财濕性方面考慮，2)之方法不可行。 、 3)—種使用斛電漿對焊錫 ^ . Λ 仃π冰之方法。Ar電漿法係 使Ar之原子撞擊物質，從而機械地撞飛對象物之方 又，但效果不明顯’並且有時會增加其他之有機污·。 又，因佈線基板之溫度會升古 ^ ^ ^ ^ - A ^ 子在自佈線基板釋放出 乳體而導致再次污染等問題，藉此，取方法不可行。 4) 一種於塗佈助焊劑德 一 p 、 後進仃回流焊，其後，進行清渰 (醇系）方法。即，該方法待# 力次係於進行金_焊錫連接之 進行助焊劑清洗之方法，作 預先 有機物，因此4)之方法亦不可行。 篇再-人附者 、主5) 一種將4)之制醇系進行清洗，替換成利用水系進行 >月洗之方法。問題在於益、、表 ’、 丁 、…、/同B寸除去有機物與氡化膜，因 127604.doc 200839908 此5)之方法亦不可行。 根據以上所述，作為提高焊锡潤濕性之方法，本申請案 發明人研究出之上述υ〜5)之方法不可行。 ” 又於上述專利文獻ι(日本專利特開2002_203872號公 報）中揭不有藉由刮擦式清潔器來機械性、物理性地除去 ^ ^於燁錫凸塊表面上之氧化臈之技術，但問題在於，於 »亥ί月况％，因對焊錫凸塊施加負載，故焊錫凸塊容易破υ - A method of mounting a semiconductor wafer by coating (4) on a tin-plated electrode on an electrode of a wiring substrate. In this method, the flux contains a substance "by removing oxygen (4) and organic contamination enthalpy formed on the surface of the solder substrate of the wiring substrate. At this time, the oxide film and the organic contamination film are not formed on the surface of the solder of the wiring board again, and the semiconductor wafer is mounted on the wiring board in a state where the halogen substance remains. However, if the solder is left after the semiconductor wafer is mounted on the wiring substrate, the flux will erode the aluminum and dry (surface electrode) formed on the main surface of the semiconductor wafer. Therefore, after the oxide film and the organic contamination film formed on the surface of the solder of the wiring substrate are removed by the flux, for example, the flux must be removed by cleaning.曰 However, when the flip chip bonding is applied, it is difficult to perform the above cleaning step. The reason is that when the gold-solder connection is performed, the bonding strength between the gold bumps formed on the semiconductor wafer and the electrodes of the wiring substrate is relatively low, and therefore it is necessary to fill the underfill between the semiconductor wafer and the wiring substrate. The bottom pass true = shoulders without filling down the temperature at which the semiconductor wafer is mounted, and the step of washing is carried out before the filling of the underfill, and the main 127604.doc 200839908 is washed for cleaning, p / 士The mussels are temporarily removed from the stage (..., the state). However, if the above-mentioned wiring substrate is removed from the self-loading material A 4 ^ right target stage, there arises a problem that the heat shrinkage stress due to the cold is broken by the kick connecting portion. Therefore, the method of applying the flux 1) after the bonding on the day of the day is not feasible. 2) - The method of cleaning electricity (4) (4) is a method that can effectively remove organic matter. "Money m, on the wiring substrate ('X, insulation μ solder resist contains tooth substance, ^ ^, When the right side of the wiring substrate is irradiated with 〇2 thunder water, the self-resisting flux releases a large amount of tooth ions in the residual sound. If the resin is formed in the state of the gate electrode of the wiring substrate, the following is In the test of the moisture resistance, the letter is rusted and the money is rotted in various parts. That is, the method of product (the wettability of the semiconductor device, 2) is not feasible. 3) Pulp to solder ^ . Λ 仃 π ice method. Ar plasma method makes the atom of Ar strike the substance, so that it mechanically hits the object, but the effect is not obvious 'and sometimes increases other organic pollution · Moreover, since the temperature of the wiring substrate rises, the ^ ^ ^ ^ - A ^ sub-releases the milk from the wiring substrate to cause re-contamination, etc., thereby making the method infeasible. 4) One is to apply the flux Deyi p, after reflow soldering, and then proceed The method of cleaning (alcohol system). That is, the method is to be used as a pre-organic material for the method of performing flux cleaning for gold-solder connection, and therefore the method of 4) is not feasible. Main 5) A method in which the alcohol system of 4) is washed and replaced with a water-based method for monthly washing. The problem is that the organic matter and the bismuth film are removed by the benefits, the table, the butyl, the ... 127604.doc 200839908 The method of 5) is also not feasible. According to the above, as a method for improving solder wettability, the method of the above-mentioned υ~5) which the inventor of the present application has studied is not feasible. The technique of mechanically and physically removing the yttrium oxide on the surface of the bismuth tin bump by a scratch cleaner is disclosed in the patent document ι (Japanese Patent Laid-Open Publication No. 2002-203872), but the problem is that In the case of »海ί月况%, due to the load on the solder bumps, the solder bumps are easy to break.

又，於上述專利文獻2(日本專利特開平號公報） 中揭示有對封裝背面照射雷射光以除去犧成分(有機膜)之 技術’此時’因雷射光之照射對象係封裝（樹脂），故可利 用南溫之一次性照射除去有機膜，但當照射對象為佈線基 板時，若欲利用高溫之一次性照射來除去有機膜，則會引 起基板表面之阻焊劑燃燒之問題。 進而’當照射對象為佈線基板時，因於焊錫凸塊之周圍 配置有導線接合用之引線（電極）等，故若僅照射高溫雷射 光，則亦會產生導線接合用之引線燃燒之不良情況。 本發明之目的在於提供一種可課求提高藉由金-焊錫連 接進行覆晶接合時之焊錫潤濕性之技術。 本《月之其他目的在於提供—種可謀求提高底層填 料之渗透性且提高覆晶接合用之焊錫潤濕性之技術。 本發明之上述及其他目的以及新賴特徵由本說明書之記 述以及附圖當可明瞭。 [解決問題之技術手段] 127604.doc 200839908 間导纟兄明本申請幸所想_ 下 月茶所揭不之發明中具代表性者之概要如 即，本發明包括下述步· 〆驟·準備於複數個電極上塗佈有 焊錫之佈線基板；藉由佶用 尸 更用了風軋與乾燥空氣之混合氣體 之氫燃燒’對上述焊錫谁并為 · 丁…、處理；將於複數個表面電極 上接合有金凸塊之半導辦曰μ 干^體日日片配置於佈線基板上，其後， 對焊錫進行加熱熔融，連接入 連接孟凸塊與焊錫以進行覆晶接 合；於半導體晶片與佈後其 抑深暴板之間填充底層填料。 又’本發明包括下述步驟· < 乂驟·將於禝數個電極上塗佈有焊 錫之佈線基板配置於所雲 、所而之％境内，於上述環境内形成第 1 Ar電漿以除去佈線基板 一 板主面之汚物；於上述除去污物之 :驟後’藉由使用了氯氣與乾燥空氣之混合氣體之氯燃 凡，對佈線基板之複數個電極上之焊錫進行熱處理。並 且’本發明包括下述步驟. 將於複數個表面電極上接合有 金凸塊之第1丰導轉曰μ & w 弟牛V體曰曰片配置於佈線基板之主面上，宜 後，對焊錫進行加熱熔融，連 逆接孟凸塊與焊錫，斟第】车 導體晶片進行覆晶接合；於第1#_曰^ 丰 丰^體晶片與佈線基板之 間填充底層填料；使第2半導 #认Μ , 干导體日日片之主面朝向上方而搭 载；弟1半導體晶片上。又， 毛明進而包括下述步驟： 將佈線基板配置於所需之 2Ar雷將 兄内於上迷裱境内形成第 物1水’以除去佈線基板主面之複數個谭接引線之污 1於上料去污物之步驟後，藉由導電性之導線，分別 電性連接第2半導體晶片主面之 其如 1数個表面電極、與佈線 基板主面之複數個焊接引線。 127604.doc -10- 200839908 [發明之效果] 間早.兒月本申明案所揭示之發明中由具代表 之效果如下。 可所獲仔 藉由使用了氫氣虚兹操办名 … 氧之混合氣體之氫燃燒，對備 :基板之複數個電極上之焊錫進行熱處理，其後，利： 金-焊錫連接進行覆晶接合，藉此除去附著於焊㈣= Γ 接機物以提面焊錫之潤濕性，可實現良好之金-烊錫連 【實施方式】 於以下之實施形態中，除了有特別需要時以外， 不對相同或同樣之部分進行重複說明。 再：：於以下之實施形態中，當為了方便起見且有必要 夺，y刀告J成複數個部分或實施形態進 方之-部分或全部之變形例、詳述、補充說明等之關係。 數又數：以：之實施形態中’當涉及要素之數等(包括個 :、數值1、範圍等)時’除了特別指明之情況 :上明確限定於特定數之情況等以外，不限定 數，可為特定數以上，亦可為以下。 寸疋 ::下再：據隨附圖式，詳細地對本發明之實施形態進行 t月射再者，於用以對實施形態進行說明之所有隨附圖式 中，對具有相同功能之部件標記相同符號 =明…為了使隨附圖式便於理解，有二 體圖或平面圖附上影線。 127604.doc -11 - 200839908 (實施形態） 圖1係表示本發明實施形態之半導體装置之製造方法之 一例之製程流程圖’圖2係表示圖丨所 造方法中所使用之佈線基板之構造之一例+之；^置之圖^ . 係表示沿著圖2所示之A-A線截斷所得之構造之一例之剖面 . 圖：圖4係表示圖1所示之半導體裝置之製造方法中之氫燃 燒怜之遮罩配置狀態之構造之一例之平面圖，圖5係沿著 r 圖4所示之Α-Α線截斷所得之構造之一例之剖面圖。又，圖 6係表示圖】所示之半導體裝置之製造方法中之氫燃燒狀態 之一例之概念圖，圖7係表示圖1所示之半導體裝置之製造 方法中之覆晶接合時之構造之一例之平面圖，圖8係沿著 圖7所示之Α—Α線截斷所得之構造之一例之剖面圖，圖9係 模式性地表示圖1所示之半導體裝置之製造方法中之氫燃 燒以及覆晶接合後之覆晶接合部之構造之一例之放大剖面 圖。進而，圖10係表示圖1所示之半導體裝置之製造方法 C, 中之底層填料填充時之構造之一例之平面圖，圖1 1係表示 &著圖10之Α-Α線截斷所得之構造之一例之剖面圖，圖12 2表示圖丨所示之半導體裝置之製造方法中之第2層晶片接 一寺之構‘之一例之平面圖，圖13係表示沿著圖12之A_ A • 線截斷所得之構造之一例之剖面圖。又，圖14係表示圖1 所不之半導體裝置之製造方法中之導線接合時之構造之一 J之平面圖，圖1 5係表示沿著圖14之A-A線截斷所得之構 ‘之一例之剖面圖，圖16係表示圖丨所示之半導體裝置之 黎k方去中之樹月曰牷封後之構造之一例之剖面圖，圖17係 127604.doc -12- 200839908 表示圖1所示之半導體裝置之製造方法中之球焊後之構造 之一例之剖面圖。 ^實施形態用於說明半導體裝置之裝配，該半導體裝置 係藉由連接形成於半導體晶片上之金凸塊與形成於佈線基 板之電極（焊接引線）上之谭锡（金-焊锡連接），將半導體晶 片覆曰曰接口於佈線基板上而成之，於本實施形態中，列舉 衣入有複數個半導體晶片之被稱作sip(SyWm匕 f、Further, in the above-mentioned Patent Document 2 (Japanese Patent Laid-Open Publication No. Hei-kai) Therefore, the organic film can be removed by the one-time irradiation of the south temperature. However, when the object to be irradiated is the wiring substrate, if the organic film is to be removed by the high-temperature one-time irradiation, the solder resist on the surface of the substrate is burned. Further, when the object to be irradiated is a wiring board, a lead wire (electrode) for wire bonding or the like is disposed around the solder bump. Therefore, if only high-temperature laser light is irradiated, the lead wire for wire bonding may be burnt. . SUMMARY OF THE INVENTION An object of the present invention is to provide a technique for improving solder wettability when flip chip bonding is performed by gold-solder bonding. The other purpose of this month is to provide a technique for improving the permeability of the underfill and improving the solder wettability for flip chip bonding. The above and other objects and novel features of the present invention are apparent from the description of the specification and the accompanying drawings. [Technical means to solve the problem] 127604.doc 200839908 纟 纟 明 明 本 本 申请 申请 申请 申请 申请 _ 概要 概要 概要 概要 概要 下 下 下 下 下 下 下 下 下 下 下 下 下 下 下 下 下 下 下 下 下 下 下 下 下 下 下It is prepared to apply a solder wiring board to a plurality of electrodes; and to burn the hydrogen of a mixed gas of air-rolled and dry air by using the corpse, the solder is used for the above-mentioned solder, and the processing will be performed; The semiconductor electrode on which the gold bump is bonded to the surface electrode is disposed on the wiring substrate, and then the solder is heated and melted, and the connection between the gate bump and the solder is connected to perform the flip chip bonding; The underfill is filled between the semiconductor wafer and the slab after the cloth. Further, the present invention includes the following steps: < a step of arranging a wiring substrate on which a plurality of electrodes are coated with solder is disposed in a cloud, and the first Ar plasma is formed in the environment The dirt on the main surface of one of the wiring boards is removed; after the above-mentioned removal of the dirt, the solder on the plurality of electrodes of the wiring substrate is heat-treated by using chlorine gas mixed with a mixture of chlorine gas and dry air. And the present invention includes the following steps. The first rich transition 曰μ & w of the gold bumps on the plurality of surface electrodes is disposed on the main surface of the wiring substrate, preferably The solder is heated and melted, and the bumps and solders are reversely connected, and the ruthenium conductor film is flip-chip bonded; the underfill is filled between the first #_曰^ Fengfeng body wafer and the wiring substrate; The semi-conductor # Μ , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Moreover, the hair styling further includes the steps of: arranging the wiring substrate in the desired 2Ar ray to form the first water in the upper viscera to remove the plurality of tanned leads of the main surface of the wiring substrate After the step of feeding the decontamination material, a plurality of surface electrodes and a plurality of soldering leads of the main surface of the wiring substrate are electrically connected to the main surface of the second semiconductor wafer by conductive wires. 127604.doc -10- 200839908 [Effects of the Invention] The effects represented by the invention disclosed in the present invention are as follows. The obtained hydrogen can be heat-treated by using a hydrogen gas mixture, hydrogen is mixed with oxygen, and the solder on the plurality of electrodes of the substrate is heat-treated, and thereafter, the gold-solder connection is subjected to flip chip bonding. Therefore, the wettability of the solder (4) = Γ pick-up to the surface solder can be removed, and a good gold-ruthenium tin can be realized. [Embodiment] In the following embodiments, the same is true except for special needs. Repeat the same for the same part. Further: In the following embodiments, for the sake of convenience and necessity, the relationship between the y knives and the partial or partial modifications, detailed descriptions, supplementary explanations, etc. . In addition to the case where the number of factors involved (including one:, numerical value, range, etc.) is used in the embodiment, except for the case where it is specifically specified: the case where the number is explicitly limited to a specific number, etc., the number is not limited. It can be a specific number or more, or the following. In the following, the embodiment of the present invention is further described in detail with reference to the accompanying drawings, and in the accompanying drawings for describing the embodiments, the components having the same function are marked. The same symbol = Ming... In order to make the drawing easier to understand, there is a two-body diagram or a plan view with a hatching. 127604.doc -11 - 200839908 (Embodiment) FIG. 1 is a process flow chart showing an example of a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a view showing a structure of a wiring board used in the method of the method of the invention. An example of a ^ is shown in Fig. 2 is a cross section of a structure obtained by cutting along the AA line shown in Fig. 2. Fig. 4 is a view showing hydrogen combustion in the manufacturing method of the semiconductor device shown in Fig. 1. A plan view showing an example of the configuration of the pity mask configuration state, and Fig. 5 is a cross-sectional view showing an example of the structure obtained by cutting off the Α-Α line shown in Fig. 4. 6 is a conceptual diagram showing an example of a hydrogen combustion state in the method of manufacturing the semiconductor device shown in FIG. 1, and FIG. 7 is a view showing a structure at the time of flip chip bonding in the method of manufacturing the semiconductor device shown in FIG. FIG. 8 is a cross-sectional view showing an example of a structure obtained by cutting off the Α-Α line shown in FIG. 7, and FIG. 9 is a view schematically showing hydrogen combustion in the method of manufacturing the semiconductor device shown in FIG. An enlarged cross-sectional view showing an example of a structure of a flip chip joint after flip chip bonding. Further, Fig. 10 is a plan view showing an example of a structure in which the underfill material is filled in the manufacturing method C of the semiconductor device shown in Fig. 1, and Fig. 11 shows a structure obtained by cutting off the Α-Α line of Fig. 10. A cross-sectional view of an example, FIG. 12 is a plan view showing an example of the structure of the second layer of the wafer in the manufacturing method of the semiconductor device shown in FIG. 1, and FIG. 13 is a line along the line A_A of FIG. A cross-sectional view of an example of the resulting structure is truncated. Further, Fig. 14 is a plan view showing a structure at the time of wire bonding in the method of manufacturing the semiconductor device shown in Fig. 1, and Fig. 15 is a view showing a section taken along the line AA of Fig. 14 Figure 16 is a cross-sectional view showing an example of a structure in which the semiconductor device shown in Figure 黎 is in the middle of the tree, and Figure 17 is 127604.doc -12- 200839908, which is shown in Figure 1. A cross-sectional view showing an example of a structure after ball bonding in a method of manufacturing a semiconductor device. The embodiment is for explaining the assembly of a semiconductor device by connecting a gold bump formed on a semiconductor wafer and a tan tin (gold-solder connection) formed on an electrode (solder lead) of the wiring substrate. The semiconductor wafer is bonded to the wiring board. In the present embodiment, a plurality of semiconductor wafers are referred to as sip (SyWm匕f,

PaCkage，系統級封裝）之半導體封裝7,作為上述半導體褒 置之一例進行說明。 s於上述SIP(半導體封裝7)中裝人有記憶體晶片與微電腦 晶片，該記憶體晶片具有記憶體電路，該微電腦晶片對上 述記憶體晶片進行控制，並與半導體封裝7之外部交鮮 號，於本實施形態中，列舉如圖17所示之裝入有一個微電 腦晶片（第i半導體晶片υ與一個記憶體晶片（第巧導體晶 片2)之半導體封裝7作為一例’但所裝入之半導體晶片之 數量只要為兩個以上即可。又，當半導體封裝7並非⑽ 時，所裝入之半導體晶片之數量亦可為一個。 即，本實施形態之半導體封裝7只要至少具有一個藉由 金-焊錫連接而覆晶接合於佈線基板上之半導體晶片即 可’於圖17所示之半導體封裝7(SIp)中，藉由金.焊錫連接 將第1層之半導體晶片 '即第i半導體晶片（微電腦晶片口覆 晶接合於佈線基板上，其後，將第2層之第2半導體晶片 (圮憶體晶片）2積層於第丨半導體晶片丨上。再者，第2半導 體晶片2導線連接於佈線基板上。 127604.doc -13- 200839908 繼而，對半導體封裝7之詳細構造進行說明，該半導體 封裝7包括··搭載有半導體晶片之封裝基板（佈線基板、 藉由金-焊錫連接而覆晶接合於封裝基板3上之作為微電腦 晶片之第1半導體晶片1、積層於第丨半導體晶片丨上之作為 記憶體晶片之第2半導體晶片2、複數條導線4、由密封樹 脂形成之樹脂體10、以及複數個作為外部端子之焊球8。 封裝基板（佈線基板）3具有作為晶片搭載面之主面3a與位 於主面3a相反側之背面3b，於主面3a上形成有用於覆晶接 合之複數個覆晶接合用端子（焊接引線）3c、以及與導線4連 接之複數個導線連接用端子（焊接引線）3(1。複數個覆晶接 合用端子3c以及導線連接用端子3d自形成於主面〜上之作 為絕緣膜之阻焊劑3e露出。複數個覆晶接合用端子3c以能 夠與苐1半導體晶片1覆晶接合之方式，以與第1半導體晶 片1之主面la之複數個焊點（電極）lc相同之排列而形成。進 而’以能夠經由導線4與第1半導體晶片1上之第2半導體晶 片2連接之方式，沿著第1半導體晶片1之晶片搭載區域之 外側’即沿著封裝基板3之主面3&之緣部形成有複數個導 線連接用端子（焊接引線）3d。 又’第1半導體晶片1以及第2半導體晶片2分別具有主面 la、2a及背面lb、2b，於各主面la、2a上形成有複數個作 為電極之焊點lc、2c。 再者’第1半導體晶片1藉由金-焊錫連接而覆晶接合於 佈線基板上。即，於第1半導體晶片1之主面la與封裝基板 3之主面3a相向之狀態下，經由金凸塊5以及焊錫6而覆晶 127604.doc -14 - 200839908 接合第1半導體晶片1之焊點lc與封裝基板3之覆晶接合用 端子3c。 進而，於第1半導體晶片1之覆晶接合部或第1半導體晶 片1與封裝基板3之間、以及晶片側面填充有底層填料9， 保護第1半導體晶片1或上述覆晶接合部。 另一方面，第2半導體晶片2經由薄膜狀黏接材料丨丨等， 黏著於朝向上方之第i半導體晶片i之背面113上。此時，因 弟2半‘體晶片2與封裝基板3導線連接，故朝向上方地黏 著於-亥弟2半導體晶片2之主面2a上。即，經由薄膜狀黏接 材料11等而連接第2半導體晶片2之背面2b與第1半導體晶 片1之背面1 b。 又’第2半導體晶片2之主面2a之焊點2c藉由金線等導線 4 ’與封裝基板3之主面3 a之導線連接用端子3d電性連接。 又’第1半導體晶片1、第2半導體晶片2以及複數個導線 4等被樹脂體10覆蓋、密封，該樹脂體1〇藉由密封樹脂而 形成於封裝基板3之主面3&上。上述密封樹脂例如為熱硬 化性環氧樹脂。 又’於封裝基板3之背面3b設置有作為半導體封裝7之外 4端子之複數個焊球8，第1半導體晶片1及第2半導體晶片 2藉由封裝基板3之覆晶接合用端子3c及導線連接用端子 3d ’與對應之焊球8電性連接。 其次’根據圖1所示之製造製程流程，對本實施形態之 半導體裝置之製造方法進行說明。 首先如圖1之步驟S 1所示，準備基板。此時，如圖2以 127604.doc 200839908 及圖3所示，準備封裝基板（佈線基板）3,於該封裝基板3之 主面3a_L形成有複數個電極（覆晶接合用端子㈣導線連 接用端子3d等），且於複數個覆晶接合用端子化各自上塗 佈著焊錫6。The semiconductor package 7 of PaCkage (system-in-package) is described as an example of the above-described semiconductor device. In the SIP (semiconductor package 7), a memory chip and a microcomputer chip are mounted, and the memory chip has a memory circuit, and the microcomputer chip controls the memory chip and communicates with the external portion of the semiconductor package 7. In the present embodiment, as shown in FIG. 17, a semiconductor package 7 in which a microcomputer chip (i-th semiconductor wafer and a memory chip (first conductor wafer 2)) is mounted is taken as an example. The number of semiconductor wafers may be two or more. Further, when the semiconductor package 7 is not (10), the number of semiconductor wafers to be mounted may be one. That is, the semiconductor package 7 of the present embodiment has at least one The semiconductor wafer in which the gold-solder connection is flip-chip bonded to the wiring substrate can be used in the semiconductor package 7 (SIp) shown in FIG. 17, and the semiconductor wafer of the first layer, that is, the i-th semiconductor, is connected by gold solder. The wafer (the microchip wafer is flip-chip bonded to the wiring substrate, and then the second semiconductor wafer of the second layer (the memory wafer) 2 is laminated on the second semiconductor wafer. The second semiconductor wafer 2 is electrically connected to the wiring board. 127604.doc -13- 200839908 Next, the detailed structure of the semiconductor package 7 including the package substrate on which the semiconductor wafer is mounted (the wiring substrate) will be described. a first semiconductor wafer 1 as a microcomputer chip, a second semiconductor wafer 2 as a memory wafer, and a plurality of wires stacked on the second semiconductor wafer by a gold-solder connection 4. A resin body 10 formed of a sealing resin, and a plurality of solder balls 8 as external terminals. The package substrate (wiring substrate) 3 has a main surface 3a as a wafer mounting surface and a back surface 3b on the opposite side of the main surface 3a. A plurality of flip-chip bonding terminals (soldering leads) 3c for flip chip bonding and a plurality of wire bonding terminals (welding leads) 3 connected to the wires 4 are formed on the main surface 3a (1 for a plurality of flip chip bonding) The terminal 3c and the wire connection terminal 3d are exposed from the solder resist 3e which is an insulating film formed on the main surface, and the plurality of flip chip bonding terminals 3c are capable of being half with the 苐1 The conductor wafer 1 is formed by flip chip bonding, and is formed in the same arrangement as the plurality of pads (electrodes) 1c of the main surface 1a of the first semiconductor wafer 1. Further, it can be formed via the wires 4 and the first semiconductor wafer 1. In the method of connecting the second semiconductor wafer 2, a plurality of wire connection terminals (welding leads) 3d are formed along the outer side of the wafer mounting region of the first semiconductor wafer 1, that is, along the edge of the main surface 3 & Further, the first semiconductor wafer 1 and the second semiconductor wafer 2 have main faces 1a and 2a and back faces 1b and 2b, and a plurality of pads lc and 2c as electrodes are formed on the main faces 1a and 2a. The first semiconductor wafer 1 is flip-chip bonded to the wiring substrate by gold-solder connection. In other words, in a state in which the main surface 1a of the first semiconductor wafer 1 faces the main surface 3a of the package substrate 3, the first semiconductor wafer 1 is bonded by the gold bumps 5 and the solder 6 127604.doc -14 - 200839908 The solder joint lc and the flip chip bonding terminal 3c of the package substrate 3. Further, the underlying filler 9 is filled between the flip-chip bonding portion of the first semiconductor wafer 1, the first semiconductor wafer 1 and the package substrate 3, and the wafer side surface, and the first semiconductor wafer 1 or the flip-chip bonding portion is protected. On the other hand, the second semiconductor wafer 2 is adhered to the back surface 113 of the i-th semiconductor wafer i facing upward via a film-like adhesive material 丨丨 or the like. At this time, since the body 2 and the package substrate 3 are electrically connected to each other, the two half-body wafers 2 are attached to the main surface 2a of the semiconductor wafer 2 in the upward direction. In other words, the back surface 2b of the second semiconductor wafer 2 and the back surface 1b of the first semiconductor wafer 1 are connected via the film-like adhesive material 11 or the like. Further, the solder joint 2c of the main surface 2a of the second semiconductor wafer 2 is electrically connected to the lead wire connection terminal 3d of the main surface 3a of the package substrate 3 by a wire 4' such as a gold wire. Further, the first semiconductor wafer 1, the second semiconductor wafer 2, the plurality of wires 4, and the like are covered and sealed by the resin body 10, and the resin body 1 is formed on the main surface 3& of the package substrate 3 by a sealing resin. The above sealing resin is, for example, a thermosetting epoxy resin. Further, a plurality of solder balls 8 as four terminals other than the semiconductor package 7 are provided on the back surface 3b of the package substrate 3, and the first semiconductor wafer 1 and the second semiconductor wafer 2 are connected to the flip chip bonding terminal 3c of the package substrate 3 and The wire connection terminal 3d' is electrically connected to the corresponding solder ball 8. Next, a method of manufacturing the semiconductor device of the present embodiment will be described based on the manufacturing process shown in Fig. 1. First, as shown in step S1 of Fig. 1, the substrate is prepared. At this time, as shown in FIG. 2, as shown in FIG. 2, 127604.doc 200839908 and FIG. 3, a package substrate (wiring substrate) 3 is prepared, and a plurality of electrodes are formed on the main surface 3a_L of the package substrate 3 (terminals for flip chip bonding (4) for wire connection The terminal 3 is immersed in the terminal 3d, and the solder 6 is applied to each of the plurality of flip-chip bonding terminals.

其後’如步驟S2所示，對基板進行烘烤。此處，對基板 進行烘烤之理由之-在於，即使於裝配半導體裝置之前， 一直將封裝基板3存放於濕氣少之環境中，若長時間存 放，有時上述封裝基板3仍會吸濕。因此，藉由該步驟Μ 所示之基板烘烤處理除去已完全渗人至封裝基板3内 分。 之後，進行步驟S3所示之第iAr(氬）電漿處理。即，將 封裝基板3配置於所需之環境内，於上述環境内形成第^ 電漿亚搭載封裝基板3之主面3a，尤其搭載第工半導體晶片 1 ’除去填充底層填料9之區域内之污物。藉此，於之後由 底層填料9密封之區域内不易混入異物，因此，可提高半 導體裝置之可靠性。然而，僅利用S1A：r(氬）電漿處理， …、法7G全除去形成於上述焊錫6表面上之氧化膜及有機污 染膜。 因此，本實施形態中，於實施了第1Ar(氬）電漿處理 後，進行圖1之步驟S4所示之氫燃燒（燃燒、熱處理）步 此處’就先進行步驟S3所示之第1Ar電漿處理步驟、還 是先進行步驟S4所示之氫燃燒（燃燒、熱處理）步驟進行說 明。 " 127604.doc -16- 200839908 百’若僅僅為了提高焊錫6之潤濕性，則可先進行 燃燒，但當全面地考慮半導體封裝7之裝配時，: 樹脂（底層填料9)之渗透性，Ar電漿處理亦尤為重要。两 、因此，本申請案之發明人發現：若於Ar電聚處 進行虱燃燒，則經氫燃燒而暫時變乾淨之焊锡6，合 之後之^電漿處理之污染，導致其潤濕性變差。即^Α 電浆處理中，因各種物質飛散，故該等物質會附著於^ 6上，導致焊錫ό之潤濕性變差。 、 因此，如圖!之流程所示’較好的是於步驟幻 ΙΑι·電漿處理’其後，於步驟以中進行氫燃燒。 ^而，若杨電漿處理之後進行氫燃燒，則進行過 水處理之部位之效果減弱，因 ^ ^ 對於不钬進仃氫燃燒之 4位’如下上述’須於封裝基心上配置遮罩 以及圖5)而進行氫燃燒。 "、、34 —藉此，即使於Ar„處理之後進行氫燃燒，亦可防 行過Ar電漿處理之部位之效果減弱。 又’若對佈線基板之電極以外之地方（絕緣膜）實施心 燒，則會燒到佈線基板之表面， … 氣體。 且有可此自絕緣膜釋放出 然而’如本實施形態上述’隔著遮罩12進行氯燃燒，藉 此可僅燃燒焊錫6。 根據上述理由，較好的是於進行氫燃燒之前進行^電漿 處理。 再者’當進行步驟S3之第1Ar電聚處理時，與下述步驟 127604.doc -17- 200839908 S8之第2Ar電漿處理相比較’較好的是使用以形成第 漿之功率小於用以形成第2Ar電漿之功率。 又，較好的是使步驟S3之施加第iAr電漿之時間，短於 步驟S8之施加第2Ar電漿之時間。 例如’於步驟S3之第IAr電漿處理中，較好的是以3〇() ^ 之功率施加Ar電漿3秒左右。 另一方面，於步驟S8之第2Ar電漿處理中，較好的是以 500 w之功率施加Ar電漿20秒左右。為了提高步驟“之第 2 Ar電漿處理步驟後之步驟S9之導線接合步驟中之導線*與 封裝基板3之導線連接用端子3d之連接性，第2心電漿處理 用於對導線連接用端子3d進行清洗，但隨著裝配步驟之進 行’封裝基板3之污物量亦增大，因此，以比較大之能量 進行第2Ar電漿處理。 相對於此，於步驟S3之第IAr電漿處理步驟中，只要裝 配尚未進行到步驟S8之第2^電漿處理，則封裝基板3之污 物亦較少。因此，若以較大之能量進行第1Ar電漿處理， 則會產生封裝基板3無端受到污染之問題。因此，於步驟 S3之第1Ar電漿處理中，較好的是施加如不能量進行心電 漿處理，該能量係指於使封裝基板3清潔到可提高底層填 料9(樹脂）之滲透性之程度之範圍内之最小能量。 之後，進行步驟S4之氫燃燒（燃燒、熱處理）。即，於步 驟3之第IAr電漿處理之後，藉由使用了氫氣與乾燥空氣 之混合氣體（合成氣體）之氫燃燒，對封裝基板3之複數個覆 晶接合用端子3c上之焊錫6進行熱處理，以提高焊錫6之潤 127604.doc -18· 200839908 濕性。此時，氫氣與乾焊办 ^ /、钇展二軋之混合比率例如為氫氣：乾 燥空氣=1 ·· 2。 θ再者’進行氫燃燒時’藉由使各覆晶接合用端子3c上之 焊錫6與燃燒氫氣與乾燥空 風口軋體所產生之火焰j 4 接觸二主要燒盡並除去附著於焊錫6上之碳等有機物，藉 此提高烊錫6之潤濕性。 對於本實施形態之氫燃燒而言，如圖6所示，當進 行氫燃燒時’於形成氫燃燒用之火焰14之喷燈13與封裝基 板3之間隔著料12而進行氫燃燒n噴㈣盘封裝 基板3之間隔著遮罩12，藉此，不對不欲實施氣燃燒之部 位進行氫燃燒，而僅對欲實施氫燃燒之部位實施氯燃燒。 此時’如圖4以及圖5所示，準備遮罩12，並於將該遮罩 12配置於封裝基板3J^„T進行氫燃燒，上述遮罩12 之開口部12a形成為與封裝基板3之覆晶接合用端子&之排 列相對應之形狀。 藉此，當進行氫燃燒時，自噴燈13噴出之火焰14可僅對 暫時固定於覆晶接合用端子3c上之焊錫6進行加熱，對焊 錫6進行熱處理，藉此可提高焊錫6之潤濕性。此時，遮罩 12之開口部12a形成為與封裝基板3之覆晶接合用端子化之 排列相對應之形狀，該開口部12a以外之區域被遮罩12覆 现，因此，可防止對於步驟S3之第ιαγ電漿處理步驟中藉 由Ar電漿而清洗過之基板表面實施氫燃燒。因此，可防止 步驟S3之第lAr電漿處理之效果因進行氫燃燒而減小。 又，遮罩12之開口部12a形成為與封裝基板3之覆晶接合 127604.doc -19· 200839908 用端子3c之排列相對應之形狀，該開口部i2a以外之區域 被遮罩12覆蓋，因此，可防止因氫燃燒而燒焦基板表面 (主面3a)、或燒焦並損壞安裝於基板表面上之電子零件等 現象。 ΓThereafter, as shown in step S2, the substrate is baked. Here, the reason why the substrate is baked is that the package substrate 3 is always stored in an environment where moisture is small even before the semiconductor device is mounted, and the package substrate 3 may still be hygroscopic if stored for a long period of time. . Therefore, the substrate baking process shown in this step 除去 removes the entire infiltration into the package substrate 3. Thereafter, the i-Ar (argon) plasma treatment shown in step S3 is performed. That is, the package substrate 3 is placed in a desired environment, and the main surface 3a of the second plasma-mounted package substrate 3 is formed in the above-described environment, and in particular, the semiconductor wafer 1 is mounted in the region where the underfill 9 is filled. Dirt. Thereby, foreign matter is less likely to be mixed in the region sealed by the underfill 9 later, and therefore, the reliability of the semiconductor device can be improved. However, only the S1A:r (argon) plasma treatment is used, and the method 7G removes the oxide film and the organic contamination film formed on the surface of the solder 6. Therefore, in the present embodiment, after the first Ar (argon) plasma treatment is performed, the hydrogen combustion (burning, heat treatment) shown in step S4 of Fig. 1 is performed, and the first Ar shown in step S3 is first performed. The plasma treatment step or the hydrogen combustion (combustion, heat treatment) step shown in step S4 will be described first. " 127604.doc -16- 200839908 If you only want to improve the wettability of solder 6, you can burn first, but when considering the assembly of semiconductor package 7, the permeability of resin (underfill 9) , Ar plasma treatment is also particularly important. 2. Therefore, the inventors of the present application found that if the bismuth combustion is carried out at the Ar electropolymerization, the solder 6 which is temporarily cleaned by hydrogen combustion is combined with the contamination of the plasma treatment, resulting in the wettability change. difference. That is, in the plasma treatment, since various substances scatter, these substances adhere to the surface 6, and the wettability of the solder enamel deteriorates. Therefore, as shown in the flow of Fig.!, it is preferable to carry out hydrogen combustion in the step after the step of "Magnetic treatment". ^,, if hydrogen combustion is carried out after the treatment of Yang plasma, the effect of the portion subjected to water treatment is weakened, because ^^ is not required to be immersed in hydrogen burning at the four positions 'the above' is required to be placed on the package base. And Figure 5) performs hydrogen combustion. ",, 34 - Therefore, even if the hydrogen combustion is performed after the Ar„ treatment, the effect of preventing the portion where the Ar plasma treatment is performed is weakened. Further, the place other than the electrode of the wiring board (insulating film) is implemented. If the heart is burned, it will burn to the surface of the wiring board, and the gas may be released from the insulating film. However, as described above, the above-described 'the above-described mask 12 is used for chlorine combustion, whereby only the solder 6 can be burned. For the above reasons, it is preferred to carry out the plasma treatment before the hydrogen combustion. Further, when the first Ar electropolymerization treatment of the step S3 is performed, the second Ar plasma of the following step 127604.doc -17-200839908 S8 is performed. The treatment is preferably 'compared to use the power to form the slurry to be less than the power for forming the second Ar plasma. Further, it is preferred that the time for applying the ith Ar plasma in step S3 is shorter than the application of step S8. The time of the second Ar plasma. For example, in the first IAR plasma treatment in the step S3, it is preferable to apply the Ar plasma for about 3 seconds at a power of 3 〇 () ^. On the other hand, the second Ar in the step S8. In the plasma treatment, it is better to apply Ar at a power of 500 w. The slurry is about 20 seconds. In order to improve the connectivity between the wire* in the wire bonding step of the step S9 after the second Ar plasma processing step and the terminal 3d for wire connection of the package substrate 3, the second core plasma treatment is used. The wire connection terminal 3d is cleaned. However, as the assembly process proceeds, the amount of dirt on the package substrate 3 also increases. Therefore, the second Ar plasma treatment is performed with relatively large energy. On the other hand, in the IAR plasma processing step of the step S3, the package substrate 3 is less contaminated as long as the second plasma treatment has not been performed in the step S8. Therefore, if the first Ar plasma treatment is performed with a large amount of energy, there is a problem that the package substrate 3 is contaminated endlessly. Therefore, in the first Ar plasma treatment in the step S3, it is preferred to apply a plasma treatment such as no energy, which means that the package substrate 3 is cleaned to improve the permeability of the underfill 9 (resin). The minimum energy within the range of degrees. Thereafter, hydrogen combustion (combustion, heat treatment) in step S4 is performed. That is, after the IAR plasma treatment in the step 3, the solder 6 on the plurality of flip chip bonding terminals 3c of the package substrate 3 is subjected to hydrogen combustion using a mixed gas of hydrogen gas and dry air (synthesis gas). Heat treatment to improve the wetness of solder 6 127604.doc -18· 200839908. At this time, the mixing ratio of the hydrogen gas to the dry welding machine and the second rolling is, for example, hydrogen: dry air = 1 · 2. When θ is further "when performing hydrogen combustion", the solder 6 on each of the flip chip bonding terminals 3c is brought into contact with the flame j 4 generated by the combustion of the hydrogen gas and the dry air ventilating body, and is mainly burned off and removed from the solder 6. Organic matter such as carbon, thereby improving the wettability of the bismuth tin 6. In the hydrogen combustion of the present embodiment, as shown in FIG. 6, when hydrogen combustion is performed, 'the fuel 13 that forms the flame 14 for hydrogen combustion and the package substrate 3 are placed 12 to perform hydrogen combustion and n-spray (four). The mask package 12 is interposed between the disk package substrate 3, whereby hydrogen burning is not performed on a portion where gas combustion is not desired, and only chlorine burning is performed on a portion where hydrogen combustion is to be performed. At this time, as shown in FIG. 4 and FIG. 5, the mask 12 is prepared, and the mask 12 is placed on the package substrate 3J to prevent hydrogen combustion, and the opening 12a of the mask 12 is formed to be in the package substrate 3. The shape of the flip chip bonding terminal & is arranged correspondingly. Therefore, when the hydrogen combustion is performed, the flame 14 ejected from the burner 13 can heat only the solder 6 temporarily fixed to the flip chip bonding terminal 3c. The solder 6 is heat-treated, whereby the wettability of the solder 6 can be improved. At this time, the opening portion 12a of the mask 12 is formed into a shape corresponding to the arrangement of the flip-chip bonding terminals of the package substrate 3, and the opening portion The region other than 12a is covered by the mask 12, so that hydrogen burning can be prevented from being performed on the surface of the substrate cleaned by the Ar plasma in the ιαγ plasma processing step of the step S3. Therefore, the first Ar of the step S3 can be prevented. The effect of the plasma treatment is reduced by the hydrogen combustion. Further, the opening portion 12a of the mask 12 is formed into a shape corresponding to the arrangement of the terminals 3c by the flip chip bonding of the package substrate 3, 127604.doc -19·200839908, The area other than the opening i2a is masked 12 Cover, therefore, possible to prevent scorching of the substrate by hydrogen combustion surface (main surface. 3A), or scorch and damage electronic parts mounted on the upper surface of the substrate and so on. Γ

即’本實施形態之氫燃燒之對象僅為封裝基板3上之用 於覆晶接合之焊錫6，於除該以外之不欲加熱之部位（基板 或安裝於基板上之電子零件、以及於第1Ar電漿處理中經 清洗之部位或導線連接用端子3(1等）上配置遮罩12，以不 對該部位加熱，而僅對焊錫6進行加熱。 又，於本實施形態中，當進行氫燃燒時，使形成氫燃燒 用之火焰14之噴燈13於封裝基板3上來回移動複數次:緩 慢地對封裝基板3之焊錫6進行加熱。此時，作為氫燃燒之 受控條件，較好的是以使封裝基板3之表面溫度達到 160〜170 C之方式進行氫燃燒。 例如，將基板與噴燈之間之距離設為7〜16 mm，於將嘴 燈13之火焰14照射至焊錫6之狀態下，使喷燈邮封裝基 板3上來回移動3〜10次，較好的是來回移動$次，藉此使二 裝基板3之表面溫度達到16〇〜17〇。。。其中，基板鱼噴 間之距離及噴燈13之來回移動次數等照射條件係1二一 貝於使封裝基板3之表面溫度達到j My 。 k 4 I。』呀，於昭 射條件下進行氫燃燒。 、…、 如此，以 使封忒基板3之表面溫度達到160〜i7〇t之 進行氫燃燒’藉此可提高焊錫6之_濕性，並且使式 於封裝基板3上來回移動複數次，缓慢地對焊錫6進= 127604.doc -20 - 200839908 熱，藉此，可於下述覆晶接合後之金凸塊5與焊錫6之界面 上形成堅固之合金層。 虱燃燒結束後，進行圖！之步驟85所示之覆晶接合。此 處，如圖7以及圖8所示，將第}半導體晶片i配置於封裝基 板3之主面3a上，其後，對焊錫6進行加熱熔融，連接金凸 鬼/、干錫6，將第1半導體晶片丨覆晶接合於封裝基板3 上，其中上述第1半導體晶片1具有複數個焊點（表面電 極）lc，且於複數個焊點1〇上接合有金凸塊5。此時，如圖 以斤示，例如，於150〜200°C之熱環境15中，一面自晶片側 轭加負載16 ’ 一面進行覆晶接合。此時，用於將負載1 6施 加到第1半導體晶片i上之夾具（未圖示）本身亦具有加熱機 構，並直接地使第丨半導體晶片丨之溫度上升。藉此，熱量 f易傳遞到金凸塊5與焊錫6之接合部，從而可提高接合可 罪〖生此處於對第1半導體晶片1進行加熱之同時施加負 載16之夾具之加熱溫度例如為2〇〇c?c。 再者，於本實施形態中，較好的是於對金凸塊5與焊錫6 進行覆晶接合後’如圖9所示，於金凸塊5與焊錫6之界面 上形成合金層’該合金層之溶點高於封裝安裝時之回流焊 溫度。因封裝安裝時之回流焊溫度(财幻為26〇。。，故於 本貝施形匕、中，例如較好的是形成AuSU2之合金層以。上 述AuSh之合金層6以列如是熔點超過26〇。〇之AuSn合金 層’其溶點為3〇9°C。於本實施形態中，為了形成例如於 半導體封裝裝配後之回流焊時（安裝時）不會於金凸塊5與焊 錫6之界面上形成裂縫之堅固之合金層，於進行氯燃燒 127604.doc -21 - 200839908 時’使喷燈13來回移動複數次，緩慢地對焊錫6進行加 熱。 其結果’藉由氫燃燒後之覆晶接合，可於金凸塊$與焊 錫6之界面上形成熔點超過26〇1之八11811合金層，即形成 AuSn2。此時，使AuSn2之合金層6a之合金寬度（L)例如為 L=22 μπι (MIN)，藉此，可使上述合金寬度穩定化。 如此’以於氫燃燒中，使封裝基板3之表面溫度達到 160〜170C之方式，使喷燈13來回移動複數次緩慢地對焊 錫6進行加熱，其後，藉由覆晶接合，以22 μιη (ΜΙΝ)之合 金寬度，於金凸塊5與焊錫6之界面上形成AuSn2之合金層 6a ’藉此’可提高焊錫6之潤濕性，並且可實現提高了耐 回流焊性以及連接可靠性之金_焊錫連接。 於覆晶接合後，如圖1之步驟S6所示，填充底層填料。 此處，如圖10以及圖n所示，於第i半導體晶片1與封裝基 板3之間、以及第丨半導體晶片丨之周圍填充底層填料％樹 脂）。此時，於連接金凸塊5與焊錫6時之溫度環境中填充 底層填料。 即，於襄配本實施形態之半導體裝置時，於加熱之狀態 下進行覆晶接合，其後，維持上述加熱狀態，並立即填充 底層填料9。即，於與覆晶接合時相同之熱環境15中填充 底層填料9。 ' 藉此，於覆晶接合後，可不自載物台（加熱器）卸下搭載 著第1半導體晶片1之佈線基板3而填充底層填料（樹脂0， 因此’可抑制因熱收縮應力而破壞金-焊錫之連接部之門 127604.doc -22- 200839908 題。 底層填料填充後，進行步驟S7所示之第2層晶片接合。 此處，如圖12以及圖13所示，使第2半導體晶片2之主面以 朝向上方，將該第2半導體晶片2搭載於第1半導體晶片i。 即，經由薄膜狀黏接材料丨丨，將第2半導體晶片2接合於第 1半導體晶片1之背面lb上。此時，第2半導體晶片2與封裝 基板3導線連接，因此，使形成有作為表面電極之焊點2c 之主面2a朝向上方，經由薄膜狀黏接材料丨丨，將背面2b連 接至第1半導體晶片1之背面lb上。 其後，進行步驟S8所示之第2Ar電漿處理。即，將封裝 基板3配置於所需之環境内，於該環境内形成第電漿以 進行第2Ar電漿處理。此時，以比步驟S3之第仏電聚處理 時之處理條件更高之能量進行第2Ar電漿處理。 例如，於步驟S3之第lAr電漿處理中，以3〇〇 w之功率施 加Ar電漿3秒左右，而於步驟％之第2斛電漿處理中，較好 的是以500 w之功率施加Ar電漿2〇秒左右。為了提高步驟 S8之第2Ar電漿處理步驟後之步驟S9之導線接合步驟中之 導線4與封裝基板3之導線連接用端子3(1之連接性，第2心 電漿處理對導線連接用端子3d進行清洗，因此，以比第 lAr電漿處理時之處理條件更高之能量進行&電漿處理。 因此，藉由第2Ar電漿處理，可除去封裝基板3之主面“ 之複數個導線連接用端子（焊接引線）3d表面之污物。 其後，於步驟S9中進行導線接合。即，如圖14以及圖15 所不，藉由導電性之導線4，分別電性連接第2半導體晶片 127604.doc •23- 200839908 2之主面2a之複數個焊點2c、與封裝基板3之主面“之複數 個導線連接用端子3d。 此時，因藉由步驟S8之第2Ar電漿處理對封裝基板3之焊 接引線進行清洗，即對導線連接用端子刊進行清洗，故可 提高導線4與導線連接用端子3d之連接性。 其後，進行步驟S10所示之樹脂密封。即，如圖16所 示，藉由樹脂成形等進行樹脂密封，並於封裝基板3之主 ( 面3a上形成樹脂體10，利用該樹脂體10來密封第】半導體 晶片1、第2半導體晶片2以及複數個導線4等。 之後，進行步驟sii所示之球焊。此時，如圖17所示， 將複數個作為外部端子之焊球8接合於封裝基板3之背面^ 上。 其後，進行步驟S12所示之單片&，並結束作為sip之半 導體封裝7之裝配。 根據本實施形態之半導體裝置之製造方法，藉由使用了 (1氣與乾燥空氣之混合氣體之氫燃燒，對封裝基板3之複 數個覆晶接合用端子3e上之烊錫6進行熱處理，立後，藉 由金-焊錫連接進行覆晶接合，藉此，可除去附著於焊錫: . “上之有機物(碳等)以提高焊錫6之潤濕性，從而，可實 現良好之金-焊錫連接。 又’因並非於覆晶接合後進行助焊劑清洗，而是預先對 封裝基板3上之焊錫6進行燃燒，故可利用金-焊錫連接， 於加熱狀態下進行覆晶接合，其後立即填充底層填料9。 藉此，於填充底層填料9並使覆晶接合部7硬化後恢復至 127604.doc -24 - 200839908 常溫’進行助辉劑清洗’從而，可防止覆晶接合部受到破 壞。 又’於半導體封裝7之裝配步驟之最初，藉由氫燃燒對 封；基板3之複數個覆晶接合用端子上之焊錫6進行熱處 理，藉此，即便對於自外部搬入之封裝基板3，亦可管、理 其電極（覆晶接合用端子3e)上之焊錫6之狀態，從而可提高 產品（半導體封裝7)於裝配時之可靠性。 以上，已根據發明之實施形態，具體地對本發明人之發 月進订了祝明’ f然，本發明並不限定於上述發明之實施 形〜、可於不脫離自身宗旨之範圍内進行各種變更。 例如’於上述實施形態中，對將半導體晶片積層為兩層 之半導體封裝7之情況進行了說明，但上述實施形態之半 導體裝置只要至少具有一個藉由金·焊錫連接之覆晶接合 而安裝於封裝基板3上之半導體晶片，則半導體晶片之積 層數可為2層以上之多層，亦可為僅為 1層之單層。 本lx明適合於利用金_焊錫連接而進行之覆晶接合。 【圖式簡單說明】 圖1係表示本發明實施形態之半導體裝置之製造方法之 一例之製程流程圖。 圖2係表示圖i所示之半導體裝置之製造方法中所使用之 佈線基板之構造之一例之平面圖。 圖3係表不沿著圖2所示之a_a線截斷所得之構造之一例 之剖面圖。 圖4係表示圖丨所示之半導體裝置之製造方法中之氫燃繞 127604.doc -25- 200839908 時之遮罩配置狀態之構造之一例之平面圖。 之一例之剖 圖5係/σ著圖4所示之Α-Α線截斷所得之構造 面圖。 圖6係表示圖1所示丰導體 之午等體表置之製造方法中之氫燃燒 狀悲之一例之概念圖。 圖7係表示圖1所示之半導體裝置之製造方法中之覆晶接 合時之構造之一例之平面圖。That is, the hydrogen burning target of the present embodiment is only the solder 6 for flip chip bonding on the package substrate 3, and the portion to be heated (the substrate or the electronic component mounted on the substrate, and the The mask 12 is placed on the cleaned portion or the wire connection terminal 3 (1, etc.) in the 1A plasma treatment, and the solder 6 is heated without heating the portion. Further, in the present embodiment, hydrogen is performed. During combustion, the burner 13 forming the flame 14 for hydrogen combustion is moved back and forth over the package substrate 3 a plurality of times: the solder 6 of the package substrate 3 is slowly heated. At this time, as a controlled condition of hydrogen combustion, it is preferable. The hydrogen combustion is performed such that the surface temperature of the package substrate 3 reaches 160 to 170 C. For example, the distance between the substrate and the torch is set to 7 to 16 mm, and the flame 14 of the nozzle lamp 13 is irradiated to the solder 6 In the state, the blowtorch package substrate 3 is moved back and forth 3 to 10 times, preferably by moving back and forth for $ times, thereby bringing the surface temperature of the second substrate 3 to 16 〇 17 17 〇. The distance between the spray booth and the back and forth of the burner 13 The irradiation conditions such as the number of times are 1 to 1 such that the surface temperature of the package substrate 3 reaches j My . k 4 I. In the case of hydrogen injection, the hydrogen is burned under the conditions of the squirrel, so that the surface of the substrate 3 is sealed. The temperature reaches 160~i7〇t for hydrogen combustion', thereby increasing the wettability of the solder 6, and moving the pattern back and forth over the package substrate 3 several times, slowly feeding the solder 6 = 127604.doc -20 - 200839908 By heat, a strong alloy layer can be formed on the interface between the gold bumps 5 and the solder 6 after the flip chip bonding. After the combustion is completed, the flip chip bonding shown in the step 85 of Fig. is performed. As shown in FIG. 7 and FIG. 8, the semiconductor wafer i is placed on the main surface 3a of the package substrate 3, and then the solder 6 is heated and melted to connect the gold bump/dry tin 6 to the first The semiconductor wafer is flip-chip bonded to the package substrate 3, wherein the first semiconductor wafer 1 has a plurality of solder joints (surface electrodes) lc, and the gold bumps 5 are bonded to the plurality of solder joints 1〇. The figure is shown in the figure, for example, in a thermal environment 15 of 150 to 200 ° C, one side from the wafer side yoke The flip-chip bonding is performed while the load 16' is applied. At this time, the jig (not shown) for applying the load 16 to the first semiconductor wafer i itself has a heating mechanism, and directly causes the second semiconductor wafer to be bonded. The temperature rises. Thereby, the heat f is easily transmitted to the joint portion of the gold bump 5 and the solder 6, so that the bonding temperature can be improved, and the heating temperature of the jig to which the load 16 is applied while heating the first semiconductor wafer 1 can be increased. For example, it is 2〇〇c?c. Further, in the present embodiment, after the flip-chip bonding of the gold bump 5 and the solder 6 is performed, as shown in FIG. 9, the gold bump 5 and the solder are used. The alloy layer is formed on the interface of 6 'the melting point of the alloy layer is higher than the reflow temperature at the time of package mounting. Because of the reflow soldering temperature during package mounting (the illusion is 26 〇, it is preferable to form the alloy layer of AuSU2 in the form of the present invention. The alloy layer 6 of the above AuSh has a melting point exceeding 26〇. The AuSn alloy layer of 〇 has a melting point of 3〇9° C. In the present embodiment, in order to form, for example, reflow soldering after semiconductor package mounting (when mounted), gold bumps 5 and solder are not formed. A solid alloy layer with cracks formed at the interface of 6 is used to move the burner 13 back and forth a plurality of times during the chlorine combustion 127604.doc -21 - 200839908, and the solder 6 is slowly heated. The result is 'burned by hydrogen The flip chip bonding can form an 1811 alloy layer having a melting point of more than 26〇1 at the interface between the gold bump $ and the solder 6, that is, forming AuSn2. In this case, the alloy width (L) of the alloy layer 6a of AuSn2 is, for example, L=22 μπι (MIN), whereby the width of the above-mentioned alloy can be stabilized. Thus, in the hydrogen combustion, the surface temperature of the package substrate 3 is adjusted to 160 to 170 C, and the burner 13 is moved back and forth a plurality of times. Soldering the solder 6 and thereafter, by flip chip The alloy layer 6a of AuSn2 is formed on the interface between the gold bump 5 and the solder 6 by the width of the alloy of 22 μm (ΜΙΝ), thereby improving the wettability of the solder 6, and improving the reflow-resistant soldering. Gold and solder connection reliability. After the flip chip bonding, as shown in step S6 of Fig. 1, the underfill is filled. Here, as shown in Fig. 10 and Fig. n, the i-th semiconductor wafer 1 and the package The underfill (% resin) is filled between the substrates 3 and around the second semiconductor wafer. At this time, the underfill is filled in a temperature environment in which the gold bump 5 and the solder 6 are connected. In other words, when the semiconductor device of the present embodiment is used, the flip chip bonding is performed in a heated state, and thereafter, the above-described heating state is maintained, and the underfill material 9 is immediately filled. That is, the underfill 9 is filled in the same thermal environment 15 as in the case of flip chip bonding. In this way, after the flip chip bonding, the wiring substrate 3 on which the first semiconductor wafer 1 is mounted can be removed from the stage (heater) to fill the underfill (resin 0, so that it can be suppressed from being destroyed by thermal shrinkage stress) Gate of the gold-solder joint portion 127604.doc -22- 200839908. After the underfill is filled, the second layer wafer bonding shown in step S7 is performed. Here, as shown in FIGS. 12 and 13, the second semiconductor is used. The second semiconductor wafer 2 is mounted on the first semiconductor wafer i with the main surface of the wafer 2 facing upward. That is, the second semiconductor wafer 2 is bonded to the back surface of the first semiconductor wafer 1 via the film-shaped adhesive material 丨丨. In this case, the second semiconductor wafer 2 is connected to the package substrate 3 by a lead wire. Therefore, the main surface 2a on which the solder joint 2c as the surface electrode is formed is directed upward, and the back surface 2b is connected via the film-shaped adhesive material 丨丨. Up to the back surface 1b of the first semiconductor wafer 1. Thereafter, the second Ar plasma treatment shown in step S8 is performed. That is, the package substrate 3 is placed in a desired environment, and a plasma is formed in the environment. 2Ar plasma treatment. At this time, The second Ar plasma treatment is performed on the energy higher than the processing conditions at the second electropolymerization treatment in the step S3. For example, in the first Ar plasma treatment in the step S3, the Ar plasma is applied at a power of 3 〇〇w for 3 seconds. In the second step of the plasma treatment of step %, it is preferred to apply Ar plasma at a power of 500 w for about 2 sec. To increase the wire of step S9 after the second Ar plasma treatment step of step S8 The wire 4 in the bonding step and the terminal 3 for wire connection of the package substrate 3 (the connection property of 1 and the second core plasma treatment are used to clean the terminal 3d for wire connection, and therefore, the processing conditions at the time of processing with the first Ar plasma The higher energy is subjected to & plasma treatment. Therefore, by the second Ar plasma treatment, the dirt on the surface of the plurality of wire connection terminals (welding leads) 3d of the main surface of the package substrate 3 can be removed. Wire bonding is performed in step S9. That is, as shown in FIG. 14 and FIG. 15, the conductive wires 4 are electrically connected to the plurality of main faces 2a of the second semiconductor wafer 127604.doc • 23- 200839908 2 respectively. a plurality of leads of the solder joint 2c and the main surface of the package substrate 3 In this case, the soldering lead of the package substrate 3 is cleaned by the second Ar plasma treatment in step S8, that is, the terminal for wiring connection is cleaned, so that the lead 4 and the terminal for connecting the wire 3d can be improved. Then, the resin is sealed in the step S10. The resin is sealed by resin molding or the like, and the resin body 10 is formed on the main surface 3a of the package substrate 3, as shown in Fig. 16 . The resin body 10 seals the first semiconductor wafer 1, the second semiconductor wafer 2, the plurality of wires 4, and the like. Thereafter, the ball bonding shown in step sii is performed. At this time, as shown in FIG. 17, a plurality of solder balls 8 as external terminals are bonded to the back surface of the package substrate 3. Thereafter, the single piece & shown in step S12 is performed, and the assembly of the semiconductor package 7 as sip is ended. According to the method of manufacturing a semiconductor device of the present embodiment, by using hydrogen combustion of a mixed gas of one gas and dry air, heat treatment is performed on the plurality of tin-plated soldering electrodes 3e on the plurality of flip-chip bonding terminals 3e of the package substrate 3. Thereafter, the flip-chip bonding is performed by a gold-solder connection, whereby the adhesion to the solder can be removed: "The organic substance (carbon or the like) on the upper side improves the wettability of the solder 6, thereby achieving a good gold-solder connection. In addition, since the solder 6 on the package substrate 3 is burned in advance because the flux cleaning is not performed after the flip chip bonding, the gold-solder connection can be used to perform the flip chip bonding in the heated state, and then immediately fill it. The underfill material 9. Thereby, after the underfill material 9 is filled and the flip-chip bonding portion 7 is hardened, it is restored to 127604.doc -24 - 200839908 at room temperature 'cleaning agent cleaning', thereby preventing damage to the flip chip joint portion. At the beginning of the assembly step of the semiconductor package 7, the solder 6 on the plurality of flip chip bonding terminals of the substrate 3 is heat-treated by hydrogen combustion, thereby allowing the package to be carried in from the outside. The plate 3 can also manage the state of the solder 6 on the electrode (the flip-chip bonding terminal 3e), thereby improving the reliability of the product (semiconductor package 7) at the time of assembly. As described above, according to an embodiment of the invention, Specifically, the present invention is not limited to the embodiment of the invention, and various modifications can be made without departing from the scope of the invention. For example, in the above embodiment, The semiconductor package 7 in which the semiconductor wafer is laminated in two layers has been described. However, the semiconductor device of the above embodiment has at least one semiconductor wafer mounted on the package substrate 3 by flip chip bonding by gold-solder connection. The number of layers of the semiconductor wafer may be two or more layers, or may be a single layer of only one layer. This is suitable for flip chip bonding by gold-solder connection. 1 is a process flow diagram showing an example of a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a view showing a method of manufacturing the semiconductor device shown in FIG. Fig. 3 is a cross-sectional view showing an example of a structure which is not cut along the line a_a shown in Fig. 2. Fig. 4 is a view showing hydrogen in the method of manufacturing the semiconductor device shown in Fig. A plan view showing an example of the configuration of the mask arrangement state at the time of 127604.doc -25- 200839908. A sectional view of one example is a structural view obtained by cutting the Α-Α line shown in Fig. 4. Fig. 6 FIG. 7 is a conceptual diagram showing an example of the hydrogen burning behavior in the manufacturing method of the noon body shown in FIG. 1. FIG. 7 is a view showing the flip chip bonding in the manufacturing method of the semiconductor device shown in FIG. A plan view of an example of construction.

ϋ 圖8係沿著圖7所示之Α-Α線截斷所得之構造之一例之剖 面圖。 圖9係模式性地表示圖丨所示之半導體裝置之製造方法 之氫燃燒以及覆晶接合後之覆晶接合部之構造之一 大剖面圖 * 圖10係表示圖1所示之半導體裝置之製造方法中之底戶 填料填充時之構造之一例之平面圖。 一 圖11係表^:沿著圖1G之Α_Α線截斷所得之構造之一例之 剖面圖。 圖12係表示圖i所示之+導體裝置之製造方法中之第2層 晶片接合時之構造之一例之平面圖。 圖13係表m圖i 2之A A線截斷所得之構造之 剖面圖。 圖14係表示圖1所示之半導體裝置之製造方法中之導線 接合時之構造之一例之平面圖。 圖15係表示沿著圖14之八^線截斷所得之構造之一例之 剖面圖。 127604.doc -26- 200839908 回人表下圖1所不之半導體裝置之製造方法中之樹脂 密封後之構造之-例之剖面圖。 /圖係表7F圖！所示之半導體裝置之製造方法♦之球 後之構造之一例之剖面圖。 〆 【主要元件符號說明】 η 1 第1半導體晶片 la 主面 lb 背面 1 c 焊點（表面電極） 2 第2半導體晶片 2a 主面 2b 背面 2c 焊點（表面電極） 3 封裝基板（佈線基板） 3a 主面 3b 背面 3c 覆晶接合用端子 3d 導線連接用端子（焊接引矣 3e 阻焊劑 4 導線 5 金凸塊 6 焊锡 6a AuSn2之合金層 7 半導體封裝（半導體裝置） 127604.doc -27- 200839908 8 焊球 9 底層填料 10 樹脂體 11 薄膜狀黏接材料 12 遮罩 12a 開口部 13 喷燈 14 火焰 15 熱環境 16 負載 127604.doc -28-ϋ Fig. 8 is a cross-sectional view showing an example of a structure obtained by cutting along the Α-Α line shown in Fig. 7. FIG. 9 is a large cross-sectional view schematically showing the structure of the hydrogen-fired and flip-chip bonded portion after the flip-chip bonding in the method of fabricating the semiconductor device shown in FIG. * FIG. 10 is a view showing the semiconductor device shown in FIG. A plan view of an example of a construction when the bottom filler is filled in the manufacturing method. Fig. 11 is a cross-sectional view showing an example of a structure obtained by cutting along the Α_Α line of Fig. 1G. Fig. 12 is a plan view showing an example of a structure at the time of joining a second layer wafer in the method of manufacturing the +conductor device shown in Fig. i. Figure 13 is a cross-sectional view showing the structure obtained by cutting off the A A line of the graph i i. Fig. 14 is a plan view showing an example of a structure at the time of wire bonding in the method of manufacturing the semiconductor device shown in Fig. 1. Fig. 15 is a cross-sectional view showing an example of a structure which is cut along the line VIII of Fig. 14. 127604.doc -26- 200839908 The following is a cross-sectional view of a resin-sealed structure in a method of manufacturing a semiconductor device as shown in FIG. / Figure 7F chart! A cross-sectional view showing an example of the structure of the ball after the manufacturing method of the semiconductor device shown. 〆【Main component symbol description】 η 1 First semiconductor wafer la Main surface lb Back surface 1 c Solder joint (surface electrode) 2 Second semiconductor wafer 2a Main surface 2b Back surface 2c Solder joint (surface electrode) 3 Package substrate (wiring substrate) 3a Main surface 3b Back side 3c Flip chip bonding terminal 3d Wire connection terminal (welding lead 3e Solder resist 4 wire 5 Gold bump 6 Solder 6a Alloy layer of AuSn2 7 Semiconductor package (semiconductor device) 127604.doc -27- 200839908 8 Solder balls 9 Underfill 10 Resin body 11 Film-like bonding material 12 Mask 12a Opening 13 Blowtorch 14 Flame 15 Thermal environment 16 Load 127604.doc -28-

Claims (1)

200839908 十、申請專利範圍： 1· 一種半導體裝置之製造方法，其特徵在於包括下述步 驟： 0)準備於主面上形成有複數個電極且於上述複數個電 _ 極上塗佈有焊錫之佈線基板；（b)使用氫氣與乾燥空氣之 混合氣體，使上述佈線基板之上述複數個電極上之焊錫 燃燒；（c)將具有複數個表面電極且於上述複數個表面電 極上接合有金凸塊之半導體晶片，配置於上述佈線基板 " 之主面上，其後，對上述焊錫進行加熱熔融，連接上述 金凸塊與上述焊錫，將上述半導體晶片覆晶接合於上述 佈線基板上；及（d)於上述半導體晶片與上述佈線基板之 間填充底層填料。 2.如請求項1之半導體裝置之製造方法，其中 於上述（b)步驟中，使遮罩介置於形成燃燒用火焰之噴 燈與上述佈線基板之間，進行氫燃燒。 、 〔3·如請求項1之半導體裝置之製造方法，其中 當於上述（b)步驟中進行燃燒時’使形成燃燒用火焰之 喷燈於上述佈線基板上來回移動複數次，緩慢地加熱上 述佈線基板之焊錫。 4·如請求項1之半導體裝置之製造方法，其中 於上述⑷步驟中之金凸塊-焊錫連接日寺之溫度環境 中，進行上述（d)步驟之底層填料之填充》 5.如請求項1之半導體裝置之製造方法，其申 於連接上述金凸塊與上述焊錫後，於上述金凸塊與上 127604.doc 200839908 述焊锡之界面上形成AuSni以上之合金層。 6·如請求項1之半導體裝置之製造方法，其中 、於連接上述金凸塊與上述焊錫後，於上述金凸塊與上 述焊錫之界面上形成熔點超過26(rC2AuSn合金層。 7·如請求項1之半導體裝置之製造方法，其中 於上述（b)步驟中，藉由燃燒除去附著於上述焊錫上之 石炭。 8. 如請求項1之半導體裝置之製造方法，其中於上述（b)# 驟中以使上述佈線基板之表面溫度達到160〜170°C之 方式進行燃燒。 9. 一種半導體裝置之製造方法，其特徵在於包括下述步 驟： (a)準備於主面上形成有複數個電極且於上述複數個電 極上塗佈有焊錫之佈線基板；⑻將上述佈線基板配置於 所需之環境内，於上述環境内形成第1Ar電漿以除去上 述佈線基板之主面之污物；⑷於上述（b)步驟之後，使用 氫氣與乾燥空氣之混合氣體，使上述佈線基板之上述複 數個電極上之焊錫燃燒；（d)將具有複數個表面電極且於 上述複數個表面電極上接合有金凸塊 配置於上述佈線基板之主面上，其後，對上 加熱熔融，連接上述金凸塊與上述焊錫，將上述第1半 導體晶片覆晶接合於上述佈線基板上；⑷於上述第4 導體晶片與上述佈線基板之間填充底層填料；使第2 半導體晶片之主面朝向上方而搭載^上述第2半導體晶 127604.doc 200839908 片上；（g)將上述佈線基板配置於所需之環境内，於上述 環境内形成第2 Ar電漿以除去上述佈線基板之主面之複 數個焊接引線之污物；及（h)於上述（g)步驟之後，藉由 導電性之導線分別電性連接上述第2半導體晶片之主面 之複數個表面電極、與上述佈線基板之主面之上述複數 個焊接引線。 10.如請求項9之半導體裝置之製造方法，其中 上述（b)步驟之用以形成上述第iAr電漿之輸出小於上 述（g)步驟之用以形成上述第2Ar電漿之輸出。 11·如請求項10之半導體裝置之製造方法，其中 於上述（b)步驟中施加上述第IAr電漿之時間比於上述 (g)步驟中施加上述第2Ar電漿之時間短。 12. 如請求項9之半導體裝置之製造方法，其中 於上述（c)步驟中，使遮罩介於形成燃燒用火焰之喷燈 與上述佈線基板之間，進行氫燃燒。 13. 如請求項9之半導體裝置之製造方法，其中 當於上述（c)步驟中進行燃燒時，使形成燃燒用火焰之 喷燈於上述佈線基板上來回移動複數次，緩慢地加熱上 述佈線基板之焊錫。 14·如請求項9之半導體裝置之製造方法，其中 於上述（c)步驟中，以使上述佈線基板之表面溫度達到 160〜170°C之方式進行上述氫燃燒。 127604.doc200839908 X. Patent application scope: 1. A method for manufacturing a semiconductor device, comprising the steps of: 0) preparing a wiring having a plurality of electrodes formed on a main surface and soldering the plurality of electrodes on the plurality of electrodes a substrate; (b) using a mixed gas of hydrogen and dry air to burn the solder on the plurality of electrodes of the wiring substrate; (c) having a plurality of surface electrodes and bonding gold bumps to the plurality of surface electrodes a semiconductor wafer disposed on a main surface of the wiring substrate, and then heating and melting the solder, connecting the gold bump and the solder, and bonding the semiconductor wafer to the wiring substrate; and d) filling an underfill between the semiconductor wafer and the wiring substrate. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step (b), the mask is placed between the burner for forming a combustion flame and the wiring substrate to perform hydrogen combustion. [3] The method of manufacturing a semiconductor device according to claim 1, wherein when the burning is performed in the step (b), the burner for forming a combustion flame is moved back and forth over the wiring substrate a plurality of times, and the heating is slowly performed. Solder of the wiring board. 4. The method of manufacturing a semiconductor device according to claim 1, wherein in the temperature environment of the gold bump-solder connection of the Japanese temple in the above step (4), the filling of the underfill material in the above step (d) is performed. A method of manufacturing a semiconductor device according to claim 1, wherein after the gold bump and the solder are connected, an alloy layer of AuSni or more is formed on the interface between the gold bump and the solder of the above-mentioned 127604.doc 200839908. 6. The method of manufacturing a semiconductor device according to claim 1, wherein after the gold bump and the solder are connected, a melting point of more than 26 (rC2AuSn alloy layer) is formed at an interface between the gold bump and the solder. The method of manufacturing a semiconductor device according to Item 1, wherein in the step (b), the charcoal attached to the solder is removed by combustion. The method of manufacturing the semiconductor device according to claim 1, wherein the (b)# The combustion is performed so that the surface temperature of the wiring board reaches 160 to 170 ° C. 9. A method of manufacturing a semiconductor device, comprising the steps of: (a) preparing a plurality of main surfaces; And an electrode is coated with a solder wiring substrate on the plurality of electrodes; (8) disposing the wiring substrate in a desired environment, and forming a first Ar plasma in the environment to remove dirt on a main surface of the wiring substrate; (4) after the step (b), using a mixed gas of hydrogen and dry air to burn the solder on the plurality of electrodes of the wiring substrate; (d) having a plurality Each of the plurality of surface electrodes is joined to the plurality of surface electrodes, and gold bumps are bonded to the main surface of the wiring board, and then heated and melted upward to connect the gold bumps and the solder to cover the first semiconductor wafer. (4) filling an underfill material between the fourth conductor wafer and the wiring substrate; and mounting the second semiconductor wafer 127604.doc 200839908 on the main surface of the second semiconductor wafer; (g) disposing the wiring substrate in a desired environment, forming a second Ar plasma in the environment to remove a plurality of soldering leads of the main surface of the wiring substrate; and (h) After the step, the plurality of surface electrodes of the main surface of the second semiconductor wafer and the plurality of soldering leads of the main surface of the wiring substrate are electrically connected to each other by a conductive wire. 10. The semiconductor of claim 9. The manufacturing method of the device, wherein the output of the (i)th step is used to form an output of the ith Ar plasma smaller than the step (g) for forming the output of the second Ar plasma 11. The method of manufacturing a semiconductor device according to claim 10, wherein the time during which the first IAR plasma is applied in the step (b) is shorter than the time during which the second Ar plasma is applied in the step (g). The method of manufacturing a semiconductor device according to claim 9, wherein in the step (c), the mask is interposed between the torch for forming the combustion flame and the wiring substrate to perform hydrogen combustion. 13. The semiconductor of claim 9. In the method of manufacturing the apparatus, when the combustion is performed in the step (c), the burner for forming the combustion flame is moved back and forth over the wiring board a plurality of times to slowly heat the solder of the wiring board. A method of manufacturing a semiconductor device according to claim 9, wherein in the step (c), the hydrogen combustion is performed so that a surface temperature of the wiring substrate reaches 160 to 170 °C. 127604.doc
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