200839849 UMCD-2006-0372 21509twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體元件及其製造方法，且特 ‘ 別是有關於一種半導體元件及選擇性半導體化合物磊曰: 的形成方法。 阳嘴 Λ 【先前技術】 隨著通訊等電子設備發展技術的突飛猛進，電晶體的 • 運作速度勢必越趨快速。然而，因為受限於電子與^洞在 矽中的移動速度，電晶體的應用範圍亦受到限制。 曰習知技術已提出利用矽化鍺(SiGe)磊晶等材料做為電 晶體源極/汲極區的主要組成。與矽的材料特性相比較，= 於鍺具有較大的原子體積，可施予通道一壓縮應力，因此 以矽化鍺形成源極/汲極區可增加電洞的 (mobility) ’進而提升元件的效能。 I階段選擇虹晶成長製程是目前相之形成魏錯 • 層的方式，然而，此種方式仍有些許問題存在。 曰請參照® 1，所示為習知電晶體剖面示意圖。習知電 曰^體的源極/汲減⑽之魏鍺層的形成方法是在間極 V體層1〇4與閘介電層106形成之後，先在基底刚中形 成凹槽12〇 n以SiH4&氣體源進行單pg段選擇性蟲 ^成長製程U ’在成長魏鍺層之前所進行的钱刻製 程或是確保石夕化鍺層品質所進行的清洗製程均會侵钱隔離 結構102之側壁與頂角的絕緣材料。而單階段選擇性石曰 成長所形成的石夕化錯層又無法填補被侵㈣區域，以= 5 200839849 UMCD-2006-0372 21509twf.doc/n 源極/汲極區108與隔離結構102接合處會形成一間隙 110。此間隙110的存在，將會因為後續在源極/沒極區 表面上形成之金屬矽化物的穿透而誘發大量漏電流(large leakage current)以及離子增益衰退(i〇n gain degradation)， 使付電晶體的功效大為降低。 【發明内容】 本發明的目的就是在提供一種選擇性半導體化合物磊 晶層的形成方法，以避免源極/汲極區之半導體化合物層與 隔離結構接合處形成間隙。 本發明的另一目的就是在提供一種半導體元件，其源 極/没極區之半導體化合物層與隔離結構接合處密合，無間 隙存在。 本發明提出一種選擇性半導體化合物磊晶層的形成方 法’此方法是以進行一選擇性半導體化合物磊晶製程，在 基底所裸露的單晶矽區上形成半導體化合物磊晶層。此選 擇性半導體化合物磊晶製程所使用之氣體源包括兩種不同 的含矽氣體源。 依照本發明的較佳實施例所述之選擇性半導體化合 物蟲晶層的形成方法，上述選擇性半導體化合物磊晶製程 為一多階段選擇性半導體化合物磊晶製程，且相鄰兩階段 之選擇性半導體化合物磊晶製程所使用之含矽氣體源不相 同。 依照本發明的較佳實施例所述之選擇性半導體化合 物蠢晶層的形成方法，上述之多階段選擇性半導體化合物 6 200839849 UMCD-2006-0372 21509twf.doc/n 磊晶製程包括一多階段選擇性矽化鍺磊晶製程或是一多階 段選擇性碳化矽磊晶製程。 依照本發明的較佳實施例所述之選擇性半導體化合物 _ 磊晶層的形成方法，上述之多階段選擇性半導體化合物磊 _ 晶製程包括兩階段製程。第一階段選擇性矽化鍺磊晶製 私其所使用之含石夕氣體源為石夕烧(SiH4)，第二階段選擇 性石夕化鍺蟲晶製程，其所使用之含石夕氣體源為二氯石夕曱烧 , (SiH2Cl2)。 依照本發明的較佳實施例所述之選擇性半導體化合 物磊，層的形成方法，上述之第一階段選擇性矽化鍺磊晶 製私疋在第二階段選擇性矽化鍺磊晶製程之前進行。上述 之進行第一階段選擇性矽化鍺磊晶製程的壓力範圍例如是 5至50托，溫度範圍在攝氏550度至750度，如攝氏660 ，，反應氣體例如是SiHU、GeHU與HQ，且SiH4的流量 範圍例如是30至2〇〇sccm，GeH4的流量範圍例如是1〇〇 .至2(^sccm以及HC1的流量範圍例如是8〇至2〇〇sccm。而 進行第二階段選擇性矽化鍺磊晶製程的壓力範圍例如是 10至50托，溫度範圍在攝氏55〇度至75〇度，如攝氏 度；反應氣體例如是SiH2Cl2、GeH4與Ηα，且SiH2Ci2 ，流量範圍例如是40至200sccm，GeH4的流量範圍例如 疋50至250sccm以及HC1的流量範圍例如是8〇至 260sccm。依照本發明的較佳實施例所述之選擇性半導體 化合物磊晶的形成方法，上述之第一階段選擇性矽化鍺磊 晶製程所沈積的半導體化合物磊晶層為多階段選擇性半導 7 200839849 UMCD-2006-0372 2l509twf.doc/n 體化合物轰晶製程所沈積的半導體化合物層之總厚度的 1/3〜5/6 ’例如是500埃至1〇〇〇埃。第二階段選擇性矽化 錯遙晶製程所沈積的半導體化合物層的厚度為100埃至 500 埃。 依照本發明的較佳實施例所述之選擇性半導體化合 物蠢晶層的形成方法，上述之多階段選擇性半導體化合物 蠢晶製程更包括在進行第二階段選擇性矽化鍺磊晶製程之 ^ 行一第三階段選擇性矽化鍺磊晶製程，其所使用之 含f氣，源為SiHU。上述第一階段選擇性矽化鍺磊晶製程 的壓力範圍例如是5至5〇托；溫度範圍在攝氏55〇度至 75〇度，如攝氏660度；反應氣體例如是SiH4、GeH4與 H且她4的流量範圍例如是30至200sccm，GeH4的 :里範圍例如是丨00至2〇〇sccm以及HQ的流量範圍例如 二80#至20〇sccm。而進行第二階段選擇性石夕化錯磊晶製程 壓力軌圍例如是10至50托；溫度範圍在攝氏550度至750 •攝氏660度，反應氣體例如是&Η2α2、GeH4與HC1， f SiHfl2的流量範圍例如是4〇至2〇〇sccm，的流量 fc圍例如疋5G至25Gseem以及HC1的流量範圍例如是8〇 ”6〇sccm。峨行第三階段選擇性石夕化錯遙晶製程的壓 f犯圍例如是5至50托；溫度範圍在攝氏550度至750 又’如攝氏660度；反應氣體例如是SiHU、GeH4盘Ηα， 30 ^2〇〇sccm ? 至200s^m 〇至2〇〇SCCm以及HC1的流量範圍例如是80 8 200839849 UMCD-2006-0372 21509tw£doc/n 依照本發明的較佳實施例所述之選擇性半導體化合 物磊晶層的形成方法，上述之第一階段選擇性矽化鍺磊晶 製程所沈積的矽化鍺磊晶層為多階段選擇性半導體化合物 . 磊晶製程所沈積的矽化鍺磊晶層之總厚度的1/10〜5/8，如 . 10()埃至500埃。第二階段選擇性矽化鍺磊晶製程所沈積 的矽化鍺磊晶層為多階段選擇性半導體化合物磊晶製程所 沈積的石夕化鍺蠢晶層之總厚度的1/6〜5/心如2〇〇埃至5〇〇 丨埃。而第三階段選擇性矽化鍺磊晶製程所沈積的矽化鍺磊 曰曰層為多階段選擇性半導體化合物蟲晶製程所沈積的石夕化 錯遙晶層之總厚度的1/1〇〜5/8，如200埃至500埃。 依,¾本發明的較佳實施例所述之選擇性半導體化合 物磊晶層的形成方法，上述之第一階段選擇性矽化鍺磊晶 製程是在第二階段選擇性矽化鍺磊晶製程之後進行。第一 P白段运擇性石夕化鍺蠢晶製程的壓力範圍例如是$至％托； 溫度範圍在攝氏550度至750度，如攝氏660度，反應氣 體例如是SiHr GeHU與HQ，且SiKU的流量範圍例^是 30至20〇sccm，GeH4的流量範圍例如是1〇〇至2〇〇sccm， 且HC1的流量範圍例如是8〇至2〇〇sccm。而進行第二階段 選擇性矽化鍺磊晶製程的壓力範圍例如是10至5〇托；溫 度範圍在攝氏550度至750度，如攝氏660度，反應氣體 ，如是SiH2Cl2、GeH4與HC1，且SiH2Cl2的流量範^二如 是40至200sccm，GeH4的流量範圍例如是5〇至25〇scc· 而HC1的流量範圍例如是8〇至260sccm。 依照本發明的較佳實施例所述之選擇性半導體化合 9 200839849 UMCD-2006-0372 21509twf.doc/n 物磊晶層的形成方法，上述第一階段選擇性矽化鍺磊晶製 程所沈積的半導體化合物磊晶層的厚度為2〇〇埃至5〇〇 埃，上述之第二階段選擇性矽化鍺磊晶製程所沈積的半導 體化合物蟲晶層為多階段選擇性半導體化合物*晶製程所 沈積的半導體化合物磊晶層之總厚度的1/6〜5/6，如1()〇 埃至1000埃。 依照本發明實施例所述，上述選擇性半導體化合物磊 晶製程所使用之含矽氣體源為兩種不同的含矽氣體之混合 物。此混合物包括SiH4與SiH2Cl2。 口 本發明提出一種半導體元件，此半導體元件包括基 底、隔離結構、摻雜的半導體化合物磊晶層、以及閘極結 構。基底上具有溝渠，隔離結構位於溝渠中，而溝渠定義 出主動區。主動區中又包括一對凹槽。位於凹槽中之摻 雜的半導體化合物磊晶層延伸覆蓋隔離結構的一頂角並定 義為源極/汲極區。而閘極結構位於源極/汲極區之間的主 動區上並且延伸至部分隔離結構上。 依照本發明的較佳實施例所述之半導體元件，上述之 杉才准的半$體化合物包括摻雜的石夕化鍺或是摻雜的碳化 〇 依舨本發明的較佳實施例所述之半導體元件，更包括 一源極/汲極延伸區位於該源極/汲極區與該閘極結構之間 的該基底中。 本發明利用多階段選擇性半導體化合物磊晶製程來形 成源極/汲極區的半導體化合物磊晶層。此製程所形成之半 200839849 UMCD-2006-0372 21509twf.doc/n 導體，合物蟲晶層與隔離結構間之接合處並不會產生間 ，可避免先前因利用單階段選擇性半導i化合物 。日衣程所誘發之大量漏電流現象以及離子增益衰退之問 為讓本發明之上述和其他目的、特徵和優點能更明顯 ^ ’下文特舉較佳實補，並配合所關式，作詳細說 明如下。 【實施方式】 圖2A至圖2D是依照本發明實施例 元件形成方法的流程刮面示意圖。 之牛蛤體 y，’請參照圖2A ’提供一基底2〇〇，此基底細例 如疋早日日碎基底。在基底細中形成溝渠施，並在 Γ二結12G4b，^ _絲區2。2。隔離結 法例如曰化二1如疋絕緣材料’例如是氧化石夕，形成的方 沄例如疋化學氣相沈積法。 胤H於主動區域2〇2内的基底200上形成閘極結構 ^極、、4構206是由閘介電層通與導體層训所組 处’閘極結構206❺形成方法例如是先 =内的基底2⑻上形成1介電材料層（未^ 料層的材質例如是氧化矽。麩 /八十从材 ^導體材料層（未緣示），以覆蓋住整個基;二 導體層训與閘介電層^體材料層與介電材料層，形成 200839849 UMCD-2006-03 72 21509tw£doc/n 然後，睛參照圖2B ’於閘極結構206兩侧形成間隙 壁211。接著’再於間隙壁211兩側的基底2〇〇中形成一 對凹槽212與214。通常，為了確保砍化錯層的品質，在 成長矽化鍺層之前通常會進行清洗製程。而此清洗製程以 及先前凹槽212與214形成之後所進行的蝕刻製程均會侵 蝕隔離結構204b之側壁與頂角，使得隔離結構2〇4b的形 狀改變為如圖所示者。 之，凊參如、圖2C，在進行清洗製程之後，進行本發 明之選擇性半導體化合物磊晶製程，利用不同的含石夕氣體 源，於凹槽212與214中磊晶成長半導體化合物磊晶層例 如是矽化鍺層或是碳化矽層，並在半導體化合物磊晶層中 形成摻雜，以形成源極/汲極區216。依照本發明之選擇性 半導體化合物磊晶製程，源極/汲極區216之半導體化合物 磊晶層會延伸覆蓋至隔離結構2〇4b的頂角230。 之後，凊參照2D，移除間隙壁2Π，再進行離子植入 製程’以在基底200中形成源極/沒極延伸區218。之後， 再於閘極結構206的侧壁再形成另一間隙壁222。在一實 施例中，半導體化合物蠢晶層為石夕化鍺層，選擇性半導體 化合物磊晶製程為多階段選擇性半導體化合物磊晶製程， 其包含二階段選擇性矽化鍺磊晶製程。第一階段選擇性矽 化鍺磊晶製程是以SiH4做為含矽氣體源；第二階段選擇性 石夕化鍺蠢晶製程則是以SiHAl2做為含石夕氣體源。 第一階段選擇性矽化鍺磊晶製程是在壓力範圍例如是 5〜50托；溫度範圍在攝氏55〇度至75〇度，如攝氏66〇度 12 200839849 UMCD-2006-0372 2I509twf.doc/n 之化學氣減積反應室巾進行。反應室巾所通人的反應氣 體源包括SiH4、GeH4與HC1的混合氣體。腿4的流量例 如是介於30至20〇SCCm ; GeH4的流量例如是介於i⑽至 20〇SCCm ; HC1的流量則例如是介於8〇至2〇〇sccm。此階 段選擇性矽化鍺磊晶製程所沈積之矽化鍺磊晶層的厚度為 整個多階段選擇性石夕化鍺磊晶製程所沈積之石夕化錯磊晶層 的總厚度的1/3〜5/6，例如是5〇〇埃至1〇〇〇埃。 在進行第一階段選擇性矽化鍺磊晶成長製程之後，進 行第二階段選擇性矽化鍺磊晶成長製程。此第二階段選擇 性矽化鍺磊晶成長製程係在壓力範圍例如是1〇〜5〇托·，溫 度範圍在攝氏550度至750度，如攝氏660度之化學氣相 沈積反應室中進行。反應室中所通入的反應氣體包括 S^Cl,、GeHU與HC1的混合氣體。SiH2Cl2的流量例如是 介於40至20〇sccm ; GeH4的流量例如是介於5〇至 250sccm ; HC1的流量則例如是介於8〇至26〇sccm。此階 段選擇性矽化鍺磊晶製程所沈積之矽化鍺磊晶層的厚度例 如是100埃至500埃。 在一貫施例中，半導體化合物磊晶層為石夕化鍺層，選 擇性半導體化合物磊晶製程為多階段選擇性半導體化合物 磊晶製程’且其包含三階段選擇性矽化鍺磊晶製程。第一 階段和第三階段選擇性矽化鍺磊晶製程均是以SiH4做為 含矽氣體源；第二階段選擇性矽化鍺磊晶製程則是以 SiHfl2做為含矽氣體源。 第一階段選擇性矽化鍺磊晶製程係在壓力範圍例如是 13 200839849 UMCD-2006-0372 21509twf.doc/n 5〜50托；溫度範圍在攝氏550度至750度，如攝氏660度 之化學氣相沈積反應室中進行。反應室中所通入的反應氣 體包括SiH4、GeHU與HC1的混合氣體。腿4的·流量例如 疋介於30至200sccm ; GeH4的流量例如是介於1〇〇至 200sccm ; HC1的流量則例如是介於⑽至2〇〇sccm。此階 段選擇性矽化鍺磊晶製程所沈積之矽化鍺磊晶層的厚度為 佔整個多階段選擇性矽化鍺磊晶製程所沈積之矽化鍺磊晶 層的總厚度的1/10〜5/8，例如是10〇埃至5〇〇埃。 在進行第一階段選擇性矽化鍺磊晶成長製程之後，進 行弟一階段远擇性石夕化鍺蠢晶成長製程。此製程係在壓力 範圍例如疋10〜50托；溫度範圍在攝氏550度至750度， 如攝氏660度之化學氣相沈積反應室中進行。反應室中所 通入的反應氣體包括SiHbCl2、GeHU與HC1的混合氣體。 sffl^ci2的流量例如是介於40至200sccm ; GeH4的流量例 如是介於50至25〇SCCm ; HC1的流量則例如是介於8〇至 26〇Sccm。此階段選擇性矽化鍺磊晶製程所沈積之矽化鍺 磊晶層的厚度為整個多階段選擇性矽化鍺磊晶製程所沈積 之矽化鍺磊晶層的總厚度的1/6〜5/8，例如是200埃至5〇〇 埃。 、 在進行第二階段選擇性矽化鍺磊晶成長製程之後，進 ^第三階段選擇性矽化鍺磊晶成長製程。此製程係在壓力 範圍例如是5〜50托；溫度範圍在攝氏55〇度至75〇度， 如攝氏660度之化學氣相沈積反應室中進行。反應室中所 通入的反應氣體包括SiKU、GeHU與HC1的混合氣體。SiH4 200839849 UMCD-2006O3 72 21509twf.doc/n200839849 UMCD-2006-0372 21509twf.doc/n IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device and a method of fabricating the same, and particularly to a semiconductor device and a selective semiconductor Compound Lei: The method of formation. Yangzui Λ [Prior Art] With the rapid development of electronic devices such as communication, the operating speed of transistors is bound to become faster. However, because of the limited speed of movement of electrons and holes in the crucible, the application range of the transistor is also limited. It has been proposed to use materials such as bismuth telluride (SiGe) epitaxy as the main component of the source/drain region of the transistor. Compared with the material properties of bismuth, 锗 has a large atomic volume, and can impart a compressive stress to the channel. Therefore, forming a source/drain region with bismuth telluride can increase the mobility' and thus enhance the component. efficacy. The selection of the iridescent growth process in the I stage is currently the way to form the Wei fault layer. However, there are still some problems in this way.参照 Refer to ® 1, which shows a schematic diagram of a conventional transistor. The method of forming the source/decrement (10) of the conventional electrode is to form the groove 12〇n in the substrate just after the formation of the interpole V body layer 1〇4 and the gate dielectric layer 106. The SiH4& gas source is subjected to a single pg segment selective insect growth process. The 'money engraving process performed before the growth of the Wei 锗 layer or the cleaning process performed to ensure the quality of the shi hua hua hua layer will invade the isolation structure 102. Insulation material for sidewalls and corners. However, the Shixia dislocation layer formed by the growth of the single-stage selective dendrite cannot fill the invaded (4) region to = 5 200839849 UMCD-2006-0372 21509twf.doc/n The source/drain region 108 is bonded to the isolation structure 102. A gap 110 is formed at the location. The presence of this gap 110 will induce a large amount of leakage current and ion gain degradation due to the subsequent penetration of the metal telluride formed on the surface of the source/nopole region. The efficacy of the power-on crystal is greatly reduced. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a selective semiconductor compound epitaxial layer to prevent a gap between a semiconductor compound layer of a source/drain region and a spacer structure. Another object of the present invention is to provide a semiconductor device in which a semiconductor compound layer of a source/polar region is adhered to a junction of an isolation structure without a gap. The present invention provides a method of forming an epitaxial layer of a selective semiconductor compound. This method is performed by performing a selective semiconductor compound epitaxial process to form an epitaxial layer of a semiconductor compound on a single crystal germanium region exposed on a substrate. The gas source used in this selective semiconductor compound epitaxial process includes two different sources of helium containing gas. According to a preferred embodiment of the preferred embodiment of the present invention, the selective semiconductor compound epitaxial process is a multi-stage selective semiconductor compound epitaxial process, and the selectivity of two adjacent stages The germanium-containing gas source used in the semiconductor compound epitaxial process is different. The method for forming a selective semiconductor compound stray layer according to the preferred embodiment of the present invention, the multi-stage selective semiconductor compound 6 200839849 UMCD-2006-0372 21509twf.doc/n The epitaxial process includes a multi-stage selection The bismuth telluride epitaxial process or a multi-stage selective carbonization 矽 epitaxial process. According to a preferred embodiment of the preferred embodiment of the present invention, the method of forming an epitaxial layer, the multi-stage selective semiconductor compound epitaxial process comprises a two-stage process. The first stage of selective deuteration 锗 锗 晶 制 其 其 其 其 其 气体 夕 夕 夕 石 石 石 石 石 石 石 石 Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si It is a chlorite, (SiH2Cl2). According to a preferred embodiment of the preferred embodiment of the present invention, a method of forming a layer, the first stage of selective deuteration, is performed prior to the second stage selective deuterium epitaxial process. The pressure range of the first stage selective bismuth telluride epitaxial process described above is, for example, 5 to 50 Torr, the temperature range is 550 to 750 degrees Celsius, such as 660 degrees Celsius, and the reaction gases are, for example, SiHU, GeHU, and HQ, and SiH4. The flow rate range is, for example, 30 to 2 〇〇 sccm, and the flow rate range of GeH4 is, for example, 1 〇〇 to 2 (^sccm and the flow rate range of HC1 is, for example, 8 〇 to 2 〇〇 sccm. The pressure range of the bismuth epitaxial process is, for example, 10 to 50 Torr, and the temperature range is 55 to 75 degrees Celsius, such as Celsius; the reaction gases are, for example, SiH2Cl2, GeH4, and Ηα, and SiH2Ci2, the flow range is, for example, 40 to 200 sccm, The flow rate range of GeH4 is, for example, 疋50 to 250 sccm, and the flow rate of HC1 is, for example, 8 〇 to 260 sccm. The method for forming epitaxial crystal of a selective semiconductor compound according to the preferred embodiment of the present invention, the first stage selective deuteration described above The epitaxial layer of the semiconductor compound deposited by the germanium epitaxial process is a multi-stage selective semiconductor 7 200839849 UMCD-2006-0372 2l509twf.doc/n Total of semiconductor compound layers deposited by the bulk compound crystallizing process 1/3 to 5/6' of the degree is, for example, 500 angstroms to 1 angstrom. The thickness of the semiconductor compound layer deposited by the second-stage selective erbium dislocation process is 100 angstroms to 500 angstroms. In the method for forming a selective semiconductor compound stray layer according to the preferred embodiment, the multi-stage selective semiconductor compound doping process further includes performing a second stage of selective bismuth telluride epitaxial process. Selective bismuth tellurium epitaxial process, the f-containing gas used, the source is SiHU. The pressure range of the first stage selective bismuth telluride epitaxial process is, for example, 5 to 5 Torr; the temperature range is 55 degrees Celsius to 75 degrees, such as 660 degrees Celsius; the reaction gases are, for example, SiH4, GeH4 and H and the flow range of her 4 is, for example, 30 to 200 sccm, and the range of GeH4 is, for example, 丨00 to 2 〇〇sccm and the flow range of HQ, for example Two 80# to 20〇sccm. For the second stage, the selective pressure-deflection process is, for example, 10 to 50 Torr; the temperature ranges from 550 to 750 ° 660 ° C, and the reaction gas is, for example, &;Η2α2, GeH4 and HC1, f SiH The flow rate range of fl2 is, for example, 4 〇 to 2 〇〇 sccm, and the flow rate fc is, for example, 疋5G to 25Gseem, and the flow range of HCl is, for example, 8〇”6〇sccm. The third stage selective 夕 化 化 遥 遥The pressure f of the process is, for example, 5 to 50 Torr; the temperature ranges from 550 to 750 degrees Celsius and 660 degrees Celsius; the reaction gas is, for example, SiHU, GeH4, Ηα, 30^2〇〇sccm ? to 200s^m 〇 The flow range of up to 2〇〇SCCm and HC1 is, for example, 80 8 200839849 UMCD-2006-0372 21509 tw. The method for forming an epitaxial layer of a selective semiconductor compound according to a preferred embodiment of the present invention, the above The bismuth telluride epitaxial layer deposited by the one-stage selective bismuth tellurium epitaxial process is a multi-stage selective semiconductor compound. The total thickness of the bismuth telluride epitaxial layer deposited by the epitaxial process is 1/10~5/8, such as. 10 () angstroms to 500 angstroms. The second stage of the selective bismuth telluride epitaxial process deposited by the bismuth telluride epitaxial layer is a multi-stage selective semiconductor compound epitaxial process deposited by the total thickness of the Shi Xihua 锗 stupid layer 1 / 6 ~ 5 / heart 2 〇〇 to 5 〇〇丨. The third stage of the selective bismuth telluride epitaxial deposition process of the bismuth telluride layer is 1 / 1 〇 ~ 5 of the total thickness of the Shi Xihua faulted crystal layer deposited by the multi-stage selective semiconductor compound process. /8, such as 200 angstroms to 500 angstroms. According to the method for forming a selective semiconductor compound epitaxial layer according to the preferred embodiment of the present invention, the first stage selective bismuth telluride epitaxial process is performed after the second stage selective bismuth telluride epitaxial process . The pressure range of the first P white-segmented Shihuahua sputum crystal process is, for example, $ to % Torr; the temperature ranges from 550 to 750 degrees Celsius, such as 660 degrees Celsius, and the reaction gases are, for example, SiHr GeHU and HQ, and The flow range of the SiKU is 30 to 20 〇 sccm, the flow rate of the GeH 4 is, for example, 1 〇〇 to 2 〇〇 sccm, and the flow rate of the HC 1 is, for example, 8 〇 to 2 〇〇 sccm. The pressure range of the second stage selective bismuth tellurium epitaxial process is, for example, 10 to 5 Torr; the temperature ranges from 550 to 750 degrees Celsius, such as 660 degrees Celsius, and the reaction gases such as SiH2Cl2, GeH4, and HC1, and SiH2Cl2 The flow rate range is 40 to 200 sccm, the flow rate of GeH4 is, for example, 5 〇 to 25 〇 scc· and the flow rate of HC1 is, for example, 8 〇 to 260 sccm. Selective semiconductor compound according to a preferred embodiment of the present invention 9 200839849 UMCD-2006-0372 21509 twf.doc/n method for forming an epitaxial layer, the semiconductor deposited by the first stage selective bismuth telluride epitaxial process The thickness of the epitaxial layer of the compound is 2 Å to 5 Å, and the semiconductor layer of the semiconductor compound deposited by the second stage selective bismuth telluride epitaxial process is deposited by a multi-stage selective semiconductor compound* crystal process. The total thickness of the epitaxial layer of the semiconductor compound is 1/6 to 5/6, such as 1 () 〇 to 1000 Å. According to an embodiment of the invention, the helium-containing gas source used in the selective semiconductor compound epitaxial process is a mixture of two different helium-containing gases. This mixture includes SiH4 and SiH2Cl2. The present invention provides a semiconductor device including a substrate, an isolation structure, a doped semiconductor compound epitaxial layer, and a gate structure. The substrate has a trench, the isolation structure is located in the trench, and the trench defines the active region. The active zone further includes a pair of grooves. The epitaxial layer of the doped semiconductor compound located in the recess extends over an apex angle of the isolation structure and is defined as a source/drain region. The gate structure is located on the active region between the source/drain regions and extends over a portion of the isolation structure. According to the semiconductor device of the preferred embodiment of the present invention, the above-mentioned half-body compound includes doped cerium oxide or doped cerium carbide according to a preferred embodiment of the present invention. The semiconductor component further includes a source/drain extension region in the substrate between the source/drain region and the gate structure. The present invention utilizes a multi-stage selective semiconductor compound epitaxial process to form a semiconductor compound epitaxial layer of source/drain regions. The process formed by this process is a semi-200839849 UMCD-2006-0372 21509twf.doc/n conductor, and the junction between the crystal layer and the isolation structure does not occur, avoiding the previous use of a single-stage selective semiconductor derivative. . The above-mentioned and other objects, features and advantages of the present invention are more apparent in the case of a large amount of leakage current induced by the daily clothing process and the other objects, features and advantages of the present invention. described as follows. [Embodiment] Figs. 2A to 2D are schematic diagrams showing the flow shaving of a component forming method according to an embodiment of the present invention. The calf carcass y, 'please provide a substrate 2' with reference to Fig. 2A', which is, for example, an early base. A ditch is formed in the base fine, and in the second junction 12G4b, ^ _ silk zone 2. 2. The isolation method is, for example, a tantalum insulating material such as ruthenium insulating material, such as oxidized stone, formed by a ruthenium chemical vapor deposition method.胤H forms a gate structure on the substrate 200 in the active region 2〇2, and the structure 206 is formed by the gate dielectric layer and the conductor layer assembly. The gate electrode structure 206 is formed by, for example, first = A dielectric material layer is formed on the substrate 2 (8) (the material of the untreated layer is, for example, yttrium oxide. The bran/eighty material is a conductor material layer (not shown) to cover the entire base; the two conductor layer training and gate The dielectric layer and the dielectric material layer are formed to form a spacer 211 on both sides of the gate structure 206 with reference to FIG. 2B'. Then, the gap is formed on both sides of the gate structure 206. A pair of grooves 212 and 214 are formed in the base 2 两侧 on both sides of the wall 211. Generally, in order to ensure the quality of the cleavage layer, a cleaning process is usually performed before the bismuth layer is grown. The cleaning process and the previous groove are used. The etching process performed after the formation of 212 and 214 both erodes the sidewalls and apex angles of the isolation structure 204b, so that the shape of the isolation structure 2〇4b is changed as shown in the figure. The selective semiconductor compound of the present invention is carried out after the process a crystallizing process, using different gas-bearing gas sources, epitaxially growing a semiconductor compound epitaxial layer in the grooves 212 and 214, such as a germanium telluride layer or a tantalum carbide layer, and forming a doping in the epitaxial layer of the semiconductor compound, To form a source/drain region 216. In accordance with the selective semiconductor compound epitaxial process of the present invention, the epitaxial layer of the semiconductor compound of the source/drain region 216 extends to cover the apex angle 230 of the isolation structure 2〇4b. Referring to 2D, the spacer 2 is removed, and the ion implantation process is performed to form the source/negative extension region 218 in the substrate 200. Thereafter, another spacer is formed on the sidewall of the gate structure 206. 222. In one embodiment, the doped layer of the semiconductor compound is a shi 锗 layer, and the selective semiconductor compound epitaxial process is a multi-stage selective semiconductor compound epitaxial process comprising a two-stage selective bismuth telluride epitaxial process. The first stage of selective bismuth telluride epitaxial process is based on SiH4 as the source of bismuth-containing gas; the second stage of selective 夕 锗 锗 锗 锗 锗 锗 锗 锗 Si Si Si Si Si Si Si Si 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一The plutonium crystallizing process is in the range of pressures of 5 to 50 Torr, for example, the temperature range is 55 to 75 degrees Celsius, such as 66 degrees Celsius 12 200839849 UMCD-2006-0372 2I509twf.doc/n chemical gas depletion The reaction chamber is carried out. The reaction gas source of the reaction chamber includes a mixed gas of SiH4, GeH4 and HC1. The flow rate of the leg 4 is, for example, 30 to 20 〇SCCm; and the flow rate of the GeH4 is, for example, i(10) to 20 〇. The flow rate of HC1 is, for example, 8 〇 to 2 〇〇 sccm. The thickness of the bismuth telluride epitaxial layer deposited by the selective bismuth telluride epitaxial process is the entire multi-stage selective shi 锗 锗 锗 锗 锗 process The total thickness of the deposited smectite layer is 1/3 to 5/6, for example, 5 Å to 1 Å. After the first stage of selective deuteration epitaxial growth process, a second stage selective deuteration epitaxial growth process is performed. The second stage selective bismuth telluride epitaxial growth process is carried out in a chemical vapor deposition reaction chamber having a pressure range of, for example, 1 Torr to 5 Torr, and a temperature ranging from 550 to 750 degrees Celsius, for example, 660 degrees Celsius. The reaction gas introduced into the reaction chamber includes S^Cl, a mixed gas of GeHU and HC1. The flow rate of SiH2Cl2 is, for example, 40 to 20 〇 sccm; the flow rate of GeH4 is, for example, 5 Torr to 250 sccm; and the flow rate of HCl is, for example, 8 〇 to 26 〇 sccm. The thickness of the germanium telluride epitaxial layer deposited by the selective germanium epitaxial process is, for example, 100 angstroms to 500 angstroms. In a consistent application, the epitaxial layer of the semiconductor compound is a shi 锗 layer, and the selective semiconductor compound epitaxial process is a multi-stage selective semiconductor compound epitaxial process' and it comprises a three-stage selective bismuth telluride epitaxial process. The first stage and the third stage of the selective bismuth telluride epitaxial process are both SiH4 as the helium-containing gas source; the second stage selective bismuth telluride epitaxial process is based on SiHfl2 as the helium-containing gas source. The first stage selective bismuth telluride epitaxial process is in the range of pressures such as 13 200839849 UMCD-2006-0372 21509twf.doc/n 5~50 Torr; temperature range is 550 degrees Celsius to 750 degrees Celsius, such as 660 degrees Celsius The phase deposition reaction chamber is carried out. The reaction gas introduced into the reaction chamber includes a mixed gas of SiH4, GeHU and HCl. The flow rate of the leg 4 is, for example, 30 to 200 sccm; the flow rate of GeH4 is, for example, 1 to 200 sccm; and the flow rate of HC1 is, for example, between (10) and 2 〇〇 sccm. At this stage, the thickness of the germanium telluride epitaxial layer deposited by the selective germanium germanium epitaxial process is 1/10~5/8 of the total thickness of the germanium telluride epitaxial layer deposited by the entire multi-stage selective germanium germanium epitaxial process. For example, it is 10 angstroms to 5 angstroms. After the first stage of selective bismuth 锗 锗 锗 成长 成长 成长 成长 锗 , , 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The process is carried out in a chemical vapor deposition reaction chamber having a pressure range of, for example, 10 to 50 Torr; and a temperature ranging from 550 to 750 degrees Celsius, for example, 660 degrees Celsius. The reaction gas introduced into the reaction chamber includes a mixed gas of SiHbCl2, GeHU and HCl. The flow rate of sffl^ci2 is, for example, 40 to 200 sccm; the flow rate of GeH4 is, for example, 50 to 25 〇 SCCm; and the flow rate of HC1 is, for example, 8 〇 to 26 〇 Sccm. The thickness of the bismuth telluride epitaxial layer deposited by the selective bismuth telluride epitaxial process at this stage is 1/6 to 5/8 of the total thickness of the bismuth telluride epitaxial layer deposited by the entire multi-stage selective bismuth telluride epitaxial process. For example, it is 200 angstroms to 5 angstroms. After the second stage of selective bismuth bismuth epitaxial growth process, the third stage is selectively enthalpy 锗 锗 epitaxial growth process. The process is carried out in a pressure range of, for example, 5 to 50 Torr; and in a chemical vapor deposition reaction chamber at a temperature ranging from 55 to 75 degrees Celsius, for example, 660 degrees Celsius. The reaction gas introduced into the reaction chamber includes a mixed gas of SiKU, GeHU and HCl. SiH4 200839849 UMCD-2006O3 72 21509twf.doc/n
的流量例如是介於30至200sccm ; GeEU的流量例如是介 於100至200sccm ; HC1的流量則例如是介於⑽至 20〇SCCm。此階段選擇性矽化鍺磊晶製程所沈積之砍化鍺 遙晶層的厚度為整個多階段選擇性矽化鍺磊晶製程所沈積 之矽化鍺磊晶層的總厚度例如是1/1〇〜5/8，例如是100埃 至500埃。 N 在另一個實施例中’選擇性半導體化合物蠢晶製程為 多階段選擇性半導體化合物磊晶製程，其多階段選擇性半 導體化合物磊晶製程可包含三階段以上的選擇性矽化鍺蠢 晶製程。 在另一實施例中，半導體化合物磊晶層為矽化鍺層， 上述選擇性半導體化合物蟲晶製程為多階段選擇性半導體 化合物磊晶製程，其包含二階段選擇性矽化鍺磊晶製程。 第一階段選擇性矽化鍺磊晶製程是以SiH2Cl2做為含石夕氣 體源；第二階段選擇性矽化鍺磊晶製程則是以⑴私做為含 矽氣體源。第一階段選擇性矽化鍺磊晶製程係在壓力範圍 例如是10〜50托；溫度範圍在攝氏550度至75〇度，如攝 氏660度之化學氣相沈積反應室中進行。反應室中所通入 的反應氣體通入包括SiE^Cl2、GeH4與HC1的混合氣體。 SiH^Cl2的流量例如是介於40至200sccm ; GeH4的流量例 如是介於50至250sccm ; HC1的流量則例如是介於8〇至 260sccm。此階段選擇性矽化鍺磊晶製程所沈積之矽化鍺 磊晶層的厚度是整個多階段選擇性矽化鍺磊晶製程所沈積 之石夕化鍺蠢晶層的總厚度的1/6〜5/6，例如是2〇〇埃至500 15 200839849 UMCD-2006-03 72 21509tw£doc/n 埃。 在進行第一階段選擇性矽化鍺磊晶成長製程之後，進 行第二階段選擇性矽化鍺磊晶成長製程。此製程係在壓力 範圍例如是5〜50托；溫度範圍在攝氏550度至750度， 如攝氏660度之化學氣相沈積反應室中進行。反應室中所 通入的反應氣體包括SiH4、GeH4與HC1的混合氣體。SiH4 的流量例如是介於30至200sccm ; GeELt的流量例如是介 於100至200sccm ; HC1的流量則例如是介於⑽至 200sCCm。此階段選擇性矽化鍺磊晶製程所沈積之石夕化錯 遙晶層的厚度例如是100埃至1000埃。 在又一實施例中，半導體化合物蠢晶層為石夕化鍺層， 上述選擇性半導體化合物磊晶製程所使用之含矽氣體源是 兩種不同的含矽氣體之混合物。此混合物包括SiH4與 SiHfl2。例如，上述選擇性半導體化合物磊晶製程為一單 階段選擇性矽化鍺磊晶製程，其製程是在壓力範圍例如是 10至50耗；溫度範圍在攝氏550度至750度，如攝氏660 度之化學氣相沈積反應室中進行。反應室中所通入的反應 氣體包括SiH4、SiH2Cl2、GeH4與HC1的混合氣體。SiH4 的流量例如是介於40至200sccm，如60sccm ; SiH2Cl2的 ⑺l i例如是介於4〇至200sccm，如95sccm ; GeH4的流量 例如是介於200至550sccm，如390sccm; HC1的流量則例 如疋介於80至260sccm，如160sccm。所通入的摻雜氣體 爛的流量例如是介於100至300sccm，如240sccm。 以上之實施例，是以先形成源極/汲極區216再形成源 16 200839849 UMCD-2006-0372 21509twf.doc/n 極/没極延伸區218來說明之。然而，在實際的應用時，其 製程順序可以依照實際的情況加以變化。例如，在另一實 施例中，上述之源極/汲極延伸區218也可以在閘極結構 - 206形成之後，間隙壁211形成之前來形成之。本發明選 擇性半導體化合物磊晶製程利用兩種不同的含矽氣體源做 為反應氣體來形成矽化鍺層，用以做為源極/汲極區的主要 材料。以SiHU做為含矽氣體源，其具有較好的吸附特性， 可以減少微負載效應(micro_l〇ading effect)。而以SiH2Cl2 做為含矽氣體源，其具有較佳的侧向成長特性，可以覆蓋2 隔離結構頂端。取兩種氣體的優點，適當的搭配使用，可 以將微負載效應由28%下降至14%且可以使得所形成之 矽化鍺層與隔離結構間的接合面不會產生間隙，且所形成 的矽^鍺層可以延伸覆蓋隔離結構之頂角。是故，先前因 2用單階段單種切氣體輯行選擇性半導體化合物屋晶 製程所誘發之大量漏電流以及離子增益衰退現象將獲得改 善，元件的效能也因此獲得提升。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 =範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1是繪不為習知之電晶體剖面示意圖。 圖2A至2D是依照本發明實施例所繪示之半導體元 件形成方法的流程剖面示意圖。 17 200839849 UMCD-2006-0372 21509twf.doc/n 【主要元件符號說明】 100 :基底 102 :隔離結構 104 :閘極導體層 106 :閘介電層 108 :源極/汲極區 110 :間隙 120 ··凹槽 200 :基底 202 ·主動區 204a :溝渠 204b :隔離結構 206 :閘極結構 208 :閘介電層 210 :導體層 211、 222 :間隙壁 212、 214 :凹槽 216 :源極/没極區 218 :源極/汲極延伸區 230 :頂角 18The flow rate is, for example, 30 to 200 sccm; the flow rate of GeEU is, for example, 100 to 200 sccm; and the flow rate of HC1 is, for example, between (10) and 20 〇 SCCm. The thickness of the cleavage layer of the deuterated layer deposited by the selective bismuth telluride epitaxial process is the total thickness of the bismuth telluride epitaxial layer deposited by the entire multi-stage selective bismuth telluride epitaxial process, for example, 1/1 〇 〜 5 /8, for example, 100 angstroms to 500 angstroms. N In another embodiment, the selective semiconductor compound doping process is a multi-stage selective semiconductor compound epitaxial process, and the multi-stage selective semiconductor compound epitaxial process may comprise a three-stage or more selective bismuth oxide process. In another embodiment, the epitaxial layer of the semiconductor compound is a germanium telluride layer, and the selective semiconductor compound crystallite process is a multi-stage selective semiconductor compound epitaxial process comprising a two-stage selective germanium telluride epitaxial process. The first stage of selective bismuth telluride epitaxial process is based on SiH2Cl2 as the source of gas-bearing gas; the second stage of selective bismuth telluride is based on (1) private use as a gas source containing helium. The first stage selective bismuth telluride epitaxial process is carried out in a pressure range of, for example, 10 to 50 Torr; and a temperature range of 550 to 75 degrees Celsius, for example, a chemical vapor deposition reaction chamber of 660 degrees Celsius. The reaction gas introduced into the reaction chamber is passed through a mixed gas including SiE^Cl2, GeH4, and HCl. The flow rate of SiH^Cl2 is, for example, 40 to 200 sccm; the flow rate of GeH4 is, for example, 50 to 250 sccm; and the flow rate of HC1 is, for example, 8 to 260 sccm. The thickness of the bismuth telluride epitaxial layer deposited by the selective bismuth tellurium epitaxial process at this stage is 1/6 to 5/ of the total thickness of the stray layer of the shi huahua 沉积 deposited by the entire multi-stage selective bismuth telluride epitaxial process. 6, for example, 2 〇〇 to 500 15 200839849 UMCD-2006-03 72 21509tw£doc/n 埃. After the first stage of selective deuteration epitaxial growth process, a second stage selective deuteration epitaxial growth process is performed. The process is carried out in a chemical vapor deposition reaction chamber having a pressure range of, for example, 5 to 50 Torr and a temperature ranging from 550 to 750 degrees Celsius, for example, 660 degrees Celsius. The reaction gas introduced into the reaction chamber includes a mixed gas of SiH4, GeH4 and HCl. The flow rate of SiH4 is, for example, 30 to 200 sccm; the flow rate of GeELt is, for example, 100 to 200 sccm; and the flow rate of HC1 is, for example, (10) to 200 sCCm. The thickness of the smectite layer deposited by the selective bismuth telluride epitaxial process at this stage is, for example, 100 angstroms to 1000 angstroms. In still another embodiment, the doping layer of the semiconductor compound is a layer of a cerium oxide, and the source of the cerium-containing gas used in the epitaxial process of the selective semiconductor compound is a mixture of two different cerium-containing gases. This mixture includes SiH4 and SiHfl2. For example, the selective semiconductor compound epitaxial process is a single-stage selective bismuth telluride epitaxial process, the process of which is, for example, 10 to 50 watts in a pressure range; and the temperature range is 550 to 750 degrees Celsius, such as 660 degrees Celsius. The chemical vapor deposition reaction chamber is carried out. The reaction gas introduced into the reaction chamber includes a mixed gas of SiH4, SiH2Cl2, GeH4 and HCl. The flow rate of SiH4 is, for example, 40 to 200 sccm, such as 60 sccm; the (7) l i of SiH 2 Cl 2 is, for example, 4 to 200 sccm, such as 95 sccm; the flow rate of GeH 4 is, for example, 200 to 550 sccm, such as 390 sccm; the flow rate of HC1 is, for example, 疋Between 80 and 260 sccm, such as 160 sccm. The flow rate of the doped gas that is introduced is, for example, between 100 and 300 sccm, such as 240 sccm. The above embodiment is described by first forming the source/drain region 216 and then forming the source 16 200839849 UMCD-2006-0372 21509 twf.doc/n pole/pole extension 218. However, in actual applications, the order of the processes can be changed according to the actual situation. For example, in another embodiment, the source/drain extensions 218 described above may also be formed prior to the formation of the gate structure 208, before the spacers 211 are formed. The selective semiconductor compound epitaxial process of the present invention utilizes two different helium-containing gas sources as reactive gases to form a germanium telluride layer for use as a source material for the source/drain regions. SiHU is used as a helium-containing gas source, which has good adsorption characteristics and can reduce the micro_l〇ading effect. SiH2Cl2 is used as a helium-containing gas source, which has better lateral growth characteristics and can cover the top of the 2 isolation structure. Take advantage of the two gases, the appropriate combination can reduce the micro-loading effect from 28% to 14% and can make the joint between the formed bismuth telluride layer and the isolation structure without gaps, and the formed 矽The 锗 layer can extend over the top corner of the isolation structure. Therefore, the large amount of leakage current and ion gain decay induced by the selective semiconductor compound house process using a single-stage single-cut gas can be improved, and the performance of the device is improved. While the present invention has been described above in terms of the preferred embodiments thereof, it is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view of a transistor which is not conventionally known. 2A through 2D are schematic cross-sectional views showing a process of forming a semiconductor device in accordance with an embodiment of the present invention. 17 200839849 UMCD-2006-0372 21509twf.doc/n [Description of main component symbols] 100: Substrate 102: isolation structure 104: gate conductor layer 106: gate dielectric layer 108: source/drain region 110: gap 120 · Groove 200: substrate 202 · active region 204a: trench 204b: isolation structure 206: gate structure 208: gate dielectric layer 210: conductor layer 211, 222: spacers 212, 214: recess 216: source / no Polar region 218: source/drain extension 230: apex angle 18