TW200836200A - Control method and memory cell utilizing the same - Google Patents

Abstract

A control method for a memory cell including a base, a source, a drain, a floating gate, and a control gate. In a specific mode, a negative polarity voltage is provided to the base, a grounding voltage is provided to the source, a positive polarity voltage to the drain, and the control gate is electrically floating.

Description

200836200 IX. Description of the Invention: [Technical Field] The present invention relates to a control method and a memory cell, and more particularly to a control method and memory cell for improving excessive erasing. [Previous technology #f] Non-volatile memory is a kind of semiconductor memory whose memory data is not lost with power off. It can be roughly classified into read only memory (ROM), erasable and stylized. Erasable programmable read only memory (EPROM) and electronic erasable programmable read only memory (EEPROM) 〇 both EPROM and EEPROM electronically write signals. The EPROM erases the data by illuminating the ultraviolet light. The EEPROM erases the data electronically, and the flash EEPROM electronically erases all or one of the EEPROMs in a region. For the sake of convenience, it is collectively referred to as EPROM. The stylization and erasing methods of the conventional EPROM are described below. In stylization, the channel hot electron effect is mainly achieved by using a channel hot electron effect, that is, using a voltage difference between the positive voltage coupled to the floating gate and the channel below it to establish an electric field of sufficient strength. The electrons acquire sufficient kinetic energy (ie, hot electrons) to penetrate the oxide layer, causing it to be trapped in the floating gate. Specifically, due to the presence of electrons in the floating gate,

Client's Docket No.: 95-025 TT^ Docket No:0492-A41052-TW/Final /Joanne 200836200 The shirt is ringing to the conduction of the channel below it, so you can use the method of injecting electrons into the floating gate. Each memory unit is programmed to store different states of "1" or "storage" 0. In the EPROM, the charging process of feeding a charged carrier into the floating gate and trapping the charged carrier in the floating gate Called the programming process, the process of moving a charged carrier out of a floating gate is called an erasing process. The erasing process is mainly achieved by the Flowler-Nordheim tunneling effect (F-N tunneling effect). That is, a large negative voltage is applied to the control gate, and the electrons in the floating gate are tunneled through the dielectric layer through the coupling of the dielectric layer, and are released through the lower channel or the source region. However, the EPROM often has a problem of so-called over-wiping (〇ver_erase) after erasing. SUMMARY OF THE INVENTION The present invention provides a control method suitable for a memory cell having a substrate and a source. a drain gate, a floating gate, and a control gate. When entering a specific mode, providing a negative voltage to the substrate, providing a ground voltage to the source, providing a positive voltage to the drain, and controlling The electrical property of the gate is a floating state. The invention further provides a memory cell comprising a substrate, a source, a drain, a floating gate and a control gate. The source and the drain are formed in the substrate. The gate is formed on the substrate. The control gate is formed on the floating idler. When entering a specific mode, the substrate receives a negative voltage, the source receives a ground voltage, and the drain receives a positive voltage. pole

Client’s Docket No. : 95-025 TT^ Docket No:0492-A41052-TW/Final /Joanne 200836200 The electrical properties are floating. The above and other objects, features and advantages of the present invention will become more <RTIgt; Schematic diagram of the cell. The memory cell 100 includes a substrate 110, a source 120, a drain 13A, a floating gate 14A, a control gate 150, and an electrical layer 160 and 170. In the present embodiment, the substrate ι1 〇 is p-type, and the source 120 and the drain 13 〇 are both N+ diffusion regions. In other embodiments, the substrate 110 can be N-type, and the source 120 and the drain 13 are both P+ diffusion regions. The source 120 and the drain 130 are formed in the substrate 11 , wherein the drain 130 is a bit line. A floating gate 14 is formed on the substrate 11A. The dielectric layer 160 is interposed between the substrate 11 〇 and the floating gate 14 。. Control gate 150 is formed over floating gate 14A. The dielectric layer 17 is interposed between the floating gate 140 and the control gate 150. ... When entering a specific mode, the substrate 11〇 of the memory cell receives the negative voltage -V, the source 120 receives the ground voltage GND, the drain 13 receives the positive voltage +V, and the control gate 15 does not. Receive any voltage, so its electrical properties are floating. Since the memory cells are easily erased after being erased, the threshold voltage of the memory cells is too low. When the threshold voltage of the memory cell is too low, after the stylization process, the critical voltage of the memory cell cannot be raised to the desired voltage value.

For example, the 'hypothesis' is that the threshold voltage of the memory cell is equal to 〇V±〇.5V.

Client's Docket No.: 95-025 TT's Docket N〇:0492-A41052-TW/Final /Joanne 200836200, indicating that the data "0" is stored. When the threshold voltage of the memory cell is equal to 2V±0.5V, it means that the data is stored. ". When the data stored in the memory cell is to be changed from "1" to "0", the memory cell needs to be erased. If excessive erasure occurs, the threshold voltage of the memory cell may be less than -0.5V. If the data stored in the memory cell is changed from "0" to "1", the threshold voltage will be less than 1.5 V after the memory cell is programmed. Therefore, it is easy to misjudge the poor material stored in the memory cell as the data "〇". In this embodiment, when the threshold voltage of the memory cell is less than a predetermined value, the specific mode is entered, and the voltage is supplied to the memory cell in a specific manner to increase the threshold voltage of the memory cell to avoid being unable to be programmed. Raise the threshold voltage of the memory cell to the standard value. In other embodiments, the particular mode can be entered after the memory cell has been erased. When the substrate 110 receives the negative polarity voltage -V, the source 120 receives the ground voltage GND, the drain 130 receives the positive polarity voltage +V, and the control gate 150 does not receive any voltage, since the electrical conductivity of the control gate 150 is floating, Therefore, it is susceptible to the bungee pole 130 and has a small amount of positive polarity voltage, so the threshold voltage of the memory cell 100 can be slightly increased to avoid stylized errors caused by excessive erasing. In the manufacturing process of the memory, the reference memory cell can be set, and the threshold voltage is a preset value for comparison with other memory cells. When the threshold voltage of the memory cell 100 is less than the threshold voltage of the reference memory cell, it means that the threshold voltage of the memory cell 100 is too low, so it is necessary to enter a specific mode to adjust the threshold voltage of the memory cell 100. When the threshold voltage of the memory cell 100 is adjusted

Client's Docket No.: 95-025 TT?s Docket No: 0492-A41052-TW/Final /Joanne 200836200 The material provides any bias to the memory cell 100. ^2® is the adjusted threshold voltage of the memory cell. Curve 22 is the memory cell boundary voltage using the bias mode of the handle 1. Curve 24: The threshold voltage of the memory cell using the white balance (for example, Dahc). Since curves 22 and 24 are the average of the threshold voltages of 25 memory cells, they have a relatively high accuracy. As shown in the figure, the initial threshold voltage of the memory cell is about 1.9V. When L1 receives the bias voltage as described in this section, its threshold voltage will rapidly increase at daytime T1, and its threshold voltage can be increased to about 2.3V, which is 0.4V more than the initial value. In contrast, curve 24, at time T1, the B-line voltage of the memory cell using the prior art is about 1.95V, which only slightly increases 〇5V. At time T2, as can be seen from curve 24, the threshold voltage of the memory cell of the prior art is about 2.05 V' and is only o.uv more than the initial value. Therefore, the bias mode disclosed in the present invention can quickly and greatly increase the threshold voltage of the memory cell, and greatly reduce the misreading phenomenon caused by the stylization. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. 1 [Simplified description of the drawings] Fig. 1 is a schematic diagram of a memory cell of the present invention.

Client’s Docket Ν〇.:95-025 TT?s Docket No:0492-A41052-TW/Final /Joanne 200836200 Figure 2 shows the adjusted threshold voltage of the memory cell. [Main component symbol description] 100: memory cell; 110: substrate; 120: source; 130: drain; 140 • floating gate; 150: control gate; 160, 170: dielectric layer; Curve〇

Client’s Docket N〇.:95-025 TT’s Docket No:0492-A41052-TW/Final /Joanne

Claims (1)

200836200 X. Patent application scope: t'Applicable to - (4) 'The memory cell has - a base, a source control method, including · and a pole, a floating gate and a control gate, which provides a specific mode, Providing - the substrate, M, grounding power is repeatedly applied to the source, providing a positive polarity and making the electrical properties of the control idler floating. The control method according to claim 1, wherein when the threshold voltage of the 圮fe cell is less than a predetermined value, the specific mode is entered. 3. The control method according to claim 1, wherein the memory cell enters the specific mode after performing an erasing operation. 4. The control method of claim 1, further comprising: providing a reference memory cell; comparing a threshold voltage of the memory cell with the reference memory cell; and when the threshold voltage of the memory cell is less than the reference memory cell The threshold voltage enters this particular mode. 5. A memory cell comprising: a substrate; a source 'formed in the substrate; a finite electrode formed in the substrate; a floating gate formed over the substrate; and a control gate, Formed on the floating gate; wherein, when entering a specific mode, the substrate receives a negative voltage, the source receives a ground voltage, and the pole receives a positive voltage, the Client's Docket No.: 95- 025 TT?s Docket No:0492-A41052-TW/Final /Joanne 11 200836200 The electrical conductivity of the gate is floating. 6. The memory cell of claim 5, wherein the substrate is P-type, and the source and the drain are both N-type. 7. The memory cell of claim 5, wherein the substrate is N-type, and the source and the drain are both P-type. 8. The memory cell of claim 5, wherein the bungee is a one-dimensional line. 9. The memory cell of claim 5, wherein the specific mode is that the threshold voltage of the memory cell is less than a predetermined value. 10. The memory cell of claim 5, wherein the specific mode occurs after the memory cell performs an erase operation. Client’s Docket No. :95-025 TT’s Docket N〇:0492-A41052-TW/Final /Joanne