TW200832411A - System and method for programming non-volatile memory with improved boosting - Google Patents

Abstract

Non-volatile storage elements are programmed in a manner that reduces program disturb, particularly at the edges storage elements strings, by using modified pass voltages. In particular, during the programming of a selected storage element, an isolation voltage is applied to a storage element proximate to the selected storage element thereby electrically dividing the channel associated with the storage elements into two isolated areas. Additional isolated areas are formed remotely from the selected storage element by applying the isolation voltage to other remote storage elements. The isolated channel regions associated with the storage elements are then boosted with different pass voltages in order to alleviate the effects of program disturb. Thus, a standard pass voltage is applied to storage elements immediately adjacent to the selected storage element, and a lower pass voltage is applied to storage elements remote from the selected storage element. In one preferred embodiment, a higher pass voltage is applied to storage elements immediately adjacent the selected storage element on the side having previously programmed storage elements. These techniques reduce the leakage of charge from adjacent boosted channel regions caused by gate induced drain leakage at the source select line and the drain select line, as well as from isolation word lines, thereby reducing program disturb effects.

Description

200832411 IX. INSTRUCTIONS: TECHNICAL FIELD OF THE INVENTION The present disclosure relates to stylized non-volatile memory and, more specifically, to techniques for reducing stylized interference effects during stylization. [Prior Art] Various electronic devices. Example Semiconductor memory has become more and more popular

For example, non-volatile semiconductor memory systems are used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, inactive computing devices, and other devices. Electrical τ erasing programmable epexes and flash memory systems are among the most common non-volatile semiconductor memories. The EEPROM type can be compared to a traditional and fully featured EEPROM. 'Using flash memory (which is also used in one step to erase the entire memory array or the EEPRQM and flash memory will be used - a transistor structure with floating closed poles, the (4) questioning system is located in - semiconductor Above and insulating the channel region in the substrate, and between the source region and the drain region. - The control gate is disposed above the floating gate and floats with the floating gate. The amount of charge on the floating gate can be controlled = this = the criticality of the formed transistor. That is, when the transistor is turned on: the employee applies a minimum amount of voltage at the gate of the control gate to allow: hunting by the float The level of the charge on the gate controls the source and the drain, and each erased gate can be used to store two ranges of charge, which can be 1 t 9 /, There are two possible states, for example, I23781.doc 200832411 state and stylized state. This flash memory device is sometimes called two soldiers: memory device 'because each memory component can store one bit Capital

A _- multi-state or multi-bit quasi-flash memory device is implemented by identifying a multi-mode/validized programmed threshold voltage range. Each of the different threshold voltage ranges will correspond to the coded data bits in the memory device - the job value of the group. For example, # this component can be placed in the corresponding =: a range of four discrete charge bands of different threshold voltages - in which: the mother storage component can store two bits of data. In general, during the -programming process, the control gate of the voltage component is programmed as a series of pulses whose amplitude will be applied over time. In a feasible manner, the pulses will increase by a predetermined step A, v Pgni with each successive pulse, for example "'0.2 W. During the period between the stylized pulses, Verification is performed. That is, the stylized levels of each of the components to be parallelized are read between successive stylized pulses and compared to the verify level. The verification level indicates the state to be stylized. For a multi-state flash memory component array: and: a verification step can be performed for each state of a component to determine a number of Xs. Whether the verification level associated with the poor material has been reached. For example, a multi-state memory component capable of storing data in four states may need to perform verification operations for three comparison points. - EEPR0M or a flash memory device (such as a NAND flash memory device in a NAND string), usually applying 123781.doc 200832411 to the control gate and grounding the bit line, thereby Electricity of the channel of the memory component a sub-portion is injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory element rises to facilitate the memory element Considered to be in a stylized state. Under the heading "S〇UrCe Side Self Boosting

Techniques for Non-Volatile Memory, U.S. Patent No. 6,859,397, and U.S. Patent Application Publication No. 2,5/24,939, entitled " Detecting 〇ver programmed Mem〇ry" More information, both of which are incorporated herein by reference. During the programming of a selected memory component, adjacent memory may be inadvertently programmed in a program called stylized interference. For example, when vpgm is applied to a word line, it may be inadvertently stylized - it does not want to be shouted but is the same as a memory element selected for simplification. The memory element on the meta-line can use several techniques to prevent stylized interference. For example, self-boosting (SB) can electrically isolate the channel associated with the unselected bit line and will The conduction voltage (eg Η) V) is applied to the "unselected word line. The unselected word lines meet to the channel associated with the unselected bit lines' such that a voltage (eg, 8V) is present in the channels of the unselected bit lines It will tend to reduce this stylized interference effect. Therefore, the self-boosting technique causes a voltage boost to be present in the channel, which tends to reduce the voltage differential across the pass-through oxide and thus reduce the stylized interference effect. In addition, 'other modified techniques (such as local auto-boost (lsb), modified 123781.doc 200832411-style self-boosting (RLSB), erased area self-boosting (EASB), and modified erased areas Self-boosting (REASB) attempts to reduce stylized interference by isolating the channels of previously programmed components and the channels from which the stylized components are to be disabled. For example, REASB technology uses a very low isolation voltage (for example, 0 V to i V) to drive a word line near the selected word line on the programmed side, and utilizes a A medium voltage (about 3 V) is used to drive a line of words next to the selected word line on the programmed side to isolate the programmed side from the erased side. All other unselected word lines are driven with a conduction voltage. Therefore, two separate boost channels are created. Due to the effect of the threshold voltage of the programmed memory elements, the boosted channel voltage on the programmed side will be 1 V to 2 lower than the boosted channel voltage on the erased side. V, however, is still sufficient to increase the threshold voltage of the isolated word line. As the length of the channel in the memory component continues to decrease, the ability of conventional channel boosting techniques to reduce stylized interference continues to decrease. Specifically, the channel length of the 'memory element' may become too short to adequately isolate the two separate boosted channel regions at the drain and source sides of the selected word line. As a result, the boost channel voltage can be reduced, resulting in stylized interference. In addition, high electric field effects (such as band-to-band tunneling (BTBT) and gate-induced drain leakage (GIDL)) may also cause the booster channel to be discharged, and/or hot carriers due to high-voltage places may Will be injected into the tunneling oxides or into the floating gates of the memory components. Therefore, there is still a need to improve the techniques for stylizing interference problems. SUMMARY OF THE INVENTION 123781.doc 200832411 The present invention discloses a technique for reducing stylized interference effects when staging non-volatile memory. In particular, multiple isolation regions are used to divide a channel associated with a storage element into a plurality of zones. A suitable conduction voltage can then be used to bias each of the plurality of binning regions to help reduce the gates caused by the source select line and the drain select line and the isolated word line.汲 (4) Leakage relationship and the leakage current flowing from the side of the area. These techniques are particularly useful for preventing severe stylized interference effects such as, for example, at the edges of a memory region at the higher and lower word lines of a long string of NAND memories. Μ中- 实实_中' will select—storage components for programming. The channel associated with the set of storage elements is divided into at least three by applying an isolation voltage to the storage element of the proximal end of the selected storage element and to the other storage element that is remote from the health element. : From the Siam area. Therefore, a first one, f, /, and a channel region are disposed on each other == one portion on the opposite side of the selected storage element. The third channel area is :::°Hai: Store 70 pieces. The potential of the third channel region is boosted by the boost voltage of the first channel region, which is lower than 忒. In a preferred embodiment, the isolation voltage is generated by the third storage element of the selected storage element, thus = the selected fourth generation channel region is generated. In-step, ; = = can be applied to multiple storages in order to create multiple isolations;; = in the specific embodiment, the __ standard to the location and the selected eclipse _ , book & storage and storage of 70 proximal channel regions corresponding to the storage element 123781.doc -10- 200832411, and will apply a lower conduction voltage to the channel region located away from the selected component Storage (four). In a preferred embodiment, the conduction voltage applied to the channel region at the proximal end of the selected storage element will be higher than the standard conduction voltage. The features and advantages of the present invention will become more apparent from the detailed description and the appended claims. [Embodiment] The present disclosure relates to techniques for reducing stylized interference, particularly at word lines at the edges of a NAND memory string. The basic concept for reducing stylized interference is to provide an additional isolation region along the NAND memory string in order to reduce the conduction voltage applied to the word line at the edge of the νανε^ memory string. An example of a non-volatile memory system suitable for practicing the present invention is the use of a NAND flash memory structure in which a plurality of transistors are arranged in series between two select gates in a NAND string. The figure "shows a top view of Figure 1. Figure 2 is the equivalent circuit. The Nand string described in Figure 2 and Figure 2 contains four transistors 1 〇〇, 1 〇 2, 1 〇 4, and 1 〇6, which will Connected in series and sandwiched between a first selection gate 12A and a second selection gate 122. The selection gates 120 and 122 respectively connect the NAND string to the bit line contact 126 and the source line Point 128. Select gates 12 and 122 are controlled by applying appropriate voltages to control gates 120CG and 122CG, respectively. Each of transistors 1 , 102 , 104 , and 1 6 has a control gate The pole 100 has a floating gate. The transistor 100 has a control gate 1 〇〇 CG and a floating gate 123781.doc 200832411 1 〇〇 FG ° transistor 102 includes a control gate 102CG and a floating idle pole 1 〇 2FG ° transistor 1 〇4 includes control gate i〇4CG and floating gate 4 FG gas crystal 1 〇6 contains a control gate 1 〇6 CG and floating idler 106FG. Control gate 1〇〇(^, i〇2CG, 1〇 4CG and 1〇6CG are respectively connected to the word lines WL3, WL2, WL1 and WL0. In a feasible setting, the transistors 1〇〇, 1〇2, 104 and 106 are respectively Memory elements or storage elements. In other designs, the memory elements may contain multiple transistors or may differ from those described in Figures 2 and 2. Select gate 12〇 will be connected to the drain Line SGD, and select gate 122 is connected to source select line SGS. Note that although Figures 1 through 2 show four memory elements in the NAND string, four transistors are used as one Example. A NAND string used in conjunction with the techniques described herein may also use four or fewer memory elements or more than four memory elements. For example, a particular nand string will be packaged in three eight or sixteen. Twenty-two, sixty-four or more memory elements. The discussion herein is not limited to any particular number of memory elements in a NAND string. In general, the invention can be used by Fowler-Nord A device for staging and erasing the dental tunnel. The invention is also applicable to devices using a multilayer dielectric stack, such as yttrium oxide, cerium nitride, and yttrium oxide ( ΟΝΟ) the dielectric formed, Or a dielectric formed of yttrium oxide, a high-k layer, and yttrium oxide. A multilayer dielectric is sandwiched between a conductive control idler and a semiconductor substrate above the memory device channel. Between the surfaces. For example, the invention can also be applied to make 123781.doc -12· 200832411 use a small conductive material island (such as nanocrystals) and replace the floating gate with a charge trapping layer (such as tantalum nitride). As a device for the charge storage area, such a memory device can be programmed and erased in the same manner as a NAND flash device that is very dominant in floating gates. Figure 3 is a circuit diagram depicting three NAND strings. A typical architecture for a flash memory system using a NAND structure includes several NAND strings. For example, three NAND strings 201, 203, and 205 are shown in a memory array with more NAND strings. Each of the NAND strings includes two select transistors and four memory elements. For example, NAND string 201 includes select transistors 220 and 230, and memory elements 222, 224, 226, and 228. NAND string 203 includes select transistors 240 and 250, and memory elements 242, 244, 246, and 248. NAND string 205 includes select transistors 260 and 270, and memory elements 262, 264, 266, and 268. Each NAND string is connected to the source line by its selection transistor (e.g., selection transistor 230, 250 or 270). A select line SGS is used to control the source side select gates. Each of the NAND strings 201, 203, and 205 can be connected to individual bit lines 202, 204, and 206 by select transistors 220, 240, 260, etc., controlled by the drain select line SGD. In other embodiments, the select lines do not have to be shared. Word line WL3 is coupled to the control gates of memory elements 222, 242, and 262. Word line WL2 is coupled to the control gates of memory elements 224, 244, and 264. Word line WL1 is coupled to the control gates of memory elements 226, 246, and 266. Word line WL0 is coupled to the control gates of memory elements 228, 248, and 268. From the figure, you can see 123781.doc -13- 200832411 out of each of the 70 lines and the individual nand string including the line in the memory element array or group. The word lines (WL3, WL2, WL1, and WL0) include columns in the array or group. Each word line connects the control gate of each memory element in the column. For example, word line WL2 will be coupled to the control gates of memory elements 224, 244, and 264. Each memory component can store data. For example, when storing a digit of a digital cradle, 'the range of feasible threshold voltages of the memory component will be cut into two ranges'. These ranges will be assigned logical data values "1,,,,,〇 ,,. In an example of a NAND type & flash memory, the threshold voltage after erasing the memory element is a negative value and is defined as a logical "丨". The threshold voltage after a one-shot operation is positive and will be defined as logic, 〇". When the critical voltage is negative and an attempt is made to read, the memory component will be turned on to indicate that the logic '1" is being stored. When the threshold voltage is positive and a read operation is attempted, the memory component will not turn on, and this indication will store the logic, 〇, ,. A memory component can also store multiple levels of information, for example, multi-bit digital data. In this case, the range of the threshold voltage is divided into the number of levels of the material. For example, if four information levels are stored, four threshold voltage ranges are assigned to the data values "u,,,q〇π, "〇1" and "00". In an example of a NAND type memory, the threshold voltage after the erase operation is a negative value and is defined as "丨丨". The positive threshold voltage is used for the states ""1〇",,,〇1", and "00". The particular relationship between the data programmed into the memory component and the threshold voltage range of the component depends on the data encoding scheme employed by the memory components. For example, US Patent No. 6 222 762 123781.doc -14-200832411 entitled "'Novel Multi-State Memory," and US Patent Application No. 2004 entitled "Tracking Cells For A Memory System" The two cases of /0255090 illustrate various data encoding schemes for multi-state flash memory components. The entire contents of both cases are incorporated herein by reference. Related Examples and Operation of NAND Flash Memory It is provided in the following reference patents: U.S. Patent No. 5,386,422, U.S. Patent No. 5,522,580, U.S. Patent No. 5,57,315, U.S. Patent No. 5,774,397, U.S. Patent. No. 6, pp. 46, 935, U.S. Patent No. 6, 45, 528, and U.S. Patent No. 6,522,58; each of which is incorporated herein by reference in its entirety. A stylized voltage is applied to the control gate of the component, and the bit line associated with the component is grounded. Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating brake In the middle of the pole, the floating gate becomes negatively charged and the threshold voltage of the component rises. To apply the stylized voltage to the control gate of the component being privateized, the stylized voltage is Applied to the appropriate word line. As discussed above, the word line is also connected to one of each of the other NAND strings that share the same word line. For example, when stylizing Figure 3 When element 224, the stylized voltage Vpgnj^ is applied to the control gates of elements 224, 244, and 264. When it is desired to program one of the elements on a word line without stylizing the other connected to the same word line In the case of a component, for example, when it is desired to program the component 224 without programming the component 244, a problem arises because the stylized voltage is applied to all components connected to a word line, so the character Online 123781.doc •15· 200832411 Unselected components (that is, components that are not selected for stylization) may be inadvertently programmed in a program commonly referred to as stylized interference. Come When stylizing component 224, adjacent components 244 or 264 that may be of concern may be inadvertently stylized. Note that stylized interference is most likely not present on a character line selected for stylization. On the memory component. However, in certain cases, stylized interference may also occur in memory components other than the selected word line, and several techniques can be used to prevent stylized interference. Boost (SB), which electrically isolates the channels associated with the unselected bit lines, and applies a conduction voltage (eg, 〇V) to the unselected during stylization The word line. The unselected word lines are coupled to channels associated with the unselected bit lines such that a voltage (eg, 8 V) is present in the unselected bit lines In the channel, this tends to reduce stylized interference. Thus, self-boosting causes voltage boost to be present in the channel, which tends to reduce the voltage across the tunneling oxide and thereby reduce stylized interference. A NAND string will typically correspond to the sequential configuration of the word lines from WL 〇 to WL 3 from which the source side to the drain side are programmed, for example, from memory element 228 to memory element 222. As an example, assume that all or most of the memory elements in adjacent NAND strings 203 have been programmed before all or most of the memory elements in the ΝΑΝβ string 201. Therefore, when the stylized program is ready to program the next few memory elements in the NAND string 2〇1, the floating of the previously programmed memory elements above the gate of 123781.doc -16·200832411 There will be a negative charge. Therefore, the boost potential using standard SB techniques may not be large enough in portions of the NAND string 203 to avoid the effects of programmed interference on the elements associated with the subsequent number of word lines in the nand string 203. For example, when the component 222 on the NAND string 201 is programmed, if the components 248, 246, and 244 on the previously programmed NAND string 203 are then 'each of the transistors (244, 24 6 and 248) One will have a negative charge on their floating gates, which will limit the boost level of the self-boosting process and may cause stylized interference on component 242. Both local self-boosting (LSB) and erased area self-boosting (EASB) attempt to solve the shortcomings of conventional self-boosting by isolating the channels of previously programmed components from the channels of the disabled components. Fix the technology. For example, if element 224 of Figure 3 is being programmed, then LSB and EASB will attempt to disable stylization in element 244 by isolating the channel of element 244 from previously programmed elements (246 and 248). . For SB, EASB, and LSB boosting methods or variations of these boosting methods, the bit line of the component to be programmed will be connected to ground or another low voltage (usually 〇V to ^ v), while the bit line of the NAND string with the elements to be disabled is at Vdd, which is typically in the range of h5 乂 to 3 v. The stylized voltage VPgm (for example, 20 V) is connected to the selected word line. In the case of the LSB boost mode, the word line next to the selected word line is set to 〇V or close to 0 V, while the remaining unselected word lines are $ 疋Conduction voltage vpass. For example, bit line 2〇2 is at 〇V and bit line 2〇4 is at vdd. The drain selection line sgd is located at 123781.doc -17- 200832411 at Vsgd (usually 2.5 V to 4.5 V) and the source select line SGS is at 〇v ° selected word line WL2 (for stylized components) 224) is at vPgm. The adjacent word lines WL1 and WL3 are at 〇v, while the other word lines (for example, WLO) are at V_s. The disadvantage of the LSB mode is that the boosted channel voltage below the selected word line can be very high, since some of the channel will be isolated from other channel areas below the unselected word line, and therefore the main The boost voltage is determined by the high program voltage vpgm. Due to this high boost relationship, BTBT or GIDL may appear near the word line biased to 〇v, and the resulting hot carriers may be injected into the selected words in the unselected NAND string. In the middle of the line. The amount of channel boost can be well controlled using this easb method. The EASB and SB are identical, with the only exception that the source side of the selected word line is biased at 〇 V. Therefore, the channel region below the selected sub-element and the channel region at the drain side of the selected component are connected, and therefore, the channel boosting is applied to have an erased state. The voltages of these unselected word lines are steadily determined 'because the boost is not affected by the data that has been previously programmed. If Vpass is too low, the boost in that channel will not be sufficient to prevent stylized interference. If the vpass is too high, it may be programmed to select an unselected word line in the selected NAND string (the bit line is Ο V)' or may interfere with the unselected NAND string due to GIDL. Selected child line. For example, WL1 would be at 〇v instead of Vpass, while WL3 would be at Vpass. In a specific embodiment, Vp_ is 7 V to 10 V. 123781.doc -18- 200832411 Although there is a problem with LSB and EASB providing improved boost, the problem will depend on the proximity of the source on the source side (the source 246 is the source side of the component 244). To be stylized or erased. If the source side adjacent component is in a programmed state, it will have a negative charge on its floating gate. Furthermore, applying 〇V to the control gate and combining it with a highly reverse bias junction under the negative gate (due to the boosting relationship) may cause the gate to induce a drain/3⁄4 drain. (GIDL) 'The electrons leak into the boost channel. GIDL is accompanied by a large bias voltage on the junction and a low or negative gate caused by the south voltage on the //pole/source regions of the memory elements due to the boost relationship. The pole voltage is $ see, which is the case when the source side is clamped and the drain junction is boosted. This boost voltage may be prematurely leaked out, resulting in a stylized dry k and the stomach P is now more severe with a sudden and highly doped junction (which is needed when the component size is reduced). If the _ stream is high enough, the boost potential in the channel region may be reduced, causing stylized interference. Moreover, the closer the word line being programmed is to the immersed pole, the φ smear that appears in the boost channel region, and the less the power, the less. Therefore, the voltage in the boost channel will drop rapidly and the staggered stylized interference. Another possible side effect of GIDL is that H can produce hot carriers (both electrons and holes). This hot carrier can be blessed, t human & κ,, ^ -# ^ - .. / In the dental tunnel emulsion zone or in the vicinity of the floating gate of the adjacent body. The same kind of stylized interference caused by the (10)L will occur on the complex word lines at the edge of the 123781.doc 200832411 NAND string, such as WL0, WL1 in a 32_nand string. WL3G, and WL31. Since the source and the gateless selection gate are both biased at a low voltage (usually 〇V for the source side and 2·5 v for the drain side), GIDL will occur at Select - Select the gate pole edge, which will cause the boost voltage to be discharged. For longer 'NAND strings, this problem becomes more serious. If the source side adjacent memory element is erased, then a positive charge will be present on the floating φ gate and the threshold voltage of the transistor will likely be negative. Therefore, even if 〇 v is applied to the word line, the transistor may not be turned off. If the memory component is turned on, the NAND string will not operate in the EASB mode. More specifically, the 1^81 system operates in the self-boost mode, which may have the problem of insufficient boost as explained above. This is the most likely case for stylized other source side components, which limits the source side boost. This problem is the biggest problem with shorter channel lengths because leaks are more likely to occur. Figure 4 is a block diagram of one embodiment of a flash memory system that can be used to implement one or more embodiments of the present disclosure. Other systems and implementation methods are also available. The memory element array 302 is controlled by row control • packet 304, column control circuit 3, c source control circuit 3 1 〇, and p well ^ control circuit 308. The row control circuit 3〇4 is connected to the bit line of the memory device array 3〇2 for reading the two materials stored in the memory elements for determining the memory elements in a The shape and duration of the stylized operation and the potential level used to control the bit lines to facilitate or prohibit the ordering and erasing of the order. Column control circuit 306 is coupled to the word line 123781.doc -20-200832411 to select one of the word lines, apply a read voltage, apply a bit with the control of row control circuit 3〇4 The stylized combination of the potential of the potential of the line is 二V: the voltage is removed. C source control circuit 31 ° will control the connection with the memory element, the shield, the Lu, the source line (marked as "C source in Figure 4) . The well control circuit 3 〇 8 will control the ρ well electric dust. The portions of the towel stored in the memory device are read by the row control circuit 3〇4 and output to the outer (10) line via the data input/output buffer 312. The program data to be stored in the memory elements is input to the data input/output buffer 312 via external scramble lines, and is output to the line control circuit 304. These external 1/〇 lines will be connected to the control: Benefit 3 1 8. / The command data for controlling the flash memory device is input to the control σ, and the poor material informs the flash memory what kind of action is required. The input command is transmitted to the state machine, which is controlled by the control circuit 3〇6, the C source control circuit 31〇, the P well control circuit 308, and the billiple input/output buffer 312. The state machine 3 16 can also output status data of the flash memory, such as ready/busy green or pass/fail. The device 318 can be connected to or can be connected to a host system, such as a digital device, a personal digital assistant, or a similar host system. The 3 3 8 will communicate with the host to receive commands (eg, The data storage sub-array array 302 is either read from the memory array 302 and provides or receives such data. The controller 3 1 8 will, for example, become a 7^ number and The control lines send them for interpretation and execution for the command circuit 314 that is part of the control circuit system 315. The command circuit 3 14 W communicates with the state machine 3 16 6. The controller 3 1 8 typically contains The buffer body is used for user data to be written into or read from the memory element array 302. The non-standard memory system includes an integrated body. a circuit comprising a controller 318; and one or more integrated circuit chips, each comprising a memory array and associated controller, input/output and state machine circuits. The memory array is integrated with the controller circuit of the system - or a plurality of integrated circuit chips. The memory system can be embedded as part of the host system or can be included in a removable card that is inserted into the host system (or other phantoms. This = card may contain the entire memory system (for example, it contains the control) or only the memory array associated with the peripheral circuitry (embed controller or control functions in the host) Therefore, the controller can be embedded in the host or included in the extractable memory system. • In a specific implementation, the specific components in Figure 4 can be combined. Further, in various designs, In addition to the memory element array 302, one or more of the components of Figure 4 can be considered as a management circuit. For example. - or multiple management circuits may contain control circuitry, a command circuit. A circuit, a state machine, a train of control circuits, a row of control circuits, a well control circuit, a source control circuit, and a data 1/() circuit. Figure 5 provides the memory of Figure 4. An example structure of the component array 3〇2. As an example, the NAND flash EEPR〇M described herein will be divided into 12128l.doc • 22-200832411 blocks. In an erase operation, it will be erased at the same time. The data stored in each block is in the item design, and the block is the smallest component unit that will be erased at the same time. In this example, there are 8,512 rows in each block, which are divided into even rows and odd rows. The bit lines are also divided into even bit lines (BLe) and count bit lines (BL〇). The four memory elements shown in the figure are connected in series to form a -NAND string. Shows that there are four components in each NAND string, but you can still use more or less

For four memory components. In fact, a particular embodiment of a longer string is explicitly covered with reference to Figures 14-17. One of the terminals of the NAND string is connected to a corresponding bit line via a select transistor SGD, and the other terminal is connected to the source line via a second select transistor SGS. During the configuration of one of the item selection and the simplification operation, 6 memory elements are selected at the same time. The selected memory elements such as Shuhai will have the same word line and the same type of bit line (for example, even bit lines or odd bit lines, so 'can be read or programmed simultaneously to form a positive page of _ logical pages Data bit 7G group, and a block in the memory can store at least eight logical pages (four word lines, each of which has odd and even pages). For multi-state memory components When each memory element stores two data bits (where each of these two bits is stored in a different page) - a block can store sixteen logical pages. Other sizes of blocks and pages may also be used in the present invention. In addition, the present invention may be implemented using architectures other than those of Figures 4 and 5. For example, in the item design, the material bits are not divided into odd numbers. With even bit lines, you can program (and program different bit lines simultaneously. ^ 123781.doc -23- 200832411 by raising the P well to the erase voltage (eg 2〇v) and The memory component can be erased by grounding the word line of a selected block. Floating with the bit line system. The erasing can also be performed on the entire memory array, the separation block, or another memory element unit of one of the memory devices. The electrons will float from the memory cells. The gate is transferred to the p-well region so that the threshold voltage of the memory component becomes negative. In the read and verify operations, the select gate (SGD and SGS) is connected to φ to 2·5 V. Voltages in the range of 4·5 V, and the unselected word lines (eg, when WL1 is selected as the word line, WL〇, and WL3) are raised to a read Conduction voltage (usually a voltage falling in the range of 4·5 v to 6 V) to operate the transistors as conductive gates. The selected word line WL1 is connected to a voltage, which is The level is specified for each read and verify operation to determine if the threshold voltage of the associated memory component is above or below this level. For example, reading a dual level memory component In operation, the selected word line • WL1 may be grounded, so it can be judged The threshold voltage is higher than 〇v. For example, in the verification operation of a two-level memory element, the selected element line WL1 is connected to 〇·8 v, so it can verify the threshold. The electric castle has arrived at least UV. The source and the ρ well are at 〇¥. The selected bit lines (assuming the even bit line (BLe)) are precharged to (for example) 0· Level of 7 V. If the critical dust is higher than the read or verify level on the word line, then due to the relationship of the non-conducting memory elements, the bit line associated with the element of interest (BLe) The potential level will remain at the level of the question. On the other hand, if the threshold voltage is lower than the reading or verification of 123781.doc -24 - 200832411 - a * (four) because the conductive memory component will be the bit Line advance: The relationship of the bit-in relationship of the potential bit line (BLe) will be reduced to the line, for example, less than G.5 V. Because &, the memory element can be detected by the --ink comparator sense amplifier connected to the bit. The erase, read, and verify operations described above are implemented in accordance with the techniques of the present technology. Because of this, those skilled in the art can change many of the details explained above. Other erase, read, and verify operations known in the art can also be used. /, As described above, each block can be divided into several pages. In one of the ways 'H stylized units. In a particular implementation, the individual pages can be divided into a plurality of segments and the breaks may contain the fewest components that are written once at a time for a basic stylization operation. Usually one will be: Multiple data pages are stored in the - column memory component... The page can store one or more segments. One section contains user data and management data (e.g., ad data), for example, an error correction code (ECC) calculated from the user (4) of the paragraph (4). When the data is being programmed into the array, the ECC is calculated in one part of the controller and is also used to check the data when reading the data from the array. Alternatively, the Ecc and/or ^ management data will be stored in a different page or even a different block from their associated user profile. In other designs, other parts of the memory device (e.g., state machines) can calculate ECC. A section of user data is typically 512 bytes, which would correspond to the size of a sector in the drive. Management data is usually an additional 16 to 2 bytes. A large number of pages form a block, wherever it is 123781.doc -25 · 200832411 contains 8 pages to, for example, up to 32, 64 or more pages. Figure 6 depicts an exemplary stylized pulse waveform. The stylized voltage v P gm

Will be divided into a number of pulses. The amplitude of the pulses increases by a predetermined step size with each pulse. In a specific embodiment in which the memory cells are stored in a data bit, an example of a step size is 0. 8 volts. In a specific embodiment comprising a plurality of data bits for storing the memory cells, the example of the step size is 〇 2 volts. An example of the starting position of the stylized voltage Vpgm2 is 12 V. When an attempt is made to disable a unit from being programmed, the channel is isolated by raising the bit line voltage to Vdd and the pass is boosted by the conduction voltage (Vpass). In a particular embodiment including the memory cells storing a plurality of data bits, the amplitude of the conducted voltage may not step up. A verify operation is performed during the period between the pulses. That is, the programmed finalization of each unit being parallelized is read between each stylized pulse to determine if it is equal to or greater than the verification level being programmed. For example, if the threshold voltage rises to 2.5 volts, the verification procedure determines if the threshold voltage is at least 2 volts. If it is judged that the critical power of the given memory cell has exceeded the verify level, then the bit line tail of the NAND string of the cell will be boosted to Vdd. The customisation of other units to be parallelized will continue until they reach their verification level. Figure 7 is a flow chart illustrating a specific embodiment of a method for stylizing a corpus. In one of them, there is no way to do it, it will be before the stylization 123781.doc •26- 200832411

Erasing the memory unit (in blocks or other units). At step 55 〇t ' of Fig. 7, the controller 318 issues a "data load" command and inputs it into the tribute input/output buffer 312. Because the command latch signal (not shown) will be entered into command circuit 314, the input data will be asserted and commanded and will be latched by state machine 316. In step W, the address data representing the page address is input from the controller 318 to the data input/output buffer 312. Since the address latch signal is input to the command circuit 314, the input data is asserted as a page address and is latched by the state machine 3丨6. In step 554, the 532 bytes of stylized data are entered into the data input/output buffer 312. The data is latched into the data storage registers of the selected bit lines. In certain embodiments, this material is also used for verification operations. In step 556, the controller 318 issues a "program" command and inputs it into the data input/output buffer 312. Since the command latch signal is input to the command circuit 314, The command will be latched by state machine 3 16. After being triggered by the "stylized" command, the data latched in the data store temporary will be stylized using the step shown in the pulse of Figure 6. Programmized into the selected memory cells controlled by state machine 3 16. In step 558, Vpgm is initialized to the start pulse (e.g., 12 V) and the program retained by state machine 316 The count value Pc will be initialized to 0. In step 560, a first Vpgm pulse will be applied to the selected word line. If the logic is stored in a particular data storage register, then the corresponding The bit line will be grounded. On the other side, 123781.doc -27- 200832411, if the right logic is "1," each bit stored in the m ^ ^ (four) buffer will be the bit line. Connected to Vdd' to disable. ▲ In step 562, the selected records are verified: _. State. If the status of __selected unit @ ... early 70 is detected (for example, H... the interface has reached the logic of the appropriate bit t...°, or - the program level of the special state), then stored The information will be changed to logic " If right, the threshold voltage has not yet reached the appropriate level.

It will change the poor materials stored in the data storage temporary storage. According to this side, 'it' must be programmed in the corresponding data storage register to store all the data storage buffers are stored logic "factory time' will know that all the selected programs have been programmed unit. In step 564, it is checked if all data storage registers are storing logic 1 . Right is ' then the stylized program is completed and successful because all selected memory units have been programmed and verified. A "pass" status is reported in step 366. If it is determined in step 564 that not all data storage registers are stored logically, then the stylized program will continue. In step 568, θ is used to check the stylized count value PC. One of the examples of stylized limit values is 2G. If the stylized count value PC is not less than 20, then the stylized program has failed, and a "failure, state" is reported in step 570. If the stylized count value PC is less than 20, then The Vpp level is incremented by the step size in step 572 and the stylized count value pc is incremented. After step 572, the program returns to step 56, to apply the next v 123781.doc -28-200832411. The shoe cover described in Fig. 7 or a variation thereof can be realized by various stylized methods. Figure 8A shows that each memory element stores two data bits.砗兮 “t ^^ ^ 边 $ Recall the critical voltage distribution of the body element array. E Describes the first critical voltage distribution of the erased body. A, B, and c describe the three critical voltage distributions of the programmed 70% and 餸70 pieces. In one design, the critical I in the Ε distribution is negative, while the critical voltages in the Α, Β, and C distributions are positive.

The specific relationship between the parental f-pressure ranges corresponding to the predetermined threshold of the set of data bits is & the specific relationship between the data in the memory component and the critical voltage level of the component depends on the The data encoding scheme used by the components. Ganzi, - y .. _ /, the consumption will assign the logical data value "11," to the threshold voltage target E (like E, assign,, 1 〇" to the critical voltage range A (state A), refer to The port boundary range B (state B) and the assignment "〇1" give the threshold voltage fc a C (like c). However, in other designs, the pot scheme can be used. In 562, three read reference voltages ν^, v吮, and * are used to read data from the memory device. By testing - the threshold voltage of a given storage element is higher than the lower KVra, Vrb & Vrc, The system is capable of determining the state of the memory component. Three verification reference voltages Vva, Vvb, and Vvc are also shown. When the memory component is programmed to state A, B, or C, the system will be in the figure. The step of 7 tests whether the threshold voltages of the memory X pieces are greater than or equal to Vva, Vvb or respectively. In a method called full sequence stylization, the memory elements 123781.doc -29-200832411 can be used. The erased state E is directly stylized to any of the programmed states A, B, or c (the curve in the figure) The arrow shows. For example, a group of memory elements to be stylized may be erased first, so that all the tl parts in the group will be in the erased state E. Although the specific body element is stylized to state a, other items are programmed from state E to state state or state 1 state.

The patterns ~, C7 are programmed as described in Fig. 8A using the program of Fig. 7 to program the memory units. Figure 8B shows an example of a two-pass technique for multi-state memory components for stylized storage of two different pages (one upper page and one lower page). In the figure, C(01). For sadness E, both pages store τ. For state a, the next page stores "〇, and the previous page is stored, 1Π. For the state B, both pages are stored. For state C, the next page stores "^, and the previous page is stored. ,,〇,,. The system that should be phonetic can assign different bit maps even though a particular bit pattern has been assigned to each of these states. Both stylization can be performed using the procedure of Figure 7. In the first stylization, the critical voltage level of the component is set according to the bit it to be programmed to the next logical page. If the bit is logic "1", the threshold voltage will not be changed because it will be in an appropriate state due to the previously erased relationship. However, if the bit system to be processed is logic T, then the critical level of the element will be changed to become state A ’ as indicated by arrow 43. It will end the first programming operation. In the second stylization operation, the critical voltage level of the component is set according to the bit TL in the program being programmed to the top logic 12378] .doc -30- 200832411. If the logical page bit 7L is to store a logical "丨", then no stylization will be performed because the component is in the state E or A, and the program of the next page + bit is viewed. Depending on the situation, both will carry a previous page bit "1Π. If the upper page bit is to be logical, then the critical voltage will be shifted. The first time the Russian right causes the component to remain in the erased state, then in the second time, the component will be programmed, so that the critical power is high and falls in the state α, such as the arrow. Described in 434. If the 70 pieces are programmed into the state after the first stylization, then in the second time, the memory component will be further programmed, causing the threshold voltage to rise and fall into the state. Within B, as depicted by arrow 432. The second result will stylize the component to the state in which the last page stores the logic, without changing the data on the next page. i In one of the ways 'if enough data is written to fill a full page' then the system can be set up to implement a full sequence of writes. If sufficient data is not written for the full page, the stylized program can use the received data to program the next page. When subsequent data is received, the system will program the previous page. In yet another way, the system may start writing in the stylized mode 1 and if enough (4) is received later to fill all or most of the memory elements of the word line, then Will be converted to full sequence stylized mode. Further details of this approach are disclosed in U.S. Patent Publication No. 2006/0126390, the disclosure of which is incorporated herein by reference to "Pipelined Pn.g_ming of Nonv〇iatiie usingEadyData" 123781.doc 31 200832411 Sequence diagrams 2 to 9° describe another procedure for stylizing non-volatile memory. = For special memory components, reduce the polarity of the transition by the following methods. The adjacent memory elements of the previous page are written to the special memory element for a particular page. In an exemplary application mode, each of the non-volatile memory types is programmed.

The state has been erased and the state A, BA ^ M t t row L system has been privateized. State £ store = two-state A store! Data 01, state_storage data 1〇, and shape 2 J sub-bats material 00. 14-series non-Gray coding-consumption case because both bits will be in adjacent state eight and three Change between: You can also use other data encoding of the physical data status. Each memory π will be #1 stored from the two data stomach based on the purpose of the reference, the second data page will be called the upper page and the next page; 'However, it can also be provided for its 4 § . Say to the status wire, 'The previous page will store bit 0 and the next page will be stored. For the status Β, 'The last page will store the bit. The next page will store the bit 1 for the disgusting c. I wish both pages are stored. Bit data 〇. This stylized program 2 has two steps. Both steps can be performed using the procedure of Figure 7. The next page will be stylized in step >. Even if the next page retains the data ^, then the state of the memory component will remain in the state. If the data is to be stylized to 0, then the critical dust VTH of the memory component is increased, and the memory component is programmed into state Bl. So 9A shows that the memory element is stylized from state E to state B, which represents the intermediate state B; so 'depicted in the figure as the verification point Vvb, which is lower than the vvb described in Figure 9C. 123781.doc •32- 200832411 In one design, after a memory component is programmed from state E to state, adjacent memory components on an adjacent word line are stylized relative to its next page. . After stylizing adjacent memory components, the floating gate-to-ocean gate coupling effect will increase the memory component of the memory cell in question. The memory component is in state B. This has the effect of widening the critical voltage distribution of the B' of B' to the critical voltage distribution of 45 图 in Fig. 8B. The widening of the threshold voltage distribution will be continued when the previous page is privately placed.

Figure 9C illustrates the f-presentation of the private page. If the memory component is in the erased state E and the upper page is to be maintained at i, then the memory component will remain in state E. If the memory component is in state E and the data on the previous page is to be stylized to 〇, then the threshold voltage of the memory component will be boosted, so that the memory component is in state A. 70 pieces of mouth hai 5 have a middle threshold voltage distribution 450: state B', and the previous page data should be maintained at 1, then the body component will be programmed to the final state B . If the memory component is in state B with an intermediate criticality distribution 450, and the information is to become data 0, then the critical component of the memory component will be (4), so that the memory component is State c. Figure 9AK does not reduce the frequency of the floating gate. The floating gate has the effect of the previous page "=_合合, because only the full turn-off" page will affect - given memory element 1 from eight #代状心,. The example of the flat code is on the previous page of the data to the state c 'and moved to the situation when the data on the previous page is 0. Although the figure provides - relative to the four data states and two assets 12378l.doc -33- 200832411 An example of a material page, however, the concepts taught can be applied to other implementations with four or more states and more than two pages or less. More details on various stylization schemes and floating gate-to-floating gates can be found in US Application No. 11/099,133, entitled *^Compensating For Coupling During Read Operations Of ^ Non-Volatile Memory "This article is incorporated by reference in its entirety. Figure 9D depicts a typical timing diagram for applying a stylized pulse as part of step 56 of Figure 7. Signal 1500 description is applied to and is currently being a stylized waveform of a word line associated with a stylized storage element; and the nickname 1 5 1 0 is applied to the conduction voltage Vpass of other word lines. The nickname 1520 is described when applied. Vpgm disables the bit line voltage Vbl of the stylized storage element; and signal 153 描述 describes the bit line voltage of the storage element that is allowed to be programmed when Vpgm is applied. The signal NAND is described as a NAND string. The drain side selects the gate voltage. • At ^, the drain side select gate is opened by applying a higher voltage (3 V to 4·5 V). Please note that Source side selection gate It is biased at 〇V. Then, the bit line is applied, and Vbl is used to program-store the component. In this case, Vbl is at or near 〇V, or at 0 ▽. Between the range of 1 v for rough/fine verification methods; or for applying a voltage V-core (usually a voltage from u "to 3 v") to disable the storage element from being programmed. When the bit line voltage VbL is 〇 V or another low voltage (curve 1530), this voltage will be the channel area of the storage element to be privateized. If a bit line voltage of 123781.doc -34-200832411 乂 is applied (curve 1520), the channel will reach a higher voltage (in the ideal case Vdd). in. At this point, if the bit line is at Vdd, vSGD will drop to turn off the select gate, and the select gate will remain in a conducting state for the lower VBL in the 0 V to 1 V range. At U, vpass will be applied to the selected word line and will be applied to all or nearly all of the unselected word lines in the NAND string. Wherein, the still stylized voltage Vpgm is applied to the selected word line, and depending on whether the channel is to be boosted to a high voltage or biased to a low voltage, the storage element will They are prohibited from being stylized or allowed to be stylized. After the programmed voltage Vpgm has been raised to this fixed amplitude level, the actual stylization of all states will mainly occur. To the end. In the case of 'private voltage Vpgm will be %; and at the same time, % will also drop, please note that the stylized voltage Vpgm may rise to its fixed amplitude and / or fall back, without stopping the stylization The voltage ^. Finally, the ^ ^ VSGD and VBL will also be shifted by 35. Then, one or more verification operations can be performed, basically a read operation to verify whether the storage element selected for programming has been Arriving at their target threshold voltage state. Additional stylized pulses with high amplitude can be applied until all or most of the storage elements have reached their desired threshold voltage state. As mentioned in the face, when stylized non-volatile Various boost methods can be used for memory devices (such as nand flash memory devices). For example, at two locations, a suitable boost voltage will be applied to all (or almost all) unselected characters. Line, which is used to prohibit or allow for stylization. Therefore, when the actual program is programmed during t7, there will be a required boost. Figure 123781.doc -35- 200832411 10 to 17 illustrates various boosting methods that will achieve different results and show the state of a particular word line at time t6. Self-boosting (SB) can be used in binary devices because this method allows for programming a NAND string in random order.

The word line. However, for multi-level devices, random order stylization is usually not used. In this case, LSB and EASB or variations of these methods can be used. An advantage of the LSB and EASB-based approach is that channel boosting is more efficient and therefore reduces stylized interference. However, when the size of the memory component is reduced, band-to-band tunneling or GIDL may occur near the drain of the grounded word line. The boosted channels may be discharged due to GIDL, which may cause stylized interference, or may generate hot carriers that are injected into the tunneling oxides of the memory components or the floating gates. Refer to Figure 1 for a description of this problem. Figure 10 illustrates a NAND string 1 具有 with an unbalanced boost channel region when using the EASB boost mode. The NANE 1000 includes a source side selection gate 1〇1〇, a drain side selection gate 1055, and memory elements 1〇15, 1020, 1025, 1030, 1035, 1040, 1045, and 1050. The modal 7L pieces are respectively coupled to the word lines WL0 to WL7 between the selection gates in a p-well area i 〇〇5. Although eight memory elements are shown in this figure, this configuration is only illustrative and other configurations can be used. As mentioned earlier, in a possible manner, stylization may begin with the source side memory component (for example, component 1〇1 5), and each time a memory component is advanced, To the 侧-side memory element 1〇5〇. In this example: the memory component is currently being programmed to be selected for the H component, and it will receive the stylized electric castle 123781.doc -36-200832411 pgm via word line WL5. a conduction voltage Vpass (which is usually in the range of 5 乂 to 1 〇 v) 、, and two are applied to the remaining memory elements by their individual word lines, except for the element 1035, which receives one Low voltage (which is usually 〇ν or 4 in the range of 0 V to 1 ν). In this example, memory components 1015 1020, 1025, 1030, and 1 〇 35 have been programmed, and memory 胄 component 1G45 and defragmentation have not yet been programmed, or at least have not yet reached their final programmed state. That is, the memory component (4) is not stylized and/or partially stylized. In a particular case, the memory element 1 〇 45, as depicted in Figure 9, may be in the intermediate programmed state B. Furthermore, in the case of the stylized scheme of Figure 9, adjacent memory elements 1035 may also be in an intermediate programmed state. In another possible stylized manner, when the memory component 1040 is being programmed, the adjacent memory components 1 〇 35 are only partially stylized. In addition, when a 4 component is being programmed, a bit line contact associated with the NAND string • 1〇00 may be grounded or may be coupled to an intermediate voltage (its It is usually in the range of ¥·2 ¥ to 1 V) for fine mode stylization. For example, see US Patent No. 6,888,758 5 Tiger's title, Programming Non-Volatile

Memory, which is explicitly incorporated herein by reference. After the memory element 1〇40 on the selected word line in the nand•string 1000 has been programmed to the desired state, a disable voltage can be applied. Vdd is applied to the word 70 line contact to prevent further memory element 1〇4〇 from being programmed until the other memory on the other NAND string connected to the same selected word line 123781.doc -37·200832411 The component is also programmed to the desired state. Due to the application of the conduction voltage, for example, it will form on the source side of the selected word line of the NAND string looo, under the previously programmed memory element. a low channel boosting region; (for example) simultaneously on the drain side of the selected word line of 1^8^〇 string-1G00, the selected memory component, and the unprogrammed and / or a partially channeled boost region is formed under the partially stylized memory component. Figure 1 is a schematic illustration of the boost regions. In general, memory components that have been programmed into a particular state will result in the Memory components The boost comparison of an associated channel region below has no effect. Furthermore, since the additional memory components are programmed from the source side to the drain side, the size of the bad boost region will increase without being programmed. The size of the high-boost region of the memory element that is partially and/or partially programmed is reduced. Due to the difference in the potential of the boosting channel and the small substrate bias effect caused by the poor boosting source side region Relationship, electric charge may leak from the high-boost channel region to the low-boost channel region, thereby causing a potential drop in the high-ruthenium channel region. Therefore, the selected word line is not selected. The possibility of stylized interference of the body element is increased. By increasing the potential of the boost channel in the already programmed region, it is possible to prevent charge from leaking from the high boost region to the low boost region. In one way, This can be achieved by using a higher Vpass value for the word line associated with the memory element that has been programmed, as illustrated in connection with Figure 11. Figure 11 illustrates a balanced rise An N AND string 11 通道 of the channel region. The NAND string 1100 includes a source side select gate 丨丨10, a drain side select gate 123781.doc -38 - 200832411 pole 1155, and memory elements 1115, 1120, 1125, 1130, 1135, 1140, 1145, and 1150, the memory elements are respectively subtracted to word lines WL 〇 WL WL WL7 between the select gates in a P well region 1105. In this way, the stylization begins with the source side memory component (for example, component 1115) and advances one at a time.

Memory element, to the drain side memory element 1丨50. In this example, memory element 1140 is the selected memory element that is currently being programmed, and it receives the stylized voltage vpgm via word line WL5. The conduction voltage Vpass of a vehicle father south is applied to the memory elements that have been previously programmed, such as memory elements 1115, 1120, 1125, and Π30, via word lines WL0, WL1, WL2, and WL3, respectively. Except for the source side memory element 1135, which receives 〇v via the word line WL4. A lower conduction voltage vpass2 is applied to the memory elements that are not stylized at the drain side of the selected memory element or to the memory that has not yet reached their final programmed state via word lines WL6 and WL7, respectively. Elements (for example, memory elements 1145 and 1150). Thus, in this example, vpass and vpasS2 are applied to individual subsets of memory elements in the NAND string, where each subset contains the opposite side of the memory device currently being programmed. One or more memory elements, but not necessarily all of the memory elements on the opposite side of the memory element currently being programmed. As described above, in the case of using the stylized scheme of Figure 9, the memory component (in this example, the memory component 145) located next to the selected memory component may be stepped on, aa JJ. In an intermediate stylized state B, among them. Furthermore, in the case of the process of Fig. 9 , the memory component 123781.doc -39- 200832411 1135 may also be in the intermediate programmed state. In fact, a low voltage (about 〇 VSi v) is applied to the adjacent source side memory element 1135 via word line WL4. Since the leakage between the drain and the source side is equal, and the relationship between the substrate bias effect due to the improved source side boosting reduces leakage, the boost potential may still be High enough. Applying a bias above 〇 V on the adjacent word line reduces the GIDL, which may occur on the adjacent word line.

Therefore, the boost of the channel region corresponding to the memory element that has been programmed can be improved. In particular, a high channel boost is formed under the memory component that has been previously programmed and under the selected memory component and the unprogrammed and/or partially programmed memory components. Area. The large conduction voltage of the channel region associated with the memory element that is not programmed first compensates for the lower boosting effect caused by the memory elements being in the programmed state. The exact compensation needs to know what state these programmed memory components are in. However, the number of pieces of stylized memory and the state to which they are to be programmed will follow each one—the NAND string is not fgj. In general, the best compensation in the range of about 2 ¥ to 3 in the character line associated with the previously programmed memory is compensated for the random data being written into the previously stylized memory. The average of the body components. That is, it should be more than 22 to about 2 V to 3 V. This difference can be optimized for a particular memory device by testing. It should be noted that the above-described LSB method and the application of such methods are not limited to EASB, and may be applied to variations of the method. In general, the compensation system provides 123781.doc 200832411 to reduce the boost on the source side of the selected memory component due to the partial or all of the memory elements being in the programmed state. Compensation is provided by raising the conduction voltage of the word line associated with the memory element that has been programmed to reduce or eliminate charge leakage between the two boost regions. Thus, the boost channel potential below the selected word line and the word line associated with the unprogrammed and/or partially programmed memory elements will be relatively high and will be almost It is irrelevant to the stylized character line. Therefore, stylized interference is reduced and smaller word line dependencies are presented. Furthermore, due to the improved boost relationship, Vpass2 may also be lower. For example, in one possible approach, Vpassl is approximately 10 V to 11 V and Vpassj 々 8 v, while the range of 'vpgm' may range from 丨6 V to 24 V in successive pulses of increasing amplitude. The optimum level of Vpassi and νρ_2 for a particular memory device can be determined by testing. It is also expected to reduce the V to ▼ tunneling because the lateral electric field below the grounded word line will therefore be reduced by the boosting technique. The further reduction of band-to-band tunneling can be achieved by the boosting scheme discussed in conjunction with Figure 2. Figure 12 illustrates a nand string 1200 having an isolation region between the boost channel regions. The edge NAND string 1200 includes a source side selection gate 121A, a drain side selection gate 1255, and memory elements 1215, 122A, 1225, 1230, 1235, 1240, 1245, and 1250, and the memory elements will Word lines WL0 through WL7 between the select gates in a p-well region 1205, respectively, are coupled. In this example, memory component 124 is selected to be privateized and will receive the stylized voltage VPgm via sub-line WL5. A relatively low conduction voltage vpassl will be applied to one or more of the previously programmed memory elements via the word line WL 〇 and WL1, 123781.doc -41 · 200832411, for example, memory Elements 1215 and 122A, and a lower or the same conduction voltage Vpass2 is applied to memory elements that are not programmed and/or partially programmed via word lines WL6 and WL7, for example, memory Parts 1245 and 1250. In addition, the lower conduction voltages Vpass3, and Vpass5 are applied to the previously programmed memory elements 1235, 123A, and 1225 via word lines WL4, WL3, and WL2, respectively, which are located in the selected memory. The body element 1240 is between the memory element m5 & 1220 that receives the higher conduction voltage 乂...". νρ_3, νρ_4, and Vpass5 are all smaller than Vpass 1 〇 In one mode, Vpass4 is less than Vpass3 and Vpass5. Vpa(1) and Vpass5 can be mutually About equal. Vpass3 and Vpaw are different. For example, vpass3 and vpass5 may be about 2 ¥ to 4 v; and Vpass4 is about 〇V to 1 V. As before, the call is "may be about 10 ¥ to 11 V. Vpass2 may be approximately 8 V, while in continuous pulses, Vpgm may range from 16 ¥ to 24 V. The optimum voltage for a particular memory device can be determined by testing. In this manner, the applied voltage substantially forms a channel or isolation region that is concentrated around a memory component (e.g., memory component 1230) having the lowest applied conduction voltage, wherein the conduction voltages It will increase symmetrically or asymmetrically on each side of the isolation zone. This isolation area may contain odd or even memory components. The isolation region is for isolating the two highly boosted channel regions and reducing the drain and source regions of the word line having the lowest bias voltage (eg, word line WL3 associated with memory element 1230) Voltage to avoid or reduce the band-to-band tunneling below the word line. Another specific embodiment with an alternative isolation zone will be provided in conjunction with Figure 13 123781.doc -42- 200832411. Figure 13 illustrates a NAND string 1300 having an alternate isolation region between boost channel regions. The NAND string 1300 includes a source side selection gate 1310, a drain side selection gate 1355, and memory elements 1315, * 1320, 1325, 1330, 1335, 1340, 1345, and 1350, and the memory elements are Word lines WL0 through WL7 between the select gates in a P well region 1 305 are coupled, respectively. In this example, memory component 1345 is selected to be programmed and it receives the stylized _ voltage Vpgm via word line WL6. A souther conducting voltage Vpass1 is applied via word line WL0 to one or more of the previously programmed memory elements, for example, memory element 13 1 5, and a lower or the same The conduction voltage Vpw is applied via word line WL7 to one or more of the unprogrammed and/or partially programmed memory elements, for example, memory element 1350. In addition, the lower conduction voltages Vpass3, v_s5, Vpass6, and Vpass7 are applied to the previously programmed memory elements 1340, 1335, 1330, 1325 via word lines WL5, WL4, WL3, WL2, and WL1, respectively. And 1320, which are located between the selected memory element 1345 and the memory element 13 15 that receives the lower conduction voltage vpassl. ' In one mode, vPass5 is less than Vpass3, Vpass4, Vpass6&, Vpass7. In addition, Vpass4 and VpaSS6 may be smaller than Vpass3 and Vpass7. Vpass3, vpass4, vpass5, vpass6, and Vpass_ are less than Vpassi. Ν_4 and vpass6 may be approximately equal to each other. Or, Chuan 4 and ~ Chuan 6 are different. Similarly, Vpass3 and Vpass7 may be approximately equal to each other. Or, and 123781.doc -43- 200832411

For example, Vpass3 and Vpass7 may be about 6 V to 8 V, two (four) and V”6 may be about 2 V to 4 V, and Vpass 5 may be about 〇^, such as Vpassl may be about 10 ¥ to u V Vpass2 may be approximately 8 V. In the sustain pulse, Vpgm may range from 16 V to Μ V. The optimum voltage for a particular memory device can be determined by testing. An extended trough or isolation region is formed which is concentrated on the memory element (e.g., memory device 133G) having the lowest applied conduction voltage and when the conduction voltage is on each side of the isolation region When symmetrically or asymmetrically increased, the slope of the boost profile will be away from the isolation region in a relatively gentle manner. Furthermore, the isolation region may contain odd or even memory components. The isolation region is used to isolate two The highly boosted channel region sub-subtracts the voltage on the drain and source regions of the word line with the lowest bias voltage (eg, the word line associated with memory element 1330) to avoid or reduce the word Belt to tunnel under the line. By extending the isolation The length of the zone further isolates the two highly stepped channel regions to avoid or reduce leakage between the two boost regions and to avoid or reduce band-to-band wear below the word line. The stylized interference reduction technique is applicable to both multi-level and unit quasi-stylization. Multi-level memory is expected to obtain greater benefits. For unit quasi-memory, it is expected to be larger under the following conditions. The benefits are stylized from the source side to the drain side of the N AND string in a predetermined word line order compared to programming in a random order. Again, these techniques can be combined with all boosts in principle. Technology is used. However, multi-bit quasi-boost mode (such as EASB and its variants) is expected to have the best benefit. 123781.doc -44- 200832411 When the device is further reduced, these techniques can be further corrected to solve Stylized interference effects and related crashes. For example, when scaling from 8_ NAND strings to i6-NAND strings and 32-NAND strings, the use of these boosting techniques will achieve significant benefits. Now move the focus to Longer On the string 'for example, 64_NAND string, where a single bit line will touch M storage elements. Therefore, stylized interference will be the worst in longer strings, and the duration of stylized interference will be 32-NAND The duration of the string is twice the duration of the 16-NAND string and eight times the duration of the 8-NAnd string. Figure 14A illustrates a NAND string 1400 with 64 memory elements. In an embodiment, additional isolated word lines are used to further divide the programmed and/or erased regions. The NAND string 1400 includes a source side select gate 1470 and a drain side select gate 148. 〇, and memory elements 1401, 402, ... 1464, which are disposed in a p-well 149. The parent memory element can be selected via a corresponding word line WL 〇 , WL1 · · · WL63. Assuming that the word line WLX is selected for programmaticization, the stylized voltage Vpgm is applied to the word line. On the source side of the selected memory element, a very low isolation voltage Vis is applied. (about ! to V) to the word line WLX·2 to generate an isolation region, and reduce the gate induced shallow drain GIDL, an intermediate gate protection voltage (about 3 v) vgp will be applied to the word line WLxq . The isolation voltage vis is applied by a predetermined predetermined distance from the selected memory element on the source side (programmed side). A second isolation region is created to the word line WLZ. In addition, the isolation voltage vis is also applied by a predetermined distance on the drain side (the side of the 123781.doc -45-200832411 has been erased). Another second isolation region is created to the word line WLy. In a preferred embodiment, 'reflected in FIG. 14B, the distance between the second isolation region and the selected memory on both sides of the selected memory is the same, and the replacement is It is a sixteen child line. Other configurations can also be used, and the best spacing for different device configurations can be determined by measurement. Thus, a plurality of isolation regions are created to define a plurality of boost regions, which are labeled as region A, region B, region c, and region d. The preferred pass & voltage system Vpass (approx. 8 V) applied to the regions 8 and c is applied to the voltage-passing voltage VpassL in the regions a and D (approximately 6 v to 7 V). Other voltages can also be used. The most important system is that the voltage applied to the regions 8 and D is lower than the voltage applied to the regions B and C. Stylized interference at the word line on either edge of the NAND string (ie, WL0, WL1, WL2, and WL61, WL62, WL63) is more severe and, therefore, applied to the same and lower words. The lower conduction voltage vpassL of the line will sufficiently boost the channel voltage to substantially alleviate stylized interference even if the duration of the stylized interference in the longer string is longer. Since these lower and higher word lines are boosted by VpassL, even with longer strings, the stylized interference can be substantially alleviated. Fig. 14B shows an example of a bias condition used in an example of the correction technique. The leftmost line shows the word line that was selected for stylization. The 64 lines to the right of the selected sub-line display the voltage applied to each of the first twenty sub-line lines (in this example). Therefore, the right side of the first column shows the word line WL 被 selected to be programmed and the stylized voltage Vpgm to which 123781.doc -46 - 200832411 to the word line WLG are applied. Since wu) is closest to the source-word line of the source side, all other storage elements on the right side of the 'n' are not programmed' and do not create any isolation regions towards the source side of the first storage element. A second isolation region is created by applying an isolation voltage U-character line and 5 as described above at a distance of sixteen character lines from the selected word line on the unstylized drain side. As mentioned above, boost voltage

Vpass will be applied to all word lines (WL1 to WL14) between the selected word line and the second isolation point and - a lower boost voltage VpassL will be applied to the outside of the second isolation point All of the word lines of the drain to WL63) 〇 For example, when word line WL19 is selected for programming, then Figure 14B shows the stylized voltage Vpgm applied to WL19. Further, the gate guard voltage vgp is applied to the word line WL18 on the source side just below the selected element line, and the voltage % is isolated. It is then applied to word 7G line WL17, removing a word line from the selected word line on the source side. In addition, the isolation voltage Vis is applied. To the word line wl4, sixteen word lines are separated from the selected word line, and a second isolation area is generated on the source side of the selected word line. Although not shown in Fig. 14B, the isolation voltage % is also applied. To the word line and 4, a sixteen word line is separated from the selected word line, and another second isolation area is created on the negative side of the selected word line. Other variations can also be used. For example, the gate protection voltage Vgp can be applied to the % of isolation voltage to be applied. The word line on either side of the word line. Figure 15A. The use of a single conduction power by a child with a single conduction is intended to be a typical red mb technique. 123781.doc -47- 200832411 Stylizes the bias of a 64-NAND string 1500 when these higher word lines are programmed. In this case, the stylized voltage Vpgm is applied to the word line WL62, and the gate protection voltage Vgp is applied to the WL6i to isolate the voltage vis. It is then applied to the word line WL60. The conduction voltage Vpass is applied to the remaining word lines (word lines W1〇 to WL5 9) in the programmed area and the remaining word lines among the erased areas (the word line boundary is "2" However, under these bias conditions, if the leakage current across the isolation region is large, the effect of the boost voltage will be due to the large channel capacitance on the programmed side and the erased side. The small channel capacitance is attenuated. Figure 1 5B illustrates a modified bias technique that helps to limit the channel capacitance when stylizing higher (or lower) word lines. The stylized voltage Vpgm is again Applied to word line WL62, a gate protection voltage is applied to WL61, and an isolation voltage is applied to word line WL60. This is programmed by applying isolation voltage Vis◦ to word line WLz. A second isolation region is formed on the side, which is located at a predetermined distance from the selected word line. For example, in one embodiment, 16 word lines are separated. This will effectively The program is divided into two isolation zones. A conduction voltage Vpass (about 8 To 1 〇V) will be applied to the word lines on both sides of the selected word line (for example, ^+1 to wl59 and WL63), however, the conduction voltages on the two regions do not have to be the same. A lower conduction voltage VpassL (preferably, Wl v) is applied to the remaining word lines on the source side of the second isolation region (for example, WL0 to WLZ-1). The capacitance on the programmed side of the sea is thus split between the isolation regions and limits the impact of the leakage on the next region. 123781.doc -48- 200832411 Figure 1 illustrates the modified bias technique A variation of the boost channel voltage in the programmed region is usually lower because of the programmed threshold voltage, so a slightly higher conduction voltage is used to compensate for the low channel potential in region B. The stylized voltage Vpgm is applied to the selected word line WLX. An isolation region is generated by applying the isolation voltage Vis. to the word line WLX_2 and applying the gate protection voltage Vgp to the word line WLxu. By applying the isolation voltage Vis. to the word line boundary 1^ and WLy will be in the selected word A second isolation region is created on both sides of the line. In this figure, the isolation boost regions are labeled as region A, region B, region C, and region 〇. Standard conduction voltage Vpass (about 8 V to 10 V) will be applied in the region c. A slightly higher conduction voltage VpassH (about 1 V to 2 V higher than Vpass) will be applied to the word line in the source side boost region B (about 6 V to 7 V). A slightly lower conduction voltage, VpassL (approximately Vpasd & 1 V to 2 V), is applied to the remaining regions A and D. This configuration compensates for the low channel potential in region B. Figure 17 illustrates A further variation of the biasing technique is modified. This is similar to the configuration shown in Figure 14A, except that more than one word line is used to create the second isolation regions. Therefore, the stylized voltage Vpgm is applied to the selected word line WLX. By applying an isolation voltage Vis. An isolation region is created by the word line WLX·2 and the application of the gate protection voltage Vgp to the word line. By applying an isolation voltage vis. The word lines WLZ and WL/E located at a specific distance from the selected word line enhance the second isolation region on both sides of the selected word line. In this embodiment, the second isolation region is generated by applying a gate protection voltage V Α μ 一 私 至 兀 兀 WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL WL The conduction voltage VIII... is applied to the word line among the regions ^ and C and the lower conduction voltage VpassL is applied to one of the regions VIII and 1), and the configuration is facilitated via the region B. The isolation region and the GIDL in D are used to reduce the leakage current. Other variations can also benefit. For example, the interpole protection power 2 vgp can be applied to both sides of the word line to which the isolation voltage is applied. The upper sub-line 'for example' is applied to the milk W and the machine z, then Vgp will be applied to WLx_3 and WLw and 诳 WLZ+1. ..., in another example, Applying a conduction voltage to the word line on the source side of the selected word field. Thus, for example, if the target is added to WL62, then it will be applied to wl^, 丨(9) will be Applied to WL6〇, Vis. will be applied to wl59. The detailed description of the invention has been presented herein for explanation and explanation. The invention is not intended to be exhaustive or to limit the invention to the disclosed form. Many modifications and variations are possible in light of the above teachings. The specific embodiments set forth herein are selected to best explain the invention. The present invention may be applied to a person skilled in the art using the present invention in various embodiments and in various modifications to the specific usage contemplated. It is intended that the present invention be The scope of the patent application is defined. [Simplified Schematic] Figure 1 is a top view of a non-volatile memory NAND string. 123781.doc -50- 200832411 Figure 2 is an equivalent circuit diagram of the NAND string of Figure 1. A circuit diagram for illustrating three NAND strings. Figure 4 is a block diagram of a particular embodiment of a flash memory system that can be used to implement one or more embodiments of the present invention. Figure 5 illustrates a memory An example of the organization of an array. Figure 6 depicts an example of a stylized voltage signal.Figure 7 is a flow chart illustrating a specific embodiment of a stylized program. A set of threshold voltage distribution paradigms in a multi-state device that is directly programmed from the erased state to the programmed state. Figure 8B shows a multi-state in a double-pass programmed from the erased state to a programmed state. A set of threshold voltage distribution examples in the device. Figures 9A through 9C show various threshold voltage distributions and illustrate a program for stylizing non-volatile memory. Figure 9D is a timing diagram for explaining a typical stylized program. Figure 10 illustrates a NAND string with unbalanced boost channel regions when using the EASB boost mode.Figure 11 illustrates a NAND string with balanced boost channel regions. Figure 12 illustrates a nand string with an isolation region between the boost channel regions. Figure 13 illustrates a NAND string with an alternate isolation region between boost channel regions. Figure 14A illustrates the use of modified rEASB| to bias a 64-NAND string using additional isolation regions. Figure 14B is a table showing bias conditions for a plurality of characters 123781.doc • 51 - 200832411 lines using the REASB technique of Figure 14a. Figure 15A illustrates the biasing of a 64-NAND string when the higher word lines are programmed using conventional REASB techniques. Figure 15B illustrates the biasing of a 64-NAND string when the higher ideology lines are programmed using the modified REASB technique. Figure 16 illustrates the use of a modified version of the modified REASB technique to bias a 64-N. AND string. Figure 17 illustrates a schematic diagram of biasing a 64-NAND string using another variation of the modified REASB technique. [Main component symbol description] 100 transistor 100CG control gate 100FG floating gate 102 transistor 102CG control gate 102FG floating gate 104 transistor 104CG control gate 104FG floating gate 106 transistor 106CG control gate 106FG floating gate 120 |Select Gate 120CG Control Gate 123781.doc -52- 200832411 122 122CG 126 128 201 202 203 204

206 220 222 224 226 228 230 240 242 244 246 248 250 260 262 123781.doc Select gate control gate bit line contact source line contact NAND string bit line NAND string bit line NAND string bit line selection Transistor memory element memory element memory element memory element selection transistor selection transistor memory element memory element memory element memory element selection transistor selection transistor memory element -53- 200832411 264 memory element 266 Memory Element 268 Memory Element 270 Selective Crystal 302 Memory Element Array 304 Row Control Circuit 306 Column Control Circuit 308 P Well Control Circuit 310 C Source Control Circuit 3 12 Data Input/Output Buffer 314 Command Circuit 315 Control Circuit System 316 state machine 3 18 controller 1000 NAND string 1005 P well region 1010 selection gate 1015 memory component 1020 memory component 1025 memory component 1030 memory component 1035 memory component 1040 memory component 1045 memory component 123781.doc - 54· 200832411

1050 Memory Element 1055 Select Gate 1100 NAND String 1105 p Well Area 1110 Select Gate 1115 Memory Element 1120 Memory Element 1125 Memory Element 1130 Memory Element 1135 Memory Element 1140 Memory Element 1145 Memory Element 1150 Memory Component 1155 Select Gate 1200 NAND String 1205 P Well Area 1210 Select Gate 1215 Memory Element 1220 Memory Element 1225 Memory Element 1230 Memory Element 1235 Memory Element 1240 Memory Element 1245 Memory Element -55- 123781.doc 200832411 1250 1255 1300 1305 • 1310 , 1315 1320 1325 # 1330 1335 1340 1345 1350 1355 1400 1401 φ 1402

1464 1470 1480 1490 1500 SGD SGS WL0-WL63 Memory Element Selection Gate NAND String ρ Well Area Selection Gate Memory Element Memory Element Memory Element Memory Element Memory Element Memory Element Memory Element Memory Element Selection Gate Polar NAND string memory element memory element memory element selection gate selection gate P well area NAND string no pole selection line source selection line word line 123781.doc -56-

Claims (1)

200832411 X. Patent application scope: 1' - #心程m non-volatile storage element isolation and such non-volatile storage (4): Zone 'where the first channel zone and the second channel zone = at least three channel components, and , s, dad sin near - the selected storage while the second channel area is far from the selected potential to enhance each channel area, Α中 / storage components; system utilization is lower than the first and second: second The potential of the zone is increased. The boost voltage of the potential of the & 2 is as requested by the method of the requester, which uses the flute to "use the potential of the two-channel area with the 箓-曰广忒 and the second-channel area of the younger brother. The voltage is boosted. 3. According to the method of claim 2, the voltage is boosted by the voltage in the middle. The middle 4 brother - the external voltage is slightly larger than the second 4. If the request voltage is large, the voltage is > The first boost voltage is approximately one to two volts greater than the second boost package I. 5 • As claimed in claim 1, < 10,000, wherein the first one is selected on the opposite side of the storage element on which the money is selected. 6 · If the request item $ 俜 俜 uses the method 'where the potential of the first- and second channel regions is boosted by the second boosting ink, and the potential of the third channel region is tied to the voltage To boost, and wherein the first boost voltage is slightly greater than the 3 boost voltage. 7. If the request item 5 is A, it further comprises: 4: using the first use of the boost voltage to boost the potential of the first channel region, external voltage to increase the potential of the second channel region, and 123781 .doc 200832411 uses a second boost voltage to boost the potential of the third channel region, wherein the third boost voltage is greater than the first boost voltage, and the second boost voltage is greater than the second boost voltage. 8. In the method of claim 7, the third boost voltage is slightly larger than the third boost voltage. 9. The method of claim 8, wherein the third boost voltage is about one to two volts greater than the first boost voltage. 10. The method of claim 7, further comprising: isolating - a fourth channel region, wherein the fourth channel region is remote from the selected storage element and is located adjacent to the third channel region, and wherein the second channel region The system is located beside the first channel region; the first boost voltage is used to boost the potential of the fourth channel region. 11. The method of claim 1, further comprising: ??? increasing a potential of the first channel region with a third boost voltage, wherein the third boost voltage is greater than the first boost voltage. 12. The method of claim 1, wherein the isolating step comprises: ^ isolating a voltage to a first storage 7C member located at a proximal end of the selected storage element and applying to a first storage located at a distal end of the selected storage element element. 13. The method of claim 12, wherein the step of isolating comprises: a gate protection voltage to a third storage element located just adjacent to the first storage element and applied to the side of the second storage element Fourth storage element. 14. The method of claim 1, wherein the isolating step further comprises: 123781.doc 200832411 applying a gate protection voltage to the second and fourth stores located just above the opposite side of the first storage element The components are applied to the fifth and sixth storage elements just above the opposite side of the second storage element. The method of claim 12, wherein the step of boosting comprises: applying a first boost voltage to a storage element located at a location corresponding to the first and second channel regions, and applying the second boost The voltage is to a storage element located at a location corresponding to the second channel region. 16. A system for programming a set of non-volatile storage elements, comprising: a plurality of non-volatile storage elements; a logic circuit that is in communication with the storage elements, wherein the management circuit isolates and At least three channel regions associated with the non-volatile storage element, wherein the first channel region and the second channel region are adjacent to a selected storage piece, and the third channel region is remote from the selected storage element, and S enhances each The potential of the channel region, wherein the potential of the third channel region is boosted by a boost voltage that is lower than the potential of the first and second channel regions. 17. The system of claim 16, wherein the potentials of the first and second channel regions are boosted by the management circuit using a first boost voltage, and the potential of the third channel region is utilized The second boost voltage is boosted. 1 8 as claimed in claim 1 wherein the first boost voltage is slightly greater than the second boost voltage. 19. The system of claim 18, wherein the first boost voltage is about one to two volts greater than the second boost voltage. 2 0 · If the request item & i i μ t , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The system of 20: wherein the potentials of the first and second channel regions are boosted by the management circuit using a first boost voltage, and the potential of the third region is utilized by the management circuit The second boost voltage is boosted, and wherein the first boost voltage is slightly greater than the second boost voltage. "The system of the priest 20, in which the management circuit will use the third boosting power: to: raise the potential of the first channel region, and use the first boosting voltage to raise the second channel region of the ό ό ,, -曰^ 1 扪 using a voltage of the brother to increase the potential of the third channel region, 1 φ 筮 曰 曰 where the second boost voltage is greater than the first boost voltage and the first boost voltage is greater than the second Boost voltage 23. As in the system of claim 22, the voltage of the second voltage of the 曰中44 brother is slightly larger than the first boosting voltage. 24·The system of claim 23, 1 曰, Τ 弟二二The voltage of the voltage is about one to two volts greater than the first voltage of the same voltage. ^ 25. The system of claim 20, 1 of which, the mouth of the mouth is further isolated from the fourth: the road area, and used a second rising electric dust to raise the potential of the fourth channel region, wherein the fourth channel region is away from the selected storage element and is located in the third channel - ^ ^ and wherein the third channel region is located Beside the first passage area. 26. As in the system of claim 25, Gans-. The official circuit further uses the third boosting voltage to boost the potential of the skirt, wherein the third boost voltage is greater than the first boost voltage. 27. The system of claim 16,苴,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, The second storage element. The system of claim 27, wherein the management circuit applies a voltage to the third storage element I located just next to the first storage element, and is applied to the JL, which is located in the 筮-heart__, a defective component Next to the fourth storage element. 29. The rut of claim 27, Gans-- 糸' wherein the management circuit applies a gate protection to the side of the opposite side of the first storage element. Third and fourth storage elements and applied to the fifth and sixth storage elements located on the opposite side of the second storage element. The system of claim 27, wherein the management circuit applies the - boost And a voltage to a storage element located at the first and second channel regions and applying the second boost voltage to a storage element located at a location corresponding to the third channel region. 123781.doc