TW200823767A - Integrated circuit card and manufacturing method thereof - Google Patents

Integrated circuit card and manufacturing method thereof Download PDF

Info

Publication number
TW200823767A
TW200823767A TW95143649A TW95143649A TW200823767A TW 200823767 A TW200823767 A TW 200823767A TW 95143649 A TW95143649 A TW 95143649A TW 95143649 A TW95143649 A TW 95143649A TW 200823767 A TW200823767 A TW 200823767A
Authority
TW
Taiwan
Prior art keywords
groove
antenna
wafer
wafer module
card
Prior art date
Application number
TW95143649A
Other languages
Chinese (zh)
Inventor
Jen-Hung Wang
Chun-Hsiung Huang
Original Assignee
Gd Teco Taiwan Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gd Teco Taiwan Co Ltd filed Critical Gd Teco Taiwan Co Ltd
Priority to TW95143649A priority Critical patent/TW200823767A/en
Publication of TW200823767A publication Critical patent/TW200823767A/en

Links

Abstract

An integrated circuit card and manufacturing method thereof is disclosed. The integrated circuit card preferably is a combination card and comprises: a substrate having an antenna therein, wherein the antenna has two electric connections; an outer cave and an inner cave formed on the substrate; two holes formed on the outer cave so as to disclose the two electric connections of the antenna; a tin paste applied on the two holes; and a chip module disposed on the outer cave.

Description

200823767 九、發明說明: 【發明所屬之技術領域】 本發明係有關於一種晶片卡及其製造方法,尤其是一 種藉由錫貧結合卡體與晶片模組之雙介面卡及其製造方 法0 【先前技術】 雙介面卡(Combination Card)為一種利用單顆晶片而同時 擁有接觸式與非接觸式功能之晶片卡,其内含的晶片可以 同時處理接觸式或非接觸的指令與傳送資料等動作。 -般而言’雙介面卡在製造過程中必須進行將晶片模 纽與卡體結合的「植晶加工」步驟。雖然先前技術已提出 =些關於「植晶加工」之製程方法,然而這些方法皆存在 者問題。 舉例而言,先前技術已揭露一種以導電膠布/導電膠 ❿(aCF/ACP)將晶片模組與卡體結合的方法,其優點為該^ 法制廣泛’並且材料取得容易;然而其缺點則為:材料 成本禹、製成產品之可靠度不佳、時間久容易變質以 法將晶片取出重製。 、 …、 此外,先前技術也揭露一種以銀膠(SilverEp〇x力將曰 片模組與卡體結合的方法,其優點為··銀膠種類多,可= 擇性多並且銀膠在電子業界使用廣泛;然而其缺點則為.、 卡片加工問題多、時間久會變脆、材料成本高 晶片取出重製。 …、法將 5 200823767 再者’先前技術也揭露一種以彈性導電膠(Flexiebump) 將晶片模組與卡體結合的方法,其優點為彈性導電膠本身 有彈丨生較處抵抗彎扭曲之應力並且應可將晶片取出重製; 然而其缺點則為··材料成本高、材料保存不易以及加工困 難度高。 另外’先前技術也揭200823767 IX. Description of the Invention: [Technical Field] The present invention relates to a wafer card and a method of manufacturing the same, and more particularly to a dual interface card using a tin-poor bonded card body and a wafer module and a method of manufacturing the same Prior Art A dual interface card (Combination Card) is a wafer card that utilizes both a single chip and a contact and non-contact function. The chip contained therein can simultaneously process contact or non-contact commands and transfer data. . In general, the double interface card must be subjected to a "phytolithography" step of bonding the wafer mold to the card body during the manufacturing process. Although the prior art has proposed some process methods for "phytolithography", these methods all have problems. For example, the prior art has disclosed a method of bonding a wafer module to a card body with a conductive adhesive tape/conductive paste (aCF/ACP), which has the advantage that the method is extensive and the material is easy to obtain; however, the disadvantage is : The material cost is 禹, the reliability of the finished product is not good, and the time is prone to deterioration and the wafer is taken out and remade. In addition, the prior art also discloses a method of combining silver foil (SilverEp〇x force to combine the enamel module with the card body, the advantage of which is that there are many types of silver glue, and the degree of sputum is more selective and the silver glue is in the electronic The industry is widely used; however, its shortcomings are: card processing problems, time will become brittle, material cost is high, and wafers are taken out and reworked. ..., Law 5 200823767 In addition, 'previous technology also discloses a flexible conductive adhesive (Flexiebump) The method of combining the wafer module and the card body has the advantage that the elastic conductive adhesive itself has the stress of resisting the bending distortion and the wafer can be taken out and reworked; however, the disadvantage is that the material cost is high. The material is not easy to store and the processing is difficult.

=晶片模組與卡體結合的方法,其優點為:珲接製程已十 分成熟、產品可靠度極佳、焊錫種類可選擇性多、焊錫材 枓成本低廉、設備簡單、投入成本低、不易有冷焊發生、 ==收重製、然而其缺點則為:手工作業方式產能 低及日日片須先進行預焊接(Pre-soldering)。 將曰技術也揭露一種以增層法(B哪P_s) 卡體結合的方法,其優點為··晶片模組與天 法之二然而其缺點則為:此方法為完全不同作 法之1程’無法結合—般現行之工序安排 險高(因為係連同晶片模組 二風 裁切誤差等問題)。 肩早杈裁切,會有 因此,實在有必要針對 種新的晶片卡及其製造方法 題。 植晶加工」之製程提供另一 ’以改善先前技術所存在之問 【發明内容】 晶 鑑於先前技術所存在 片卡及其製造方法,以 6 200823767 製程所存在之問題。 i先’本發明提供一種晶片卡製造方法,用以將晶片 模=與卡體結合以形成晶片卡,其主要包含以下步驟: 1·提供-卡體’其中該卡體之—内層設置有一天線。 2.在卡體上形成一外層凹槽與一内層凹槽。 凹槽中形成二孔,以顯露天線之二電性接點。 4.靶加錫貧於二孔中。 模組,並將晶片模組設置於外層凹槽中。 •、曰曰片板組猎由錫膏結合於外層凹槽内,並使晶片模电 與天線電性連接。 、 本發明提供一種晶片卡,其係藉由上述製造方 4一 。本發明之晶片卡包含:-卡體,其内層設置有 槽H该天線包含二電性接點;一外層凹槽與一内層凹 i之:電::體上;二孔,形成於外層凹槽中’以顯露天 線之一電性接點;—錫膏,施加於二孔中; 其係藉由錫膏而处^ 3片核、、且’ 線電性連接 外層凹槽内’並且晶片模組係與天 【實施方式】 易懂為上述和其他㈣、特徵和優點能更明顯 明如下。“出較佳實施例並配合所附圖式,作詳細說 百先,睛參考圖1闕於本發明之晶片卡之製 步驟流程圖。如1k方法之 如圓1所示’本發明之方法包含步驟_、 7 200823767 S102、S103、Sl〇4、S105以及S106,以下將進一步說明各 個步驟之詳細流程。 如圖1所示,本發明首先進行步驟S101,提供一卡 體。其中,在步驟S101中,本發明所提供之卡體係一雙介 面卡之卡體,亦即其内層包含以熱壓合(lamination)之方式 設置之天線,但本發明並不以此為限。 接著’本發明進行步驟S102,在卡體上形成一凹槽。 如圖2所示,在步驟S102中,本發明係在卡體10上先形成 一外層凹槽12後,再於外層凹槽12中形成一内層凹槽14。 在本發明之一實施例中,外層凹槽12及内層凹槽14可以銑 孔方式形成,但本發明並不以此為限。 接著,本發明進行步驟S103,在凹槽中形成至少一 孔,以顯露天線之至少一電性接點。如圖3所示,在本發 明之一實施例中,本發明在步驟sl〇3中係在卡體1〇之外層 凹槽12中相對應於天線之二電性接點181及182處形成二 孔161及162,並將天線之絕緣層刮除,以使埋置在卡體 10中之天線之二電性接點181及182可透過孔161及162 而顯露出來。此處需注意的是,在圖3的實施例中,步驟 S103係形成相對應於天線之兩個電性接點181及182之兩 個孔161及162,但本發明並不以此為限。 接著,本發明進行步驟S104,施加錫膏於至少一孔 中,以供進一步藉由錫膏將晶片模組與卡體結合。如圖4 所不,在本發明之一實施例中,本發明在步驟§1〇4中係在 孔161及162中施加錫膏191及192。在本發明之一實施 8 200823767 例中,本發明係先預設錫膏191及192之點膠量大小及位 置後,再以定量點膠系統將定量之錫膏191及192點於孔 161及162中,但本發明並不以此為限。 接著,本發明進行步驟sl〇5,提供晶片模組,並將晶 片模組設置於凹槽中。如圖5所示,在步驟娜中,本發 明係提供一外形與外層凹槽12相配合的晶片模組2〇,並將 晶片模組20設置於外層凹槽12中。在本發明之一實施例 中,本發明係藉由將晶片模組20自一捲帶中取下,並以真 空吸盤與機械手臂將取下之晶片模組2〇置入外層凹槽 中。此外,在晶片模組2〇已置入外層凹槽12中後本發明 逛可輕微加熱晶片模組2〇,以初步固定晶片模組2〇於外層 凹槽12中,以方便進行後續的步驟,但本發明並不以此為 限此外在本鲞明之一實施例中,晶片模組2〇已於里背 面先行貼上熱融膠帶(圖未示),但本發明並不以此為 限。 _ #著,本發明進行步驟遍,將晶片模組藉由錫膏結 s於凹槽内’並使Ba片模組與天線電性連接。在步驟$觸 中,本發明係藉由下列方式,而將晶片模組與卡體結合, 並與天線電性連接: 1·在一預設之溫度、時間及壓力下,施加一熱燙頭於 晶片模組上,以使晶片模組與天線之至少一電性接點充分 接合。 2·在一預設之溫度、時間及壓力下,施加一冷卻頭於 晶片模組上,以使晶片模組與天線之至少一電性接點充分 9 200823767 冷卻固化。 在本發明之一實施例中,上述之加溫、加壓及冷 驟係可依如圖7所示之錫膏之溫度特性而進行,㈣ 亚不以此為限。 乃 =步驟讓後,本發明即可如圖6所示,藉由锡膏The method of combining the chip module and the card body has the advantages that the splicing process is very mature, the product reliability is excellent, the solder type can be more selective, the solder material is low in cost, the device is simple, the input cost is low, and it is difficult to have Cold welding occurs, == weight-receiving system, but its shortcomings are: manual operation, low productivity and daily pre-soldering. The 曰 technique also exposes a method of combining layers (B), which has the advantages of a wafer module and a celestial method. However, the disadvantage is that this method is a completely different process. It is impossible to combine the current process arrangement with high risk (because it is related to the problem of the second wind cutting error of the wafer module). The shoulders are cut early and there will be a need for a new wafer card and its manufacturing method. The process of phytolithography provides another problem to improve the prior art. [Summary of the Invention] In view of the prior art, the chip card and the method of manufacturing the same, the problem of the process of 6 200823767. The present invention provides a method for manufacturing a wafer card for combining a wafer die=with a card body to form a wafer card, which mainly comprises the following steps: 1. Providing a card body, wherein the card body is provided with an antenna . 2. Forming an outer groove and an inner groove on the card body. Two holes are formed in the groove to display two electrical contacts of the open circuit. 4. Target tin is poor in two wells. The module and the wafer module are disposed in the outer groove. • The cymbal plate group is soldered to the outer groove by a solder paste, and the die is electrically connected to the antenna. The present invention provides a wafer card which is manufactured by the above-mentioned manufacturer. The wafer card of the present invention comprises: a card body having an inner layer provided with a groove H. The antenna comprises two electrical contacts; an outer groove and an inner layer concave i: electric: body; two holes formed in the outer concave In the slot, 'the electrical contact is one of the open-air lines; the solder paste is applied to the two holes; the solder paste is used to place the three cores, and the 'wire is electrically connected to the outer recess' and the wafer Module system and day [Embodiment] It is easy to understand that the above and other (four), features and advantages can be more clearly as follows. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to the preferred embodiment and in conjunction with the drawings, a detailed flow chart of the steps of the wafer card of the present invention will be described with reference to Figure 1. The method of the present invention is as shown in Figure 1 of the 1k method. Including steps _, 7 200823767 S102, S103, S1 〇 4, S105 and S106, the detailed flow of each step will be further explained below. As shown in Fig. 1, the present invention first performs step S101 to provide a card body. In S101, the card system provided by the present invention has a card body of a double interface card, that is, the inner layer thereof comprises an antenna arranged by thermal lamination, but the invention is not limited thereto. Step S102 is performed to form a groove on the card body. As shown in FIG. 2, in step S102, the present invention forms an outer groove 12 on the card body 10, and then forms a groove in the outer layer groove 12. The inner layer groove 14. In an embodiment of the invention, the outer layer groove 12 and the inner layer groove 14 can be formed by milling, but the invention is not limited thereto. Next, the invention proceeds to step S103, in the groove Form at least one hole in the open to the open line One less electrical contact. As shown in FIG. 3, in an embodiment of the present invention, the present invention corresponds to the second electrical property of the antenna in the outer layer groove 12 of the card body 1 in step s1〇3. Two holes 161 and 162 are formed at the contacts 181 and 182, and the insulating layer of the antenna is scraped off so that the two electrical contacts 181 and 182 of the antenna embedded in the card body 10 can be exposed through the holes 161 and 162. It should be noted that, in the embodiment of FIG. 3, step S103 forms two holes 161 and 162 corresponding to the two electrical contacts 181 and 182 of the antenna, but the present invention does not Next, the present invention proceeds to step S104, applying a solder paste to at least one hole for further bonding the wafer module to the card body by solder paste. As shown in FIG. 4, in an embodiment of the present invention In the present invention, in the steps §1 to 4, the solder pastes 191 and 192 are applied to the holes 161 and 162. In one embodiment of the present invention, 8200823767, the present invention first presets the amount of solder paste of the solder pastes 191 and 192. After the size and position, the quantitative solder pastes 191 and 192 are spotted in the holes 161 and 162 by a quantitative dispensing system, but the invention is not limited thereto. Next, the present invention performs step s1, 5, provides a wafer module, and sets the wafer module in the groove. As shown in FIG. 5, in the step, the present invention provides an outer shape matching the outer layer groove 12. The wafer module 2 is disposed and the wafer module 20 is disposed in the outer layer recess 12. In one embodiment of the invention, the present invention is obtained by removing the wafer module 20 from a roll and The vacuum chuck and the robot arm place the removed wafer module 2 into the outer groove. Further, after the wafer module 2 is placed in the outer groove 12, the present invention can slightly heat the wafer module 2〇. The preliminary fixing of the wafer module 2 is performed in the outer layer groove 12 to facilitate the subsequent steps, but the invention is not limited thereto. In addition, in one embodiment of the present invention, the wafer module 2 is disposed on the back surface. The hot melt tape (not shown) is attached first, but the invention is not limited thereto. _#, the present invention performs the steps of electrically connecting the wafer module to the antenna by solder paste s in the recess. In the step $ touch, the present invention combines the wafer module with the card body and electrically connects with the antenna by the following means: 1. Applying a hot stamping head under a preset temperature, time and pressure. The chip module is configured to fully engage at least one electrical contact of the wafer module and the antenna. 2. Apply a cooling head to the wafer module at a predetermined temperature, time and pressure to allow at least one electrical contact between the wafer module and the antenna to be fully cooled. In one embodiment of the present invention, the above-mentioned heating, pressurization and cooling may be carried out according to the temperature characteristics of the solder paste as shown in Fig. 7, and (4) is not limited thereto. After the step is made, the invention can be as shown in Fig. 6, by solder paste.

將日日片模組20鱼卡I#〗〇同宁址入 J 擎結曰,/ 相較於切技術之銀膠 l^t ,本發明之製造方法不但晶片卡之植晶加 > 2衣^易、產能提高,而且還能達成製程穩定、加工良 率及產品可靠度均大幅提高之效果。 片卡接提供一種藉由上述製造方法所形成之晶 卡^考圖8關於本發明之晶片卡之示意圖。如圖8 所不,本發明之晶片卡1包 讲署古一工成1〇 下匕3卡體10,該卡體10之内層 口又置有天線1 8,該夭绩1只治人| 1〇, μ 茨大線18包含至少一電性接點181及 & °卡體ίο上有-外層凹槽12及—内層凹槽14 161及162係相對應於電性接·點⑻及182之位置而妒1 •於外層凹槽12中。孔161月 ^ 7成The Japanese film module 20 fish card I#〗 〇 宁 址 入 入 入 J J J 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰 曰The clothing is easy, the production capacity is improved, and the effect of stable process, high processing yield and product reliability is greatly improved. The chip card provides a crystal card formed by the above manufacturing method. Fig. 8 is a schematic view of the wafer card of the present invention. As shown in Fig. 8, the wafer card 1 package of the present invention has a 1st 〇3 card body 10, and the inner layer of the card body 10 is also provided with an antenna 1-8. 1 〇, μ 大 线 18 includes at least one electrical contact 181 and & ° card body ίο on the outer layer groove 12 and the inner layer groove 14 161 and 162 corresponds to the electrical connection point (8) Position 182 and 妒1 • in the outer groove 12. Hole 161 months 70%

162中具有錫膏191及192 , 並且晶片模組2〇係藉由錫膏J 及192而結合於外層凹梓 12内,以使晶片模組2〇盘 m 性連接。 /、天線18之電性接點181及182電 雖然本發明已以較佳眘 限定太恭昍/乂古、 例揭鉻如上,然其並非用以 X 壬可熱習此技術者,在不脫離本發明之精神 和範圍内,當可作些誶夕、 令知Θ之積神 ^ " 更動與潤飾,因此本發明之伴鳟 範圍當視後附之申請專刺r R &田 个义月之保漢 丁月寻利乾圍所界定者為準。 200823767 【圖式簡單說明】 圖1為本發明之晶片卡之製造方 m 0 ^ 以及忐之步驟流程圖 凹槽之示 圖2為依據本發明之製造方法,在卡體上形成一 圖3為依據本㈣之製造方法,細射形成至少一 示意圖。 〈 圖4為依據本㈣之製造方法,在至少—孔中施加锡膏之 示意圖。 圖5為依據本發明之製造方法,提供晶片模組並將晶片模 組設置於凹槽中之示意圖。 圖6為依據本發明之製造方法,藉由錫膏將晶片模組與卡 體固定結合之示意圖。 圖7為錫膏之溫度特性曲線圖。 圖8為本發明之晶片卡之示意圖。162 has solder pastes 191 and 192, and the wafer module 2 is bonded to the outer recess 12 by solder pastes J and 192 to make the wafer module 2 m-connected. /, the electrical contacts 181 and 182 of the antenna 18, although the present invention has been more carefully limited to be too respectful / eternal, the case of chrome as above, but it is not used to X 壬 can learn this technology, not Without departing from the spirit and scope of the present invention, it is possible to make some enthusiasm and to make a sense of enthusiasm and refinement. Therefore, the scope of the invention is attached to the application of the special thorn r R & The definition of the righteous month of the Han Dynasty is determined by the definition of the right to do. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a manufacturing process of a wafer card of the present invention, m 0 ^ and a step of a flow chart. FIG. 2 is a manufacturing method according to the present invention, and a method is formed on the card body. According to the manufacturing method of the above (4), at least one schematic is formed by fine shot. Fig. 4 is a schematic view showing the application of a solder paste in at least a hole in accordance with the manufacturing method of the above (4). Figure 5 is a schematic illustration of a method of fabricating a wafer module and placing a wafer module in a recess in accordance with the method of the present invention. Fig. 6 is a schematic view showing the wafer module and the card body being fixedly bonded by solder paste according to the manufacturing method of the present invention. Figure 7 is a graph showing the temperature characteristics of the solder paste. Figure 8 is a schematic illustration of a wafer card of the present invention.

【主要元件符號說明】 晶片卡1 卡體10 外層凹槽12 天線18 孔 161、162 晶片模組20 内層凹槽14 電性接點181、182 鍚膏 191 、192[Main component symbol description] Wafer card 1 card body 10 outer groove 12 antenna 18 hole 161, 162 chip module 20 inner layer groove 14 electrical contact 181, 182 钖 cream 191, 192

Claims (1)

200823767 十、申請專利範園·· 丄種曰曰片卡之製造方法,用以將一晶片模組與一 t體結合以形成-晶片卡,該方法包含以下步驟: k供遠卡體,其中 ^ r茨卞體之一内層設置有一天線,· 在禮卡體上形成一凹槽; 在口亥凹槽中形成至少一孔,以顯露該天線之至少一電性接 點; 施加錫膏於該至少一孔中· >提供該晶片模組; 否又置该晶片模組於該凹槽中;以及 將該晶片模組藉由該錫膏結合於該凹槽内,並使該晶片模 組與該天線電性連接。 2'如中請專利範圍第1項所述之方法,其中該凹槽包含 一外層凹槽以及1層凹槽’並且該至少—孔係形成於該 外層凹槽中。 3、如中請專利範圍第1項所述之方法,其中該天線係以 熱壓合(lamination)之方式設置於該卡體之該内層。 4 :如申請專利範圍第1項所述之方法,其中在施加錫膏 於忒至J 一孔中之步驟中,係先預設錫膏之點膠量大小及 位置後,再將定量之錫膏點於該至少一孔中。 5曰、如/請專利範圍第!項所述之方法,其中係藉由將該 晶片模組自一捲帶中取下,以提供該晶片模組。 6、如申請專利範圍第1項所述之方法,其中係藉由-真 二及ia»與機械手臂,以設置該晶片模组於該凹槽中。 12 200823767 7、 如申請專利範圍第1項所述之 万去,其中在設置該晶 片模組於該凹槽中之步驟後,進一牛4 ^ 步包含以下步驟: 加熱該晶片模組,以初步固定該曰η # & μ » 心硪日日片板組於該凹槽中。 8、 如申請專利範圍第1項所述之太本 ^延之方法,其中在將該晶片 模組藉由該鍚膏結合於該凹槽内之步驟中,係包含以下步 驟: 在一預設之溫度、時間及壓力下,始+ #1 如 生刀卜轭加一熱燙碩於該晶片 模組上,以使該晶片模組鱼續壬綠夕兮 、 门伏、五,、邊大綠之该至少一電性接點充 胃分接合; f一預設之溫度、時間及壓力下,施加—冷卻頭於該晶片 杈組上,以使該晶片模組與該天線之該至少一電性接點充 分冷卻固化。 9、 一種晶片卡,包含: 一卡體,該卡體之一内層設置有一天線,該天線包含至少 一電性接點; 馨一凹槽,形成於該卡體上; 至少一孔,形成於該凹槽中,以顯露該天線之該至少一電 性接點; 一錫Ί* ’施加於該至少一孔中; 一晶片模組,該晶片模組係藉由該錫膏而結合於該凹槽 内,並且該晶片模組係與該天線電性連接。 10、 如申請專利範圍第9項所述之晶片卡,其中該凹槽包 含一外層凹槽以及一内層凹槽,並且該至少一孔係形成於 該外層凹槽中。 13 200823767 11、如申請專利範圍第9項所述之晶片卡,其中該天線係 以熱壓合之方式設置於該卡體之該内層。200823767 X. Application for a patent garden · 制造 之 之 , , , , , , 结合 结合 结合 结合 结合 结合 结合 结合 结合 结合 结合 结合 结合 结合 结合 结合 结合 结合 结合 结合 结合 结合 结合 结合 结合 结合 结合 结合 结合 结合 结合 结合 结合 结合 结合One of the inner layers of the body is provided with an antenna, and a groove is formed on the body of the card; at least one hole is formed in the groove of the mouth to expose at least one electrical contact of the antenna; and the solder paste is applied to the at least Providing the wafer module in a hole; not disposing the wafer module in the recess; and bonding the wafer module to the recess by the solder paste, and bonding the wafer module to The antenna is electrically connected. The method of claim 1, wherein the groove comprises an outer groove and a layer of groove ' and the at least hole is formed in the outer groove. 3. The method of claim 1, wherein the antenna is disposed on the inner layer of the card body by thermal lamination. 4: The method according to claim 1, wherein in the step of applying the solder paste to the hole of the J, the size and position of the solder paste are preset, and then the tin is quantified. Paste in the at least one hole. 5曰, such as / please patent scope! The method of claim 1, wherein the wafer module is provided by removing the wafer module from a roll. 6. The method of claim 1, wherein the wafer module is disposed in the recess by using a true two and an ia» and a robotic arm. 12 200823767 7. As described in the first paragraph of the patent application, after the step of setting the wafer module in the groove, the following steps are included: heating the wafer module to preliminary Fix the 曰η# & μ » 硪 硪 日 日 日 in this groove. 8. The method of claim 1, wherein the step of attaching the wafer module to the recess by the paste comprises the steps of: Under the temperature, time and pressure, the beginning + #1 is like a raw knife yoke plus a hot slab on the chip module, so that the wafer module fish continues to green, the door, the five, the side The at least one electrical contact of the green is filled with the stomach; f is applied to the stack of the wafer at a predetermined temperature, time and pressure so that the wafer module and the antenna are at least one The electrical contacts are fully cooled and solidified. A wafer card comprising: a card body, an inner layer of the card body is provided with an antenna, the antenna comprises at least one electrical contact; a recess is formed on the card body; at least one hole is formed in In the recess, the at least one electrical contact of the antenna is exposed; a tin stamp* is applied to the at least one hole; and a wafer module is bonded to the wafer module by the solder paste The inside of the groove, and the chip module is electrically connected to the antenna. 10. The wafer card of claim 9, wherein the groove comprises an outer groove and an inner groove, and the at least one hole is formed in the outer groove. The wafer card of claim 9, wherein the antenna is thermally bonded to the inner layer of the card body. 1414
TW95143649A 2006-11-24 2006-11-24 Integrated circuit card and manufacturing method thereof TW200823767A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW95143649A TW200823767A (en) 2006-11-24 2006-11-24 Integrated circuit card and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW95143649A TW200823767A (en) 2006-11-24 2006-11-24 Integrated circuit card and manufacturing method thereof

Publications (1)

Publication Number Publication Date
TW200823767A true TW200823767A (en) 2008-06-01

Family

ID=44771298

Family Applications (1)

Application Number Title Priority Date Filing Date
TW95143649A TW200823767A (en) 2006-11-24 2006-11-24 Integrated circuit card and manufacturing method thereof

Country Status (1)

Country Link
TW (1) TW200823767A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI506561B (en) * 2008-11-19 2015-11-01 Internat Frontier Tech Lab Inc Embossed hologram chip and its manufacturing method
CN105846056B (en) * 2016-03-28 2019-04-02 歌尔股份有限公司 A kind of production method of antenna module and a kind of antenna module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI506561B (en) * 2008-11-19 2015-11-01 Internat Frontier Tech Lab Inc Embossed hologram chip and its manufacturing method
CN105846056B (en) * 2016-03-28 2019-04-02 歌尔股份有限公司 A kind of production method of antenna module and a kind of antenna module

Similar Documents

Publication Publication Date Title
TWI363303B (en) Rfid tag manufacturing methods and rfid tags
US8105880B2 (en) Method for attaching a semiconductor die to a leadframe, and a semiconductor device
JP4699353B2 (en) Alternative FLMP package design and package manufacturing method
CN105706236B (en) The manufacturing method of electrode terminal, power semiconductor device and power semiconductor device
JP4479209B2 (en) Electronic circuit device, method for manufacturing the same, and apparatus for manufacturing electronic circuit device
TWI243396B (en) Elemental pieces and complex wiring board using the same
TWI281588B (en) Method for bonding integrated circuit chips and other devices to a liquid crystal display panel, liquid crystal display panels and method of fabricating the same
CN101304017B (en) Sintered high performance semiconductor substrate and corresponding production method
JPH11515120A (en) IC card module and method and apparatus for manufacturing IC card
JP2002203939A (en) Integrated electronic component and its integrating method
TW200807588A (en) Semiconductor device, built-up type semiconductor device using the same, base substrate, and manufacturing method of semiconductor device
TWI304623B (en)
TW200941672A (en) Semiconductor device and method of manufacturing the same
TW200823767A (en) Integrated circuit card and manufacturing method thereof
TW200423389A (en) Manufacturing method of solid-state photographing apparatus
CN105895523A (en) Method for manufacturing semiconductor device
JP3719921B2 (en) Semiconductor device and manufacturing method thereof
CN102163690B (en) Package manufacturing method, piezoelectric vibrator, and oscillator
CN114725247A (en) Preparation method of electrode structure and preparation method of battery string
TW459316B (en) Substrate with wiring layers and method thereof
TW200841429A (en) IC chip package
CN201887726U (en) Multiple row-arrangement composite substrate, frequency device group and frequency device
TWI277184B (en) Flip-chip leadframe type package and fabrication method thereof
CN101197005A (en) Chip card and manufacturing method thereof
TW200921518A (en) Method for producing RFID and structure thereof