200822822 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種電路基板，特別係有關於一種增強 引線抗拉強度之電路基板，可供於半導體封裝之使用。 【先前技術】 按，電路基板（Substrate)可作為一電性互連之晶片載體， 以運用於半導體封裝。積體電路晶片在運算時產生熱量，會 積熱於電路基板，在停止運算後將下降至室溫，形成溫度循 環。ί電路基板處於昇溫與降溫的循環中，電路基板内部產 生熱應力，會有線路斷裂導致電性斷路（circuit broken)之風 險0 如第1及2圖所示，在一種習知的電路基板1〇〇中，在 一基板核心層110上設有複數個連接墊12()與複數個引線 130並以一防銲層140覆蓋之。該些引線丨3〇係可設於該基 板核心層110上並連接對應之該些連接墊12〇至内部導通孔 或是内接墊。該些連接墊120係可作為一積體電路封裝產品 之對外接墊，例如可以接合上銲球或錫膏。該防銲層j 4〇係 覆蓋該些引線130但顯露該些連接墊120之至少一部位。通 常每一引線130係具有一上表面ι31與一下表面132並且具 有矩形截面。該些引線13〇之下表面132係貼附於該基板核 心層110 ;該些引線13〇之上表面131與侧面係被該防銲層 140所覆蓋。然而，隨著高密度配線需求，該些引線13〇之 線寬進一步要求更窄，導致該些引線130之抗拉強度（tensile strength)有弱化現象。當模擬產品運算的熱循環試驗 5 200822822 (Thermal Cycle Test，TCT)中 斷裂處133(如第2圖所示）， 【發明内容】 ，發現部份之引線13〇會產生有 ¥致無法正常運算的電性斷路。 本發明之主要目的係在於提供—種增強引線抗拉強度之 電路基板，克服熱循環試驗中？丨線斷们丨起電性斷路的問 題，特別適用於積體電路封裝之高密度基板。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board, and more particularly to a circuit board for enhancing the tensile strength of a lead wire, which is usable for use in a semiconductor package. [Prior Art] According to the circuit substrate, the substrate can be used as an electrically interconnected wafer carrier for use in a semiconductor package. The integrated circuit chip generates heat during calculation, accumulates heat on the circuit board, and drops to room temperature after the calculation is stopped to form a temperature cycle. ίThe circuit board is in a cycle of temperature rise and temperature drop, thermal stress is generated inside the circuit board, and there is a risk of circuit breakage due to line breakage. 0 As shown in FIGS. 1 and 2, in a conventional circuit board 1 In the crucible, a plurality of connection pads 12 () and a plurality of leads 130 are disposed on a substrate core layer 110 and covered with a solder resist layer 140. The lead wires can be disposed on the substrate core layer 110 and connect the corresponding connection pads 12 to the internal via holes or the inner pads. The connection pads 120 can be used as external pads of an integrated circuit package product, for example, solder balls or solder paste can be bonded. The solder resist layer j 4 covers the leads 130 but exposes at least a portion of the connection pads 120. Typically each lead 130 has an upper surface ι 31 and a lower surface 132 and has a rectangular cross section. The lower surface 132 of the lead 13 is attached to the substrate core layer 110; the upper surface 131 and the side surface of the lead 13 are covered by the solder resist 140. However, with the demand for high-density wiring, the line widths of the leads 13 are further narrower, resulting in weakening of the tensile strength of the leads 130. When the thermal cycle test 5 of the simulation product operation 5, 200822822 (Thermal Cycle Test, TCT) breaks 133 (as shown in Fig. 2), [invention], it is found that some of the leads 13 产生 will have a ¥ can not be normal operation Electrical disconnection. The main object of the present invention is to provide a circuit substrate which enhances the tensile strength of a lead wire and overcomes the heat cycle test. The problem of electrical disconnection is particularly suitable for high-density substrates in integrated circuit packages.
本發明的目的及解決其技術問題是採用以下技術方案來 實現的。依據本發明，—種增強引線抗拉強度之電路基板係 包含-基板核心層、複數個連接墊、複數個引線以及一防鲜 層。該些連接墊係設於該基板核心、層上。該些引線係設於該 基板核心層上並連接至該些連㈣。該防銲層係形成於該基 板核心層上’以覆蓋該些引線但顯露該些連接墊。其中，該 些引線係具有-ϊ型截面，藉此增強該些引線之抗拉強度。 本發明的目的及解決其技術問題還可採用以下技術措施 進一步實現。 在前述的電路基板中，每一引線係可具有一上表面、一 下表面與在兩側之凹入側面。 在前述的電路基板中，該些引線之凹入侧面與上表面係 可被該防銲層所覆蓋。 在前述的電路基板中’另可包含有一介電層，其係位於 該基板核心層與該防銲層之間，以覆蓋該些引線之凹入侧 面。 在前述的電路基板中，該介電層係可包含有該防銲層相 近的防銲材料。 6 200822822 在前述的電路基板中，該些引線之下表面係可貼附於該 基板核心層。 在前述的電路基板中，該些連接墊係可為圓形墊。 在前述的電路基板中，該些引線之一部位係可嵌埋於該 基板核心層内。 【實施方式】 依據本發明之第一具體實施例，揭示一種增強引線 抗拉強度之電路基板。如第3及4圖所示，該增強引線抗拉 強度之電路基板200係包含一基板核心層21 0、複數個連接 墊220、複數個引線230以及一防銲層240。 該基板核心層210係為介電材料，如FR-3、FR-4之玻璃 纖維布含浸樹脂或聚亞醯胺（PI)。依需要間隔的線路層層數 不同，該電路基板200可能會有複數個基板核心層2 1 0。 該些連接墊220係設於該基板核心層2 1 0上，其材質係 為銅或是其它導電物質，以作為對外電性連接接點。在本實 施例中，該些連接墊220係可為圓形墊，可接合銲球或錫膏， 作為積體電路封裝產品之外接端。 該些引線230係設於該基板核心層210上並連接至該些 連接塾220。該些引線230之另一端係可連接至該電路基板 200之導通孔（via)或導電指等等，以達電性互連。該些引線 230之材質亦可為銅或是其它導電物質。 該防銲層240係形成於該基板核心層2 1 〇上，以覆蓋該 些引線230但顯露該些連接墊220。通常在該些連接墊220 之顯露表面係形成有一金屬保護層（圖未繪出），如鎳金、錫、 7 200822822 錫錯等等’用以防止該些連接墊220之氧化並增進對外銲接。 此外，如第3圖所示，該些引線22〇係具有一 I型截面， 並且被該防銲層240覆蓋。在一具體結構中，每一引線22〇 係可具有一上表面23 1、一下表面232與在兩側之凹入側面 233。該些引線230之下表面232係可貼附於該基板核心層 210,該防銲層240係覆蓋該些引線23〇之上表面231。在本 實施例中，該電路基板200另可包含有一介電層25〇，其係 位於該基板核心層210與該防銲層24〇之間，以覆蓋該些引 線230之凹入侧面233。較佳地，該介電層25〇係可包含有 該防銲層240相近的防銲材料，以使該介電層25〇之形成技 術可與該防銲層240相同，有利於製作該介電層25〇。 因此，該些引線220相較於傳統的引線具有更強的抗拉 強度。當運用於積體電路封裝，一積體電路封裝構造係可包 含如前所述之電路基板200,複數個銲球（圖未繪出）更可接 合於該些連接墊220,該些引線23〇之寬度可以設計更窄， 在熱循環試驗中也不易產生斷裂的問題。 參閱第5A至5E圖，進一步具體說明該電路基板2〇〇之 引線230之製作流程。首先，如第5A圖所示，提供一基板 核心層210 ’再壓合上一銅箔’蝕刻該銅箔，以形成該些引 線230之底層234,該底層234之下方即為該些引線23〇之 下表面232。其中上述銅荡之厚度約為該些引線23〇之厚度 之三分之一。之後’如帛5B 所示，以電鑛銅之方式在該 底層234之上方形成一中間層235，該中間層235之寬度係 小於該底層234之寬度，以形成上述之凹入侧面233。之後， 200822822The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. According to the present invention, a circuit board for enhancing the tensile strength of a lead wire comprises a substrate core layer, a plurality of connection pads, a plurality of leads, and a fresh-proof layer. The connection pads are disposed on the substrate core and the layer. The leads are disposed on the core layer of the substrate and connected to the connections (4). The solder resist layer is formed on the core layer of the substrate to cover the leads but expose the connection pads. Among them, the lead wires have a -ϊ type cross section, thereby enhancing the tensile strength of the leads. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the foregoing circuit substrate, each of the lead wires may have an upper surface, a lower surface, and a concave side surface on both sides. In the aforementioned circuit substrate, the concave side surface and the upper surface of the leads may be covered by the solder resist layer. In the foregoing circuit substrate, a dielectric layer may be further disposed between the core layer of the substrate and the solder resist layer to cover the concave side surfaces of the leads. In the foregoing circuit substrate, the dielectric layer may include a solder resist material similar to the solder resist layer. 6 200822822 In the foregoing circuit substrate, the lower surface of the leads may be attached to the core layer of the substrate. In the foregoing circuit substrate, the connection pads may be circular pads. In the foregoing circuit substrate, one of the leads may be embedded in the core layer of the substrate. [Embodiment] According to a first embodiment of the present invention, a circuit board for enhancing the tensile strength of a lead wire is disclosed. As shown in Figs. 3 and 4, the circuit board 200 for enhancing the tensile strength of the lead includes a substrate core layer 210, a plurality of connection pads 220, a plurality of leads 230, and a solder resist layer 240. The substrate core layer 210 is a dielectric material such as FR-3, FR-4 glass fiber cloth impregnated resin or polyamidamine (PI). The circuit substrate 200 may have a plurality of substrate core layers 2 1 0 depending on the number of circuit layers that are spaced apart as needed. The connection pads 220 are disposed on the substrate core layer 210, and are made of copper or other conductive materials to serve as external electrical connection contacts. In this embodiment, the connection pads 220 can be circular pads that can be soldered with solder balls or solder pastes as external terminals of the integrated circuit package product. The leads 230 are disposed on the substrate core layer 210 and connected to the connection ports 220. The other ends of the leads 230 are connectable to vias or conductive fingers of the circuit substrate 200 for electrical interconnection. The wires 230 may also be made of copper or other conductive materials. The solder resist layer 240 is formed on the substrate core layer 2 1 , to cover the leads 230 but expose the connection pads 220. Generally, a metal protective layer (not shown) is formed on the exposed surface of the connection pads 220, such as nickel gold, tin, 7 200822822 tin, etc. to prevent oxidation of the connection pads 220 and to improve external soldering. . Further, as shown in Fig. 3, the leads 22 have an I-shaped cross section and are covered by the solder resist layer 240. In a particular configuration, each lead 22 can have an upper surface 23 1 , a lower surface 232 and recessed sides 233 on either side. The lower surface 232 of the lead wires 230 is attached to the substrate core layer 210, and the solder resist layer 240 covers the upper surface 231 of the leads 23A. In this embodiment, the circuit substrate 200 further includes a dielectric layer 25〇 between the substrate core layer 210 and the solder resist layer 24A to cover the recessed side 233 of the leads 230. Preferably, the dielectric layer 25 can include a solder resist material similar to the solder resist layer 240, so that the dielectric layer 25 can be formed in the same manner as the solder resist layer 240, which is advantageous for fabricating the dielectric layer. The electrical layer is 25 〇. Therefore, the leads 220 have stronger tensile strength than conventional leads. When applied to an integrated circuit package, an integrated circuit package structure may include the circuit substrate 200 as described above, and a plurality of solder balls (not shown) may be further bonded to the connection pads 220, and the leads 23 The width of the crucible can be designed to be narrower, and the problem of cracking is less likely to occur in the thermal cycle test. Referring to Figures 5A through 5E, the fabrication flow of the leads 230 of the circuit substrate 2 is further specified. First, as shown in FIG. 5A, a substrate core layer 210' is further pressed and a copper foil is etched to etch the copper foil to form the bottom layer 234 of the leads 230. The leads 23 are under the bottom layer 234. Under the surface 232. The thickness of the copper ridge is about one third of the thickness of the leads 23 。. Thereafter, as shown in Fig. 5B, an intermediate layer 235 is formed over the underlayer 234 in the form of electrowinning copper, the intermediate layer 235 having a width smaller than the width of the underlayer 234 to form the recessed side 233 described above. After that, 200822822
如弟jc圖所示，利用印刷或沉積技術在該基板核心層川 之外路表面形成該介電層250。特別要注意較，應於該介 電層250形成之時或是以研磨方式顯露該中間層a”。之 後如第5D圖所不，再以電鑛銅之方式在該中間層η $之 上方形成一頂層236,該頂層236之寬度係大於該中間層235 見度該頂層236之一部分可形成於該介電層25〇上，以 =成上述引線230之上表面231並構成引線。最後，如 第5E圖所示，將該防銲層24〇形成於該介電層：⑽上，並 覆蓋該引線230之上表面231，以製得具有！型截面且其凹 入側面233被填實之引線230。 在第一具體貝^例中，揭示另一種增強引線抗拉強度之 電路基板，如第6圖所示，該電路基板3〇〇係包含一基板核 心層310、複數個連接墊（圖未繪出）、複數個引線33〇以及 一防辉層340。 該些連接墊與該些引線330係設於該基板核心層310 上。該防銲層340係形成於該基板核心層3丨〇上，以覆蓋該 些引線330但顯露該些連接墊。並且，該些引線330係具有 一 I型截面。在本實施例中，每一引線330係可具有一上表 面331、一下表面332與在兩側之凹入侧面333。該下表面 3 3 2係貼附於該基板核心層3 1 〇，該些引線3 3 0之凹入侧面 3 33與上表面331係可被該防銲層340所覆蓋。故利用該些 引線330之I型截面與其凹入侧面333被覆蓋之架構，增進 該些引線330之抗拉強度。 在第三具體實施例中，揭示另一種增強引線抗拉強度之 9 200822822As shown in the figure jc, the dielectric layer 250 is formed on the surface of the substrate core layer by printing or deposition techniques. In particular, it should be noted that the intermediate layer a" should be exposed when the dielectric layer 250 is formed or in a polished manner. Thereafter, as shown in FIG. 5D, the intermediate layer η$ is again in the form of electrowinning copper. Forming a top layer 236 having a width greater than the intermediate layer 235. A portion of the top layer 236 can be formed on the dielectric layer 25A to form the upper surface 231 of the lead 230 and form a lead. Finally, As shown in FIG. 5E, the solder resist layer 24 is formed on the dielectric layer: (10) and covers the upper surface 231 of the lead 230 to have a ?-shaped cross section and the concave side surface 233 is filled. The lead wire 230. In the first specific example, another circuit board for enhancing the tensile strength of the lead wire is disclosed. As shown in FIG. 6, the circuit board 3 includes a substrate core layer 310 and a plurality of connecting pads. (not shown), a plurality of leads 33A and an anti-glaze layer 340. The connection pads and the leads 330 are disposed on the substrate core layer 310. The solder resist layer 340 is formed on the substrate core layer. 3丨〇 to cover the leads 330 but reveal the connection pads. The lead wires 330 have an I-shaped cross section. In this embodiment, each of the lead wires 330 may have an upper surface 331, a lower surface 332 and concave side surfaces 333 on both sides. The lower surface 3 3 2 is attached. In the substrate core layer 3 1 〇, the recessed side surface 3 33 and the upper surface 331 of the lead wires 310 are covered by the solder resist layer 340. Therefore, the I-shaped cross section of the lead wires 330 and the concave side surface thereof are utilized. The 333 covered structure enhances the tensile strength of the leads 330. In a third embodiment, another enhanced tensile strength of the lead 9 is disclosed.
電路基板，如第7圖所示，該電路基板400係至少包含 板核心層410、複數個引線430以及一防銲層440。該些引 線430之兩側係可形成有一凹入側面43 1，如圓弧凹槽、v 形凹槽或ϋ形凹槽，可使該些引線430之截面為I型或漏斗 型等。較佳地，該些引線430之一部位係可嵌埋於該基板核 心層410内，並以該防銲層440覆蓋該些引線43〇突出於該 基板核心層410之其它部位。藉此增進該引線43〇之抗拉強 度與定位性。此外，可進一步說明該些引線43〇之形成方法， 首先，對一銅箔過度蝕刻，以形成具有兩側凹入側面43丨之 引線430，再壓合該基板核心層41〇，以使該些引線43〇之 底部稍嵌埋於該基板核心層410内，另以該防銲層44〇形成 於該基板核心層410上，以覆蓋該些引線43〇。 以上所述，僅是本發明的較佳實施例而已，並非對本發 月作任何形式上的限制，雖然本發明已以較佳實施例揭露如 上，然而並非用以限定本發明，任何熟悉本項技術者在不 2本發明之巾料利職内，所作的任何簡單修改、等效 '、化與修飾’皆涵蓋於本發明的技術範圍内。 【圖式簡單說明】 第1圖 第2圖 第3圖 第4圖 習知電路基板之局部截面示意圖。 習知電路基板沿其中一引 引綠之局邛截面示意圖。 依據本發明之θ ^ . %. 八體實細例，一種増強引線抗拉 又之電路基板之局部截面示意圖。 依據本發明之繁—Θ ^ ^ ，、體實施例，該電路基板沿其 一引線之局部截面示意圖 200822822 第5A至5E圖：給；—兩The circuit substrate, as shown in Fig. 7, includes at least a board core layer 410, a plurality of leads 430, and a solder resist layer 440. The two sides of the lead wires 430 may be formed with a concave side surface 43, 1 such as a circular arc groove, a v-shaped groove or a meandering groove, and the lead wires 430 may have a cross section of a type I or a funnel type. Preferably, one of the leads 430 is embedded in the substrate core layer 410, and the solder wires 440 cover the leads 43 and protrude from other portions of the substrate core layer 410. Thereby, the tensile strength and the positioning property of the lead wire 43 are improved. In addition, the method for forming the leads 43 is further described. First, a copper foil is over-etched to form leads 430 having concave sides 43 on both sides, and then the substrate core layer 41 is pressed to make the The bottoms of the leads 43 are slightly embedded in the substrate core layer 410, and the solder resist 44 is formed on the substrate core layer 410 to cover the leads 43A. The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalents, modifications, and modifications made by the skilled person within the scope of the invention are covered by the technical scope of the present invention. [Simple diagram of the figure] Fig. 1 Fig. 2 Fig. 3 Fig. 4 Fig. 4 is a partial cross-sectional view of a conventional circuit board. A schematic diagram of a cross-section of a green circuit along a conventional circuit substrate. According to the θ ^ . % of the present invention, a partial cross-sectional view of a circuit board with a bare lead tensile resistance is shown. According to the conventional method of the present invention, a partial cross-sectional view of the circuit board along a lead thereof is made in the following section: 200822822, 5A to 5E;
4該㈣以^程W 第6圖發明之第二具體實施例’另-種增強引線抗 拉強度之電路基板之局部截面示意圖。 第7圖：依據本發明之第三具體實施例，另―種增強引線抗 拉強度之電路基板之局部截面示意圖。 【主要元件符號說明】 100 電路基板 110 基板核心層 120 連接墊 130 引線 131 上表面 132 下表面 133 斷裂處 140 防銲層 200 電路基板 210 基板核心層 220 連接墊 230 引線 231 上表面 232 下表面 233 凹入側面 234 底層 235 中間層 236 頂層 240 防銲層 250 介電層 300 電路基板 310 基板核心層 330 引線 331 上表面 332 下表面 333 凹入側面 340 防銲層 400 電路基板 410 基板核心、層 430 引線 431 凹入側面 440 防銲層 114 (4) A partial cross-sectional view of a circuit board for enhancing the tensile strength of a lead wire according to a second embodiment of the invention. Fig. 7 is a partial cross-sectional view showing a circuit board for enhancing the tensile strength of a lead wire according to a third embodiment of the present invention. [Main component symbol description] 100 circuit substrate 110 substrate core layer 120 connection pad 130 lead 131 upper surface 132 lower surface 133 break 140 solder resist layer 200 circuit substrate 210 substrate core layer 220 connection pad 230 lead 231 upper surface 232 lower surface 233 Concave side 234 bottom layer 235 intermediate layer 236 top layer 240 solder resist layer 250 dielectric layer 300 circuit substrate 310 substrate core layer 330 lead 331 upper surface 332 lower surface 333 concave side 340 solder resist layer 400 circuit substrate 410 substrate core, layer 430 Lead 431 recessed side 440 solder mask 11