TW200816454A - Memory arrays and methods of fabricating memory arrays - Google Patents

Abstract

A memory array includes a plurality of memory cells formed on a semiconductor substrate. Individual of the memory cells include first and second field effect transistors respectively comprising a gate, a channel region, and a pair of source/drain regions. The gates of the first and second field effect transistors are hard wired together. A conductive data line is hard wired to two of the source/drain regions. A charge storage device is hard wired to at least one of the source/drain regions other than the two. Other aspects and implementations are contemplated, including methods of fabricating memory arrays.

Description

200816454 IX. Description of the Invention: [Technical Field to Which the Invention Is Ascribed] The present invention relates to a method of storing a memory train and a vehicle. [Prior Art] Memory System - An integrated circuit type used to store data in a computer system. It is typically fabricated in one or more arrays of individual memory cells. The memory unit can be volatile, semi-volatile or non-volatile. Non-volatile «The hidden unit can store data for an extended period of time, many of which include when the computer is turned off. Volatile memory is dissipated and therefore needs to be refreshed and rewritten, and many instances include multiples per second. Ο An exemplary volatile semiconductor memory system, dynamic random access memory (DRAM), is shown in Figure 1 as an exemplary prior art dram unit. Figure 1 depicts an individual/single-DRAM cell 1Q that includes a field effect access transistor-like storage capacitor i4. The field effect transistor i 2 includes a pair of source/drain regions I5 three I6 and a gate 17. The source/drain region 16 is described as being connected to the storage capacitor 14, and the source/drain region 15 is electrically connected to the bit line 18, 17 is typically in the form of an extended word line, which is formed into a plurality of columns. The gate of the field effect transistor. The bit line 18 is typically connected to a plurality of source/nomogram regions 15 formed as field effect transistors of "row" (normally perpendicular to the interpole/word line columns). A number of example towels, (iv) a common source/pure region 15 of the field effect transistor (four) connection. A dual-crystal DRAM cell using a capacitor has been proposed, as disclosed in U.S. Patent No. 6,81,937. Although the present invention aims to solve the above problems, it is not limited thereto. The textual expression of the scope of the patent application (which does not include the interpretation or other limitations of this specification) and its equivalent principles is limited. SUMMARY OF THE INVENTION The disclosure of the present invention has been filed to promote the constitutional purpose of the U.S. Patent Law "Promoting Science and Progress in Useful Technology" (Chapter 1, Paragraph 8). Aspects of the invention include a memory array and a method of fabricating a memory array. The memory array configuration can be fabricated by any method without being limited to the method of fabricating a memory array as disclosed in the above. Likewise, the method of fabricating memory J does not have to be forked to a memory array configuration as disclosed herein. [Embodiment] First, an exemplary aspect of a memory array configuration will be described with reference to FIG. In various embodiments, a memory array fabricated in accordance with the present invention comprises a plurality of memory cells formed on a semiconductor substrate. In the context of this document, the term semiconductor substrate, or, semi-body substrate, is defined to mean any structure comprising a semiconducting material, including but not limited to bulk semiconductor materials, such as semiconductor wafers. (alone or in an assembly containing other materials), 2, a layer of semiconducting material (single_ or in an assembly containing other materials). • Any support structure of the substrate cedar, including but not limited to the above-mentioned semiconducting properties. The preferred semiconductor substrate includes a large-volume semiconductor substrate, for example: large-volume single crystal. Aspects of the invention may of course also be used for the upper semiconductor of the insulator, the board and any other substrate (whether existing or to be developed) in which the operational memory array can be fabricated or formed. The memory array will contain a plurality of memory banks S, and exemplary individual memory cells in accordance with various embodiments of the present invention are generally indicated with reference to Figure 12, number 123126.doc 20081645420. It's not a sensation, "heart... All memory cells have the same construction. ^B. The individual memory of the same structure is the same as 0. How can it be used only by example, ^ ^ ^ ^ Λ ^ Figure 2 contains the semiconductor The semiconductor substrate 22 of the material 23 〇 semiconductor 姑 〇 m m m m 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可 可Or the well is doped with a suitable background. When you are a good person, you can use other semiconductor materials and substrates. Only ϋ ..., consider ^ 偟 straw from the dry case, + conductor material 23 of the exemplary $ 景 doping with Ρ type appropriate agent / / / 辰, so that the gate can be activated after the formation of n-type field effect electricity The channel area of the crystal. The individual memory cells 2A include a first field effect transistor 24 and a second field effect transistor 26. Each of them includes a idle pole, a channel region, and a - source source region. For example, 'the first field effect transistor 24 is described as including a gate 28' to describe the second field effect transistor 26 as containing a gate. The gates 28 and 3 are received, respectively, in the openings σ 29 and 31 formed in the semiconductor material 23 of the semiconductor substrate 22, as described, but only by way of example. In the embodiment, the ports 29 and 31 are in the form of elongated trenches in which the conductive material received will form a word line/gate for a plurality of memory cells. Preferably, only the exemplary opening widths of the examples 'openings 29 and 31 and the spacing between adjacent openings are less than or equal to 5 angstroms. Exemplary depths for the described trench openings 29 and 31 are from 100 angstroms to 500 angstroms from the outermost surface of the semiconductor material 23. An exemplary preferred electrically conductive material for the gates 28 and 3 is a conductive doped semiconductor material and/or metal. In the context of this document, "metal" defines a mixture of any elemental metal, alloy or elemental metal, or a conductive metal compound. By way of example only, for gates 28 and 3, 123126.doc 200816454 A preferred conductive material is titanium nitride. Gate dielectric 32 is depicted as inner opening 29 and 31. Any suitable existing or pending dielectric material can be used, an example of a preferred range of thicknesses from 30 angstroms to 80 angstroms. ' 々 Each discharge crystal 24 includes a pair of source/drain regions 34 and 36, and a first effect transistor 26 includes a pair of source/drain regions 38 and 40. This can be formed by any ion implantation, diffusion doping, etc., as well as any other procedure (whether present or not). The non-consumable thickness of such source/drain regions 34, 36, 38 and 40 is less than or equal to 5 angstroms from the outer surface of material 23. In the exemplary preferred embodiment, the pair of source/drain regions are laterally received between gates 28 and 30 and shared by first and second transistors 24 and 26. In the exemplary embodiment described, the source/drain region 36 of the first field effect transistor 24 and the source/deuterium C戍40 of the second field effect transistor constitute the same source/drain A region that is shared by such first and first field effect transistors. In one embodiment, as shown, other source/drain regions 34 of the pair 34/36 are laterally received outside the gate Ο 28, at the gate

Outside the 30, the other source/drain regions % of the 38/4 接收 are received laterally. In the exemplary preferred embodiment described, the shared source/drain regions 36/4 are received laterally and laterally outside of the gates 28 and 3〇. In addition, in the preferred embodiment described, the regions of the other source/drain regions 3 4 and 38 are received on the front side of the gates 28 and 30, and the source is described in a preferred embodiment. The / drain region is formed in the bulk semiconductor material U. However, other configurations are of course contemplated, including, by way of example only, the source/drain of the two. 123126.doc -10- 200816454 The first field effect transistor 24 includes a channel region 42 and the second field effect transistor % includes a channel region 44. In combination, but only as a preferred embodiment, this will result in the general w shape of the depicted section. Each of the channel regions U, the material includes at least one switchable current path within the cross-section of the substrate, which extends or extends between the shared source/pole 7 drain region 36M and the respective other source/drain regions 34. Preferably, as shown, each current path 46 includes interconnected first and second Γf' vertical segments 48 and 50. The first and first substantially vertical segments 48 and 50 of the exemplary embodiment described (") can be considered to include a front (four) portion 52', respectively, and that the interconnect portion 56 is adjacent to the front side of the first substantially vertical segment. The second substantially vertical segment 5 of the inner end portion 52 is received. In the exemplary embodiment described, interconnect segment 56 is oriented substantially horizontally relative to one of the substrate orientations described. Figure 2 schematically depicts a conductive data line 6 〇 which is connected to the source/drain region pair 34/36 and the source/drain region pair 38/4 〇 other source/drain regions μ, 38. Electrical connection. In an exemplary preferred embodiment, the conductive data lines 6 are received on the front side of the G = poles 28 and 30. Figure 2 also schematically depicts a charge storage device 62 electrically coupled to a shared source/drain region 36/4. In the exemplary preferred embodiment described, the charge storage device a comprises a capacitor. "Figure 2 unintentionally describes conductive data lines 60 and charge storage devices 62 that are electrically coupled to their respective source/drain regions, which may occur in any manner or in any embodiment. In a preferred aspect, the gates The front side of the poles 28 and 30 receives the charge storage device 62, and in a preferred aspect, the conductive data line 6 is received on the front side of the gates and %. In addition, in a preferred and exemplary aspect, 123126.doc 200816454 ' The charge storage device 62 is received on the front side of the conductive data line 60, such as in the preferred embodiment, as exemplified in the following description. In a preferred embodiment, the 'individual memory cell 2G includes a dram unit, a feed line 60. A one-dimensional line is included. In the preferred embodiment, the conductive material electrically interconnects the gates 28 and 3() of the first and second transistors 24 and 26, respectively. For example, Figure 2 schematically depicts conductive The material region or segment 64' electrically connects the conductive gates. In an exemplary embodiment, the conductive material interconnected with the gates 28 and 3() is formed in the semiconductor substrate 22 (better) Semiconductor substrate Received in the trenches of material 23. For the sake of clarity, the material 23 and the possible peripheral insulating material 32 adjacent to the conductive material are not shown in the schematic perspective cross-sectional view depicted in Figure 2. One aspect of the invention includes memory An array comprising a plurality of memory cells formed on a semiconductor substrate. The individual cells of the memory cell include first and second field effect transistors, respectively comprising a gate, a channel region, and a pair Source/drain region: The gates of the first and second field-effect transistors are hard-wired together. The conductive data lines are hard-wired to the source// and the pole regions, and the charge storage device is hard. The wiring is connected to at least one of the source/drain regions except the two. For example, by way of example only, FIG. 2 schematically depicts a preferred configuration of the individual memory cells of the memory array. This exemplary individual memory cell is schematically depicted in Figure 3. In a preferred embodiment of this aspect, one of the source/drain regions is laterally received between the gates. In a preferred embodiment, the source Pole/bungee area One of the 123126.doc -12-200816454 is shared by the first and second field effect transistors, and in a preferred aspect the storage device is connected to the shared source/drain region. In the solution, the closed-pole hard wiring is connected to H by a conductive material received in at least one trench formed in the semiconductor material of the semiconductor substrate and extending between the closed electrodes, and the electrical mutual polarity can be considered. 'For example, by separating interconnects or layers, or by any other means existing or to be developed, and for any aspect of the present disclosure (4). - In a preferred embodiment, each channel region is included at the source/ A current path extending between the drain regions to = one of the sections, the first and second substantially vertical segments of the interconnect. Any other exemplary attributes of the specific embodiment of Figure 2 first described may also be considered. By way of example only, FIGS. 4-6 describe an exemplary additional configuration with respect to FIG. 2 that incorporates a conductive data line and a charge trap device structure. The same reference numerals as in Fig. 2 have different numbers indicating additional structures. The insulating cover 7 is received on the conductive (4), 30. An exemplary preferred material is tantalum nitride. The interlayer dielectric has been formed on the front side of the semiconductor material 23." Demonstration! The raw material is a dioxide dioxide, which may or may not be mis-doped. It has passed through the vertical direction toward the source m-pole regions 34 and 38. The conductive data line is in contact with: ^ The conductive material 75 has been deposited and patterned to form a conductive data line. This can be formed by a drum-like program or formed by deposition and subtraction patterning = patterning only by example An exemplary preferred method includes sinking = or a plurality of conductive materials 75 followed by post-patterning and subtractive etching. A patterned material 75 is deposited thereon before or after the insulating material 76, and / / and subsequently Anisotropically etching the same or different % of insulating material to form an edge of the insulating conductive wire between the layers 123126.doc -13 - 200816454. Etching to form the data line effectively recesses the material 75 within the contact opening. As shown in the cross section of Fig. 5, a certain insulating spacer forming material % is then deposited thereon over the material 75 in the cross-sectional view of Fig. 5.

另 Another interlayer dielectric layer 78 has been deposited (Fig. 5). *Specially preferred materials include hetero or undoped - oxidized stone. The contact opening 8〇 of the shared source/drain region 36/40 has been traversed through the interlayer dielectric layer and the surname. The conductive insertion material 81 is received therein. Charge storage device 62 is depicted as including a capacitor having a storage node electrode 82 that is electrically coupled to a conductive plug 81 that is received within contact σ8〇. The battery 'Electrical' 84 is received outside and above the storage node electrode 82, and the outer conductive unit plate electrode % has been formed thereon. Of course, any exemplary or pending material may be considered for capacitor dielectric 84 and conductive capacitor electrodes 82 and 86. The diagrams of Figures 2 and 4 through 6 described herein are merely exemplary representations of individual 5 memory elements and memory arrays in accordance with various aspects of the present invention. Those skilled in the art will appreciate that this can be made in any of a variety of ways, whether existing or to be developed. Exemplary inventive aspects of a method of fabricating a memory array are illustrated by way of example only with reference to FIG. Figure 7 is a top plan view of a semiconductor substrate including (by way of example only) a memory array region. The active area area of the trench isolation region and the alternate line 1〇1 of the line 1〇2 have been formed in a suitable semiconductor substrate, for example, the substrate 22 of the specific embodiment will be described first. A series of runway trenches 104 have been etched into active area regions 101 and trench isolation regions 102' which are generally perpendicular to the alternating lines of active area and trench isolation regions 102. By way of example only, this can be used in the form of openings 29 and 31 of Figures 123126.doc - 14 - 200816454 2 for the manufacture of individual memory cells. A conductive material is formed in the track-type trench 1〇4 to form a pair of electrically connected word lines with respect to individual trenches of the track-type trench. Exemplary preferred materials are the materials described by the reference gates 28 and 30. . Accordingly, and also in an exemplary preferred embodiment, the gate dielectric (not shown in Figure 7 for clarity) is formed as an exemplary arrangement prior to providing the gate material 28/30. The runway type ditch is 1〇4. The source/drain regions may be formed laterally in the runway trench 104 and laterally outside the raceway trench 4 in the active area. By way of example only, and with reference to the specific embodiment of FIG. 2, such exemplary lateral internal source/drain regions are designated at 36/40, such exemplary lateral external source/drain regions are numbered in FIG. 34 and 38 are designated. The conductive data lines (not shown in FIG. 7 for clarity) are formed to be electrically connected to the source/drain regions that are laterally received outside of the track-type trench, for example, for example implementations of exemplary FIGS. 2 and 4-6. Example source/drain regions % and 38. The charge storage device (not shown in Fig. 7 for clarity) is formed to be electrically connected to the individual regions of the source/drain regions that are laterally received inside the track-type trenches 1 〇4. For example and by way of example only, capacitors or other devices may be formed with respect to the source/drain regions 36/4 of the specific embodiments of Figures 2 and 4-6. By way of example only, exemplary separate conductive contacts 110 are shown as being received external to the memory array 100 for electrical connection with conductive material (ie, conductive materials 28 and 30 relative to each trench 1) for access/activation Each character/interpolar line pair. One aspect of the present invention includes a method of fabricating a memory array comprising alternating between an active area region and a trench isolation region in a semiconductor substrate. 123126.doc -15-200816454 line. An exemplary such alternate line is illustrated by way of example only in FIG. A series of ditches are engraved into a region of active area that is perpendicular to the alternate line of the active area and the isolated area of the trench and the isolation area of the trench. By way of example only, the exemplary trench openings 2 9 and 3 1 depicted in Figure 7 are exemplary such pairs of trenches, regardless of whether a runway-type trench is formed. In any event, in an embodiment, a portion of the semiconductor substrate is engraved into an interconnected trench that interconnects individual trenches of each pair of trenches. For example, (-) and by way of example only, each of the exemplary semicircular/arched trench sections 112 described is an exemplary interconnected trench that interconnects individual trenches. Only one of such trench turns 12 may be fabricated or alternately formed, or a 2-state trench may be etched. Alternatively, the universal trench pair can be simultaneously and/or separated using a common mask step button or separated from the masking step and/or etching. A conductive material is formed in the trench pair and the interconnect trench to form a pair of electrically connected word lines with respect to the individual trenches of the trench pair. This may involve depositing at least some of the conductive material U in the trench pairs and interconnected trenches simultaneously or completely differently. (Interconnect material/region 64 in Figure 2 corresponds to such interconnected trenches and conductive materials.) = The source/drain regions are formed laterally in the middle of individual trenches in the trenches and in the individual trenches of each pair of trenches Within the area of the action area. A conductive data line electrically connected to the source/no-polar region received outside the individual trenches of each pair of trenches is formed. A charge storage device is formed that is electrically coupled to individual regions of the source/drain regions received between individual trenches of each pair of trenches. The specific embodiments of Fig. 2 and Figs. 4 to 6 will be described by way of example only. 123126.doc -16- 200816454 The above exemplary embodiments of Figures 2, 4-6, and 7 can be fabricated by any of a number of existing or pending techniques. In addition, the secondary micro-shirt can be fabricated only by the trench openings 29, 31 described in the Figures 2, 4 to 6 and 7. For example and by way of example only, the trench opening profile can be fabricated to the smallest possible lithographic feature size within the first hard mask layer. Thereafter, an additional suitably thin hard mask material can be deposited thereon to align the sidewalls and the substrate of the trench formed in the first hard mask layer. This can withstand the anisotropic spacer class name,

Therefore, the opening width of the trench is reduced before the trench openings 29 and 31 are engraved into the substrate material, and the described trench is formed as a secondary lithography. In addition, by using an anisotropic silver engraved hard mask spacer, which is deposited to a lateral thickness smaller than the current minimum lithography engraved feature size, the hard mask block between the trenches can be fabricated in a similar manner. Lithography. In addition, the peripheral circuit gate material may be deposited before the trench openings 29, 31 are formed, and then the peripheral circuits in the array area are transmitted before the peripheral gate material is patterned to form the field effect transistor gates in the peripheral circuit area. The gate material forms trench openings 29,31. Additionally, by way of example only, the exemplary gate dielectric 32 and gate material 28, 3〇 described can be deposited and planarized with respect to the perimeter of the conductive gate material prior to removal of the peripheral gate material from the array. Chemical. By way of example only, the described exemplary recesses of the conductive gate material 28, 30 within the memory array can occur coherently with the etching of the peripheral gate material. Further by way of example only, the insulating material 70 formed on the conductive gate material can be formed coherently with the insulating spacer formed with respect to the peripheral gate structure and have the same material. Of course, any other existing or pending development of 123126.doc -17-200816454 can be considered as well as in connection with any of the substrates identified and claimed herein. The present invention has been described with respect to the structure and the description of the invention. However, it should be understood that the present invention is not limited to the specific features of the display and description: therefore, any form or modification of the component that is disclosed in the preferred embodiment of the present invention is The equivalent of the teaching order, the interpretation of the field, please attach the scope of the patent to the appropriate scope. BRIEF DESCRIPTION OF THE DRAWINGS Preferred embodiments of the present invention have been described above with reference to the accompanying drawings. 1 is a schematic diagram of a prior art DRAM cell. 2 is a schematic perspective cross-sectional view and partial schematic view of a substrate segment including a memory cell in accordance with various aspects of the present invention. Figure 3 is a schematic illustration of a single/individual memory unit in accordance with an aspect of the present invention. Figure 4 is an enlarged schematic top plan view of a substrate segment including the memory cell of Figure 2; Figure 5 is a schematic cross-sectional view taken along line 5-5 of Figure 4. Figure 6 is a schematic cross-sectional view taken along line 6-6 of Figure 4. Figure 7 is another enlarged schematic top plan view of a substrate segment in accordance with aspects of the present invention. [Main component symbol description] 10 DRAM cell 12 field effect access transistor 14 storage capacitor 123126.doc -18 - 200816454 Ο 15 source/drain region 16 source/drain region 17 gate 18 bit line 20 memory Body unit 22 Semiconductor substrate 23 Semiconductor material 24 First field effect transistor 26 Second field effect transistor 28 Gate/conductive gate material 29 Opening 30 Gate/conductive gate material 31 Opening 32 Gate dielectric/periphery Insulation material 34 source/> and pole region 36 source/> and pole region 36/40 shared source/drain region 38 source/drain region 40 source/drain region 42 channel region 44 channel region 46 switchable current path 48 first substantially vertical segment 50 second substantially vertical segment 123126.doc -19- 200816454 52 front inner end portion 56 interconnect segment 60 conductive data line 62 charge storage device 64 conductive material 70 insulating cover / Insulating material 72 interlayer dielectric/interlayer dielectric layer 74 conductive data line contact opening 75 conductive material 76 insulating material 78 interlayer dielectric layer 80 contact opening 81 conductive insert material / conductive Plug 82 storage node electrode / conductive capacitor electrode 84 capacitor dielectric 86 outer conductive unit plate electrode / conductive capacitor electrode 100 memory array area 101 alternate line 102 line / trench isolation area 104 runway type trench 110 conductive contact 112 trench section 123126.doc •20-

Claims (1)

200816454 X. Patent Application Range: 1 . A memory array comprising: a plurality of memory cells formed on a semiconductor substrate, the individual cells of the memory cells comprising: • first and second field effects The transistor 'includes a gate, a pass, a 31 region, and a pair of source/drain regions, respectively; the gates are received in openings formed in the semiconductor material of the substrate, the pair of sources/汲The pole region f is laterally received in the middle of the gate, and the first and second transistors share another region of the pair of source pole regions of the first and second transistors Each of which is laterally received outside its individual gates, a conductive > feed line that is received laterally outside of the gates and with each of the other regions of the pair of source/drain regions Electrically coupled; and a charge storage device electrically coupled to the shared source/drain region. {2] The memory array of claim 1, wherein the semiconductor material comprises a large volume semiconductor material. 3. The memory array of claim 2, wherein the large volume semiconductor material comprises a large volume single crystal germanium. 4. An array of memory as claimed in claim 1, wherein a region of the pair of source/drain regions is received frontside of the gates. 5. The memory array of claim 1 wherein each of the other regions of the pair of source/drain regions are received laterally outside the gates. 6. The memory array of claim i, wherein the front side of the gate is connected to the one of the source/drain regions and the pair of source/drain regions Each of the areas. 7. The memory array of claim 1, wherein the charge storage device is received in front of the gates. 8. The memory array of claim 1 wherein the charge storage device is received on the front side of the gates and on the front side of the four conductive data lines. 9. The memory array of claim 1, wherein each channel region comprises a current path in at least one of the sections extending between the shared source/drain region and the respective other source/drain region, The first and first upper vertical segments of the interconnect are included. The memory array of claim 1, comprising a conductive material electrically interconnecting the gates of the first and second transistors. 11. The memory array of claim 10, wherein the conductive material is received in a trench formed in the semiconductor substrate. 12. The memory array of claim 10, wherein the conductive material is received in a trench formed in the semiconductor material of the semiconductor substrate. 13. The memory array of claim 1, wherein each channel region comprises a current path in at least one of the sections extending between the shared source/drain region and the respective other source/drain region, And including a first and a second substantially vertical segment of the interconnect; and a conductive material electrically interconnecting the first and second transistors. 14. The memory array of claim i, wherein the memory cells comprise DRAM cells. 123126.doc 200816454 1 5 - A memory array comprising: a plurality of memory cells formed on a semiconductor substrate, the individual cells of the memory cells comprising: first and second field power a crystal, each of which includes a gate, a channel region, and a pair of source/drain regions; one of the pair of source/drain regions is laterally received in the middle of the gates and is received by the first and the first The two transistors of the first and second transistors are f/other of the pair of source/drain regions; the parent of the domain is received on the front side of the individual gates, and each channel region is included in the a current path in at least one of the sections extending between the source/drain region and the other source/drain region, comprising first and second substantially vertical segments of the interconnect; And electrically connected to each of the other regions of the pair of source/drain regions; and a charge storage device electrically coupled to the shared source/drain region. The memory array of claim 15, wherein the first and second substantially vertical portions of the front end portion of the package 3, the current path in the cross section is included near the inner end portion of the front surface An interconnected section received between the first and second substantially vertical segments. 17. The memory array of claim 15 wherein the current path 4 13 in the cross-section receives an interconnected substantially horizontal segment between the first and second substantially vertical segments, such as 6 hai. 18. The memory array of claim 15, wherein the conductive data lines are received in front of the gates. The memory array of claim 15 wherein the charge storage device is received laterally outside of the gates. 20. The memory array of claim 15 wherein the charge storage device is received on the front side of the gates and on the front side of the data line. 2 1 . The memory array of claim 1, comprising a conductive material electrically interconnecting the gates of the first and second transistors. 22. The memory array of claim 15, wherein the conductive data line comprises a bit of a p-line' and the memory cells comprise DRAM cells. A memory array comprising: a plurality of memory cells formed on a semiconductor substrate, the individual cells of the memory cells comprising: a first field effect transistor and a first field effect transistor each comprising a a gate, a channel region, and a pair of source/drain regions; one of the pair of source/drain regions is laterally received in the middle of the gates and shared by the first and second transistors Each of the other regions of the pair of source/drain regions U of the first and second transistors are laterally received outside of their respective gates, and the conductive material is such that the first and second transistors are The gates are electrically interconnected; the conductive data lines are electrically connected to each of the other regions of the pair of source/drain regions; and a charge storage device is associated with the shared source/drain Regional electrical connection. 24. The memory array of claim 23, wherein the conductive material is received in a trench formed in the semiconductor substrate. The memory array of claim 23, wherein the conductive material is received in a trench formed in the semiconductor material of the semiconductor substrate 123126.doc 200816454. 26. The memory array of claim 23, wherein the conductive data line is received in front of the open electrodes. 27. The memory array of claim 23, wherein the charge storage device is received laterally outside of the gates. 28. The memory array of claim 23, wherein the charge storage device is received on the front side of the gates and on the front side of the conductive data lines. U 29. The memory array of claim 23, wherein the charge storage device comprises a capacitor. a memory array comprising: a plurality of memory cells 'formed on a large-volume semiconductor substrate'. The individual cells of the memory cells include: first and second field effect transistors, Each of the source/drain regions is received in a trench within the bulk semiconductor material of the substrate, and the source-drain region is formed in the substrate. The intermediate large volume semiconductor material is laterally received and shared by the first and second transistors, each of the other regions of the pair of source/drain regions of the first and second transistors being tied The large-capacity semiconductor material other than the individual gates is laterally received, and the conductive material electrically interconnects the gates of the first and second transistors, and each channel region is in the shared source/drain region At least one section extending between the respective other source/drain includes a current path in the A-volume semiconductor material, including the first and second substantial segments of the interconnection; and the soil and 123126.doc 200816454 ' Electric > feed line 'which is attached to the gates The front side receives and is electrically connected to each of the other regions of the pair of source/drain regions; and a charge storage device electrically coupled to the shared source/drain region and is coupled thereto The front side of the conductive data line is received. 3. The memory array of claim 30, wherein the electrically conductive material comprises a metal. 32. The memory array of claim 3, wherein the metal comprises TiN. 3 3 - a memory array comprising: a plurality of memory cells formed on a semiconductor substrate, the individual cells of the memory cells comprising: a brother and a young transistor, each comprising a a gate, a channel region, and a pair of source/drain regions; the gates of the first and second field effect transistors are hard-wired together; and a conductive data line is a hard-wired connection Up to two of the source/drain regions; and a charge storage device that is hardwired to at least one of the source/drain regions except the two. 34. The memory array of claim 33, wherein the one region is received laterally between the gates. 35. The memory array of claim 33, wherein one of the source/drain regions is shared by the first and second field effect transistors, the charge storage device being coupled to the one shared source/ Bungee area. 36. The memory array of claim 33, wherein the gate is received by a conductive material received in the trench of at least one trench 123126.doc 200816454 formed in the semiconductor material of the semiconductor substrate and extending between the gates Very hard wiring is connected together. 37. The memory array of claim 33, wherein the gates are hardwired by a conductive material received in at least two trenches formed in the semiconductor material formed in the conductor substrate and extending between the gates Together. 38. The memory array of claim 33, wherein the charge storage device is received in front of the gate of the sputum*, τ隹通寺. 39. The memory array of claim 33, wherein the conductive data lines are received in front of the inter-poles. The memory array of claim 33, wherein each channel region comprises a current path in at least one of the sections extending between the source/drain regions, the first and second substantially vertical segments of the interconnect . 41. A method of fabricating a memory array, comprising: forming alternating lines of active area regions and trench isolation regions in a semiconductor substrate; etching a series of runway trenches into a general and active area region and trenches c, isolated Forming a conductive material in the raceway-type trench to form a pair of electrically connected word lines with respect to individual trenches of the runway-type trench; The source/drain regions of the runway-type trenches are laterally formed and laterally outside the runway-type trenches; and the source/drain electrodes are formed laterally received outside the runway-type trenches a electrically conductive data line electrically connected to the area; and a charge storage device electrically connected to an individual region of the source/汲123126.doc 200816454 pole region laterally received within the racetrack trench. 42. A method of fabricating a memory array, comprising: forming alternating lines of active area regions and trench isolation regions in a semiconductor substrate; 胄 a series of trench pairs etched into a general-purpose area and a trench isolation region The alternating area of the active area and the trench isolation area, the at least one interconnect trench, such as +c, is etched to interconnect the semiconductor substrate of each of the individual trenches of the trench; in the trench pair and the Conductive materials are formed in the interconnected trenches to form electrical-connected word lines with respect to the individual trenches of the trenches; in the middle of individual trenches of the respective pairs of trenches and outside of individual trenches of the respective pairs of trenches Transmitting a source/drain region in the area of the active area; forming a conductive data line electrically connected to the source/drain regions that are laterally received outside the individual trenches of the respective pairs of the trenches; A charge storage device is formed that is electrically coupled to individual regions of the source/drain regions that are received between individual trenches of the respective pairs of trenches. 43. The method of claim 42, wherein the engraving of the series of trenches and the engraving of the interconnected trenches comprises a common masking step. The method of claim 42, wherein the surname engraving the series of trenches and engraving the interconnected trenches comprises a common etching step. 45. The method of claim 42, wherein forming the electrically conductive material comprises depositing at least some of the electrically conductive material in the trenches and interconnecting trenches. The method of claim 42, which comprises etching only one interconnected trench for each pair. 47. The method of claim 42, comprising etching only two interconnected trenches for each pair. 48. The method of claim 42, comprising etching for a plurality of interconnected trenches of each pair 0 〇 ϋ 123126.doc