TW419726B - Semiconductor device and its manufacture method - Google Patents

Abstract

A semiconductor memory device with plural memory cells is provided. Its capacitor electrode could be connected with metal line in the upper layer without via photolithography process. The IMD of the upper layer metal line is above the insulation film of the capacitor. Device isolation oxide film and a diffusion layer region on a semiconductor substrate is provided to form memory cell, and an insulation film covered the metal line layer. The features of the semiconductor memory device are: make dummy electrodes when form the insulated layer opening and the bottom electrode connected with the diffusion layer. The dummy electrodes are formed at the same layer as the bottom electrode. Besides, capacitor insulation layer is used to form the top capacitor electrode that could be buried in the trench between the bottom and dummy electrodes. Via the opening of the IMD layer upon the top capacitor electrode, top electrode connects with the upper layer metal lines.

Description

419726 V. Description of the Invention (1)-Field of Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device having a storage capacitor on a substrate and a manufacturing method thereof. Description of gas-related technologies In recent years, with the progress of microfabrication of semiconductor memory devices, manufacturing processes have been simplified and the number of processes has been reduced to reduce manufacturing costs, which has become a problem (refer to, for example, Japanese Patent Publication No. 09_1 861 59, Japanese Patent Application No. 09-9_2). 〇 ^ 64 要 / Bulletin, etc.). Fig. 9 is a layout view of the known semiconductor memory device, and Fig. 9 is a sectional view taken along line C-D in Fig. 9. Figures 丨 丨 to 丨 丨 are sectional views of the manufacturing process of the conventional device, which correspond to the lines. Niu Conductor 6 has hidden devices ΠΞ1.1 to 圊 12 'in the order of the process, explaining the "semiconductor memory-like well-known technology, the formation element" is first' on the semiconductor substrate, and the oxide film 2 and the diffusion layer region 3 are separated using pieces. After stacking up! Insulation 骐 16 is used as the wiring layer of bit line 4, and the bit line 4 is soldered in the area of the hairpin and pre- 疋, and the second insulation _17 is stacked on it to bury it.

Capacitance contact hole Next, as shown in FIG. 11, it has a photolithography technique to dig the capacitor, such as about 0 in the upper part.

419726 V. Description of the invention (2) Next, after forming a polycrystalline silicon film with a thickness of about 0.7 μm as doped with impurities, it is patterned using a lithography technique, and a lower electrode 6 is formed on the capacitor contact hole 5. Secondly, after forming a capacitor insulating film 9 ′ made of a nitride film with a thickness of about 6 nm and a polycrystalline silicon film doped with impurities such as phosphorus, the lithography technique is used to remove the polycrystalline silicon film in a predetermined area. Form the capacitor upper electrode 10 ° In this process, in the conventional technology, because the capacitor upper electrode 10 ′ is fully formed so as to cover the lower electrode 6, in this state, it cannot be electrically connected to the electric valley upper electrode 10. In this case, the diffusion layer region 3, the gate electrode, or the bit line 4 located below the capacitor upper electrode 10 is electrically connected to the wiring layer 1 above the capacitor upper electrode 10. Here, in order to 'maintain a region which is not electrically connected to the capacitor upper electrode 10' even when a connection hole electrically connected to the diffusion layer region 3 or the like is formed, it is necessary to form a photoresist pattern as shown in FIG. 11, and The process of removing the valley upper electrode 10 of the semiconductor wafer terminal, and the capacitor upper electrode ′ after removal has a shape as shown in FIG. 9. 々 Secondly, as shown in FIG. 12, after the interlayer insulating film is formed, the area of the upper electrode: the upper electrode 10 is extended using the lithography technology to dig out the opening to form a metal contact hole. 04 " m, with a pore diameter β of about 035 A m at the bottom Second, polycrystalline silicon doped with impurities is deposited in this opening to be buried

Buy 6th 419726 V. Description of the invention (3) Deng Ma Hui # 'to form tungsten plug 12, and by forming the upper wiring 丨 丨, the shape of figure 0 is obtained. Here, the structure of a conventional semiconductor memory device will be described with reference to FIG. On the semiconductor substrate 1, an element separation oxide film 2 and a diffusion layer region 3 are formed thereon, interposed therebetween! The insulating film 16 forms a bit line 4, and a second insulating film 17 is formed so as to cover the bit line 4. A lower electrode 6 is formed on the first insulating film 16 and the second insulating film 17 on the diffusion layer region 3 through the capacitor contact hole 5 and is electrically connected to the diffusion layer region 3. ~ Secondly, a capacitor insulating film 9 is formed to cover the lower electrode 6, and a capacitor upper electrode 10 is formed thereon. The structure is configured to cover the lower electrode 6, and extended to have an electrical connection with the upper wiring. Area of the metal contact hole. in this way. The capacitor upper electrode 10 and the upper layer wiring 11 are electrically connected through the crane plug 12. The translation of the present invention is to solve the problem mentioned above in the conventional method of manufacturing a semiconductor memory device, because the capacitor upper electrode is fully formed so as to cover the capacitor lower electrode, so in this state, it cannot be used with the capacitor upper part. In the case where the electrodes are not electrically connected, 'the diffusion layer region, the gate electrode or the bit line located under the upper electrode of the capacitor' is electrically connected to the wiring above the upper layer of the capacitor. Therefore, in order to maintain a region that is not electrically connected to the capacitor upper electrode even when a connection hole that is electrically connected to the diffusion layer region is formed, it is necessary to

V. Explanation of the invention (4) ^ Forming a photoresist pattern 'Remove the upper part of the capacitor other than the memory cell array. Electrically perform coating: In this process, in addition to forming the upper electrode of the capacitor, it must also be treated. , Development, etching, photoresist removal, etc. "I hope that this cost-reduced semiconductor device, if we can not use micro j 旎 I: to form a capacitor upper electrode, you can reduce the number of processes. The purpose of the above-mentioned conventional technology is to reduce the number of manufacturing processes by not performing the micro-based system, which is entirely new: electricity f upper electricity, and to provide a kind of memory device. + The method of manufacturing the conductor memory device and the method of the semiconducting μα problem are it; :::: The manufacturing unit array of the semiconductor memory device of the present invention ^ < π π, in the lower part of the shape of the memory constituting the semiconductor memory device The electrodes are the same. After the configuration, the conductive member is etched, so that = = =: the shape of the conductive film is stacked. The upper electrode = two electrodes or a virtual map. It has a type of + conductor containing a plurality of memory cells. The memory unit's body unit is provided with an insulating ϋf70 array on the substrate, the memory film and 2 electrodes: the semiconductor memory has a capacitor insulation layer, and is composed of :: lower: ί ::; the lower electrode of the body unit Formed by the same component as the-F electrode

The eighth stomach r: ^-419726___ V. Description of the invention (5) The capacitor insulating film is formed so as to cover the lower electrode and the virtual pattern; among the internal electrodes, in the method of the present invention for the insulating film, the element array electrode, The electricity is formed in this field and the electricity is formed in the field, buried in the lower part, according to Example 0, its capacitance is according to the manufacturer's memory, and the lower part of the electricity is formed by a virtual map and the area in between is covered by the body. The region buried between the adjacent lower electrodes is also provided on the virtual pattern with the same and upper electrodes as the memory cell. The second aspect is to provide a semiconductor memory device, a semiconductor memory device having a plurality of memory cells, and the memory cell having a valley insulating film and an upper electrode on the substrate through an insulating film. For the lower electrode of the memory cell, a virtual pattern formed by the same components in the middle electrode of the same process; covering the lower electrode and the capacitive insulating film of the memory cell array; the lower part of the memory cell array Thunder cup; ^ ^ ^ ^ τ on the uλ and the conductive member of the adjacent virtual pattern, attack the upper electrode in a shape of ^, and prevent the electrode and the entire area of the upper part of the virtual project. According to the embodiment, a detailed description of the implementation mode of the present invention and a brief description with a diagram are given in the detailed description of the above and other embodiments of the present invention and with reference to FIG. 1: a semiconductor diagram of the first embodiment 2: a semiconductor diagram of the first embodiment The advantages, advantages, and characteristics of semiconductors can be more clearly understood from the following preferred formulas, among them: Layout of the memory device Sectional view of the memory device.

419726 V. Description of the invention (6) Fig. 3: A cross-sectional view showing the manufacturing method of the semiconductor memory device of Example 1 in the order of manufacturing processes. Fig. 4 is a cross-sectional view showing the manufacturing method of the semiconductor memory device according to the first embodiment in the order of manufacturing processes. Fig. 5 is a cross-sectional view showing the manufacturing method of the semiconductor memory device according to the first embodiment in the order of manufacturing processes. Fig. 6 is a cross-sectional view showing the manufacturing method of the semiconductor memory device according to the first embodiment in the order of manufacturing processes. FIG. 7 is a layout diagram of a semiconductor memory device of Embodiment 2. FIG. FIG. 8 is a cross-sectional view of a semiconductor memory device according to a third embodiment. Figure 9: Layout of a conventional semiconductor memory device. Figure 10: A cross-sectional view of a conventional semiconductor memory device. Fig. 11 is a cross-sectional view showing a conventional method of manufacturing a semiconductor memory device in the order of processes. Fig. 12: A cross-sectional view showing a conventional method of manufacturing a semiconductor memory device in a process sequence. DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element separation oxide film 3 Diffusion layer area 4-bit line 5 Capacitor contact hole 6 Capacitor lower electrode

Page 10 419726 V. Description of the invention (7) 7 Virtual pattern 8 Photomask insulation film 9 Capacitor insulation film I 0 Capacitor upper electrode II Upper wiring 12 Tungsten plug 1 3 Capacitor contact hole 1 4 Interlayer insulation film 15a Photoresist pattern 1 5b photoresist pattern 1 5 c photoresist pattern 1 6 first insulating film 17 second insulating film 101 capacitor lower electrode (detailed picture) 102 virtual pattern (layout 圊) 103 capacitor contact hole (layout diagram) 104 metal contact hole ( (Layout) 105 Capacitor upper electrode (Layout) Detailed description of the preferred embodiment The semiconductor device of the present invention, in a preferred embodiment, is provided in the same process as the capacitor lower electrode, and a dummy is set in the same layer. The lower electrode pattern (referred to as a virtual pattern, refer to 102 in FIG. 1 or 7 in FIG. 2). In the virtual pattern area, a connection hole (metal contact hole) is formed, which is used to make electricity

41ί > 72δ V. Description of the invention (8) The upper electrode (circle 2 of coil 2) is electrically connected to the upper wiring (11 in Fig. 2). [Embodiment] In order to further explain the embodiment of the present invention ', an embodiment of the present invention will be described with reference to the drawings. [Embodiment 1] Hereinafter, Embodiment 1 of the present invention will be described. 1 to 6 are diagrams illustrating an embodiment of a semiconductor device and a manufacturing method thereof according to the present invention. First, a method for manufacturing a semiconductor device according to the first embodiment will be described with reference to the drawings. 3 to 6 are cross-sectional views showing the A-B cross section of FIG. 1, which are cross-sectional views showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention. First, a well-known technique is used to form an element separation oxide film 2 and a diffusion layer region 3 on a semiconductor substrate. Secondly, after the first insulating film 16 is completely deposited, a wiring layer having a position of 4 is formed in a predetermined area, and a second insulating film 17 is deposited thereon to bury the wiring 4. 5. The right side of the tool is shown in FIG. 3, and a capacitor contact hole m is excavated using a lithography technique. The upper part is about 0-2 cores and the bottom is about 0.15 holes. Secondly, the polysilicon technology is shown in Figure 8. In order to form a silicon oxide film with a thickness of about 0 * 1M, a silicon oxide film with a thickness of about 0 * 1M is formed as shown in FIG. 4, using lithography to form a lower electrode 6, a dummy pattern γ, and a photomask insulation.

Secondly, as shown in FIG. 5 ′, and with a film thickness of about 0.25 and a full opening > forming a gasified stone film with a film thickness of about 6 nm, and a polycrystalline silicon film doped with impurities such as phosphorus.

Page 12 419726 V. Description of the invention (9)

"Etching back" allows the polycrystalline silicon film to remain only on the lower electrode 6, the dummy case, and the sidewall portion of the mask insulating film 8 to form a capacitor upper electrode 100 ". In this embodiment, the The last name is returned, so the electricity & upper electrode 10 is only formed inside the trench sandwiched between the lower electrode 6 or the dummy pattern 7 and the photomask insulation 8. The film is therefore 'in order to form an electrical connection with the diffusion layer region 3 and the like. When connecting the holes, it can also ensure the area that is not electrically connected to the capacitor upper electrode 10, so there is no need to form the photoresist pattern β as shown in the conventional technology, that is, even if the photoresist pattern is not formed as in the conventional technology, and The capacitor upper electrode 10 ′, which removes unnecessary regions, can also be used in the polycrystalline silicon film cashback process, and the capacitor upper electrode 10 is bound to be formed. Second, as shown in FIG. 6, after the interlayer insulating film 4 is formed, the dummy pattern 7 In the area, a photolithography technique is used to form an opening for burying the metal contact hole u, which has a pore diameter of about 0.4 mm in the upper part and about 0.35 in the bottom part. Next, such as titanium and nitrogen are formed. Wiring of titanium and tungsten After the material is cut, the crane plug 12 is formed with the shape of FIG. 2 with the upper wiring. Here, the structure of this embodiment will be described with reference to FIG. 2. It is on the semiconductor substrate 1 and has a t-element separation. The oxide film 2 and the diffusion layer are on top of it and / or the insulating film 16 to form a bit line 4, and a second insulating film 17 covering the bit line 4 is formed. The first insulating film 16 and the second insulating film 17 are electrically contacted with the contact hole 5 to form a lower electrode 6 ′ and are electrically connected to the diffusion layer region 3.

41972S V. Description of the invention (〖〇) 'Sexual connection. In this embodiment, the case of Qiu Yee 7 under the public opinion. The same layer of the electrode 6 is formed to form a virtual map, followed by the lower electrode 6 and the virtual map +8, and a resistive element 9 is formed, so that i is overlaid / the upper cover is formed into a mask insulating film and a mask insulating film 8 . Let ^ cover the lower electrode 6 and the dummy pattern 7 then: ff valley upper electrode! 〇 It is completely buried in the lower gap, and is only arranged on the side wall portion β dummy pattern 7 between the lower electrode 6 and the dummy = 6. In addition to covering the insulating film 8 first, in the region of the dummy pattern 7, the layer wiring 11 is electrically connected through the tungsten plug. The layout of the upper thunder—illustrating this structure, will form the array of electric valleys 4 electrodes 1G1 formed as a length of about 〇3 ^ ^ The interval between the lower electrodes ⑻ is formed as a width of about 0.22 _... And = 'this embodiment t > is the same as the capacitor lower electrode :: the virtual pattern 102 shaped in the same layer is formed to be the same size as the capacitor = pole 101 (eg, the length is about 0.38 _x 〇9S㈣ The two t Λ are about 0.... Size and can be electrically connected to the upper-layer wiring. The H-type contact hole 1G4) ′ allows it to cross the virtual pattern 102. The difference between the capacitor lower electrode 101 and the virtual pattern 102 is whether the connection hole is electrically connected to the lower diffusion layer region 3 (capacitance contact & Here, the 'virtual case 102' is not limited to The shape shown in this embodiment is also a shape that can be a 101 array of the lower electrode of the integrated surrounding capacitor 419726

5. Description of the invention (π) That is, as long as it can be extended. It is also possible to arrange a plurality of virtual patterns in an array. It is also the capacitor upper electrode 10 arranged between the capacitor lower electrode 100 and the metal contact hole 104, and is electrically connected to the upper wiring. [Embodiment 2] FIG. 7 is the embodiment 2 The following is a description of a second embodiment of the present invention. The difference between the embodiment 2 in FIG. 7 and the implementation in FIG. I is: The virtual pattern 102 is the same shape as the capacitor lower electrode iqi— In the embodiment, as shown in FIG. 7, it is an extension of the cell array area ^ The shape of the long side. & Here, the interval of “virtual pattern 1 0 2 must be an interval for forming the capacitor upper electrode 10 suitable for the polycrystalline silicon film”, and its width is the narrowest from the same interval as the capacitor lower electrode 6, and at most it is The interval between the lower electrodes of the capacitor 6 is preferably within 3 times. [Embodiment 3] Hereinafter, Embodiment 3 of the present invention will be described. Fig. 8 is a sectional view of the third embodiment. The difference between the third embodiment of FIG. 8 and the first embodiment of FIG. 2 is that the photomask insulating film 8 is not required in the third embodiment. That is, it is not necessary to form the silicon oxide film described in Embodiment I with reference to FIG. 4. Effects of the Invention As described above, 'the present invention can achieve the following effects. A first effect of the present invention is that the manufacturing of a semiconductor memory device can be shortened.

Page 15 419726 V. Description of the invention (12) k 'can reduce the cost and shorten the construction period by reducing the number of processes. The reason is that in the present invention, since the dummy pattern is formed on the same layer in the same process as the capacitor lower electrode, the lithography process can be omitted when the electrode is formed. That is, during the process of forming the upper electrode of the capacitor, the silicon film is etched back. Because the upper electrode of the capacitor is formed only under the capacitor, it is formed even in the region of the diffusion layer and the like. ^ The connected area 'can also ensure that it is not electrically connected to the upper electrode of the capacitor. Therefore, a photoresist pattern is formed by the lithography process and the non-domain is formed. The capacitor upper electrode in the main area is etched back on the polycrystalline silicon film, and it is not necessary to form the capacitor upper electrode 'necessarily' so that the photoresist coating, the partial electrode, Absolute exposure and development between layers. edge

Page 16

Claims (1)

£ 41972ο 6. Patent application scope 1. A method for manufacturing a semiconductor memory device, the semiconductor memory device having a memory cell array of a plurality of memory cells, and the memory cells are formed on the substrate to form a columnar lower part The electrode is formed with a capacitor insulating film and an upper electrode formed thereon, and is characterized in that: when the lower electrode of the memory cell is formed, a virtual pattern formed by the same component as the lower electrode is formed in the same process. ; Forming the capacitor insulating film on the lower electrode of the memory cell array and the dummy pattern; and thereafter, on the lower electrode covered by the capacitor insulating film of the memory cell array, and phase The upper electrode is formed by burying a conductive member 'in a region adjacent to the dummy pattern. 2. A method for manufacturing a semiconductor memory device, the semiconductor memory device is provided with a memory cell array of a plurality of memory cells, and the memory cell 7C is formed by forming a columnar lower electrode on a substrate and forming thereon The electric valley insulation film and the upper electrode are characterized by: (a) a virtual pattern formed by the same component as the lower electrode in the same process when the lower electrode of the memory unit is formed; ', Forming a capacitive insulating film that can cover the s memory cell array and the dummy pattern; (C) bury a mine guide in the area between the lower electrode of the memory cell array and the adjacent dummy pattern Furnace iA μ Taisha m = f structure to form the upper electrode and not cover the area of the lower electrode and the upper part of the virtual pattern. [3.-Manufacturing method of semiconductor memory device, the semiconductor memory Page 17 v __ 411? 72G_ VI. Patent Application Scope I '--- The device has a memory cell array with a plurality of memory cells, and the 1-cell unit is for forming a lower electrode on the substrate and a capacitor insulation film: j The upper electrode is formed by the following components: when the lower electrode of the memory cell is formed, in the same process, at the periphery of the memory cell array, the same member as the lower element is formed. Forming a dummy pattern, and at that time, forming a mask insulating film on the lower electrode and the dummy pattern; and (b) forming a capacitor that can cover the lower electrode and the dummy pattern array and the mask insulating film An insulating film; ... Cc) and a conductive member is buried in the area between the lower electrode and the adjacent dummy pattern of the memory cell array to form the upper electrode so as not to cover the lower electrode and the dummy All areas of the upper part of the pattern 4. As in the method for manufacturing a semiconductor memory device according to any one of claims 1 to 3, the virtual pattern is arranged in a memory formed by the lower part ... The peripheral region of the cell array. 5. The method for manufacturing a semiconductor memory device according to any one of claims 1 to 3, wherein the virtual pattern is configured to surround a memory cell array formed by the lower electrode. 6. The method for manufacturing a semiconductor memory device according to any one of claims 1 to 3, wherein the dummy pattern is formed into a shape at least the same height as the lower electrode. , 419728 6. Scope of patent application-The upper columnar lower electrode can cover the capacitor insulating film and the upper electrode of the lower electrode. The semiconductor memory device is characterized by: a virtual pattern and the lower portion of the memory unit The electrodes are about the same height 'and are formed by the same member as the lower electrode; the capacitor insulating film is formed to cover the lower electrode and the dummy pattern; the upper electrode is buried in the phase covered by the capacitor insulating film The area between the lower electrodes is adjacent to the dummy pattern, and also has the same capacitive insulating film and upper electrode as the memory cell. 8. A semiconductor memory device comprising a memory cell array of a plurality of memory cells, and the memory unit includes a columnar lower electrode provided on a substrate, a capacitor insulating film and an upper electrode that can cover the lower electrode 'The semiconductor memory device is characterized by having: a virtual pattern' which is approximately the same height as the lower electrode of the memory cell 'and is formed of the same member as the lower electrode; a capacitor insulating film is formed so as to cover The lower electrode and the dummy pattern, and the upper electrode are buried in an area between adjacent lower electrodes covered with the capacitor insulating film, and the dummy pattern also has the same capacitor insulation as the memory cell. Film and upper electrode, and the upper electrode of the dummy pattern is connected to the upper-layer wiring via an interlayer insulating film '. 9. · A semiconductor memory device having a plurality of memory cells