TWI566334B - Method for fabricating dynamic random access memory device - Google Patents

Description

Method for manufacturing dynamic random access memory device

The present invention relates to a semiconductor technology, and more particularly to a method of fabricating a dynamic random access memory device.

As technology evolves, the size of dynamic random access memory devices continues to shrink, making their density increasingly higher, and individual memory devices closer to each other. As a result, the charge generated in the memory device easily leaks to the adjacent memory device and a bit flip phenomenon occurs, thereby causing an error signal. This phenomenon is called the word hammer.

1 is a cross-sectional view showing a conventional dynamic random access memory device. The DRAM device includes a dummy word line 14 and two general word lines 12 disposed in a substrate 10. The structure of the dummy word line 14 is generally the same as that of the general word line 12. Furthermore, the substrate 10 between the general word lines 12 and the substrate 10 between the general word lines 12 and the dummy word lines 14 are respectively provided with a doping region 18 and a doping region 19, wherein the doping region 18 is provided by a bit The contact line 20 is electrically connected to the bit line 22 , and the doped region 19 is electrically connected to the storage capacitor 26 via the capacitive contact window 24 .

During the operation of the DRAM device, a bias voltage is repeatedly applied to one of the adjacent general word lines 12 for the purpose of writing/erasing. Stop applying bias. When a bias voltage is applied, electrons accumulate on the general word line 12, as shown in FIG. When the bias is stopped, the electrons will spread in different directions, such as A, B, and C directions. For the B direction, electrons are scattered into the substrate 10, which has less effect on the memory device.

For the A direction, the electrons cross over the adjacent general character line 12 One again enters the storage capacitor 26 through the doped region 19 located in the A direction, causing word line interference. However, a deep doped region (not shown) may be formed under the doped region 18 between adjacent general word lines 12 to block electrons in the A direction and thereby prevent word line interference in the region.

For the C direction, due to the dynamic random access memory device Due to the limitations of the process and structure, a deep doped region cannot be formed under the doped region 19 in the C direction. Accordingly, a conventional solution is to apply a negative bias voltage (for example, -0.5 V) to the dummy word line 14 to block the propagation path of the electrons, thereby improving the word line interference phenomenon of the adjacent memory device. However, since the negative bias of the dummy word line 14 causes leakage current (for example, gate-induced drain leakage (GIDL)), the renewing time for the dynamic random access memory device ( Refresh time) causes adverse effects.

In view of this, the industry needs a new dynamic random access memory device and a manufacturing method thereof to improve the above problems.

An embodiment of the present invention provides a method for fabricating a dynamic random access memory device, comprising: forming two mask layers spaced apart from each other on a substrate; forming a material layer conformally on the substrate having the mask layer, Forming a layer of material between the mask layers; forming two recesses on opposite side walls of the recessed area a spacer, wherein a first region is defined between the spacers and two second regions are defined between the spacers and the mask layer; and the mask layer and the spacers are used as etching masks for performing multiple etching processes, Forming a first trench and two second trenches in the substrate of the first region and the second region, wherein the depth of the first trench is deeper than the depth of the second trench; and filling in the first trench A dummy gate layer is inserted into the dummy gate layer and a gate layer is filled in the second trench.

10,400‧‧‧Base

12‧‧‧General word line

14‧‧‧Dummy word line

16‧‧‧Insulation

18, 19‧‧‧Doped area

20‧‧‧ bit line contact window

22‧‧‧ bit line

24‧‧‧Capacitive contact window

26‧‧‧ Storage Capacitor

28, 402‧‧‧ shallow trench isolation structure

404‧‧‧active area

406‧‧‧Oxide layer

407‧‧‧ nitride layer

408‧‧‧etch stop layer

410‧‧‧ Cover layer

412‧‧‧Material layer

414‧‧‧ recessed area

416‧‧‧ spacer

418‧‧‧First District

420‧‧‧Second District

422‧‧‧ first trench

424‧‧‧Second trench

426‧‧‧Dummy gate layer

428‧‧ ‧ gate layer

430‧‧ ‧ gate dielectric layer

432‧‧‧first insulation

434‧‧‧Second insulation

600, 700‧‧‧ dynamic random access memory device

W1‧‧‧first width

W2‧‧‧second width

D1‧‧‧first depth

D2‧‧‧second depth

D3‧‧‧First distance

D4‧‧‧Second distance

S‧‧‧ displacement

Figure 1 is a schematic cross-sectional view showing a conventional dynamic random access memory device.

2 is a cross-sectional view showing a dynamic random access memory device in accordance with an embodiment of the present invention.

3A to 3H are schematic plan views showing an intermediate manufacturing stage of a dynamic random access memory device according to an embodiment of the present invention.

4A to 4H are schematic cross-sectional views taken along line 4-4' of Figs. 3A to 3H, respectively.

5A to 5H are schematic cross-sectional views taken along lines 5-5' in Figs. 3A to 3H, respectively.

Figure 6 is a cross-sectional view showing a dynamic random access memory device in accordance with an embodiment of the present invention.

Figure 7 is a cross-sectional view showing a dynamic random access memory device in accordance with an embodiment of the present invention.

Hereinafter, a dynamic random access memory device according to an embodiment of the present invention will be described Production method. However, the present invention is to be understood as being limited to the details of the present invention.

FIG. 2 is a cross-sectional view showing an embodiment of a dynamic random access memory device according to an embodiment of the present invention, wherein the same components as those in FIG. 1 are denoted by the same reference numerals and the description thereof is omitted. In the present embodiment, the structure of the memory device is similar to that shown in FIG. 1, except that the shallow trench isolation structure 28 is substituted for the dummy word line 14. Shallow trench isolation structure 28 includes hafnium oxide, tantalum nitride, hafnium oxynitride, other suitable materials, or combinations of the foregoing. Since the trenches in the shallow trench isolation structure 28 and the trenches in which the general word lines 12 are disposed are not fabricated in the same process, the trench trench isolation layer 28 may have a trench depth deeper than the general word line 12 The depth of the trench is used to block the electron dispersion path in the C direction as described in FIG. 1, thereby reducing word line interference.

However, in the above configuration, the trenches of the shallow trench isolation structure 28 are generally formed by a lithography and etching process, and in the subsequent process steps, the general word line 12 is formed by a lithography and etching process. Groove. Therefore, the position of the subsequently formed groove is likely to occur with the displacement S different from the original design, as shown in FIG. This displacement S causes the area of the doped region 19 on one side to be relatively reduced while the area of the doped region 19 on the other side is relatively increased, resulting in a contact area between the doped region 19 having a relatively small area and the capacitive contact window 24. Reduced, resulting in higher contact resistance.

In order to improve the above problem, a method of fabricating a dynamic random access memory device according to an embodiment of the present invention will be described below with reference to FIGS. 3A to 3H, FIGS. 4A to 4H, and 5A to 5H. Wherein, the 3A to 3H drawings are drawn according to the present invention. A schematic plan view of an intermediate manufacturing stage of a dynamic random access memory device according to an embodiment, and FIGS. 4A to 4H are schematic cross-sectional views taken along line 4-4' of FIGS. 3A to 3H, respectively, and FIGS. 5A to 5H are respectively A schematic cross-sectional view along line 5-5' in the 3A to 3H drawings is shown. Referring to Figures 3A, 4A, and 5A, a substrate 400 is provided that includes germanium or other suitable semiconductor material. A plurality of shallow trench isolation structures 402 are formed in the substrate 400. The forming of the shallow trench isolation structure 402 may include: forming a formation region of the shallow trench isolation structure 402 on the substrate 400 using a lithography process, etching the formation region to form a deep trench, and filling with one or more dielectric materials. Groove. The complex active region 404 is defined by the shallow trench isolation structure 402 to form a dynamic random access memory device in subsequent processing steps.

Referring to FIGS. 3B, 4B, and 5B, two mask layers 410 spaced apart from each other are formed on the substrate 400. In an embodiment, the mask layer 410 can include a hafnium oxide layer 406 and a tantalum nitride layer 407 disposed thereon. Further, the yttrium oxide layer 406 and the tantalum nitride layer 407 may be formed using chemical vapor deposition. Thereafter, the tantalum nitride layer 407 and the underlying hafnium oxide layer 406 may be patterned using a lithography process and an etch process to form the cap layer 410 spaced apart from each other. The etching process includes: dry etching (for example, plasma etching, reactive ion etching (RIE) or other suitable etching process).

Thereafter, an etch stop layer 408 is formed on the substrate 400 between the mask layers 410. In an embodiment, the etch stop layer 408 comprises hafnium oxide. Further, the etch stop layer 408 can be formed using a thermal oxidation process or a deposition process. Next, a material layer 412 is formed conformally on the substrate 400 having the mask layer 410 and the etch stop layer 408 such that the material layer 412 forms a recessed region 414 between the mask layers 410. In an embodiment, material layer 412 includes polysilicon. Furthermore, chemical vapor can be used A deposition or other suitable deposition process forms a layer 412 of material.

Please refer to the 3C, 4C, and 5C diagrams for compliance. A second material layer (not shown) is on the material layer 412. In an embodiment, the second material layer may include tantalum nitride, tantalum oxide, or a combination thereof. Then, by performing an etching process (eg, anisotropic etching) on the second material layer, two spacers 416 are formed on the opposite sidewalls of the recessed region 414 to be between the spacers 416. A first zone 418 is defined and two second zones 420 are defined between the spacers 416 and the masking layer 410.

Next, the structure of the 3C, 4C, and 5C is increased. The re-etching process is as shown in Figures 3D to 3F, 4D to 4F, and 5D to 5F below.

Please refer to the 3D, 4D, and 5D, with the spacer 416 As an etch mask, the material layer 412 is etched to expose the etch stop layer 408 of the first region 418. The etching process can include dry etching (eg, plasma etching, reactive ion etching, or other suitable etching process).

Please refer to Figures 3E, 4E and 5E for etching removal. The etch stop layer 408 of the first region 418 is exposed to the substrate 400 of the active region 404. Next, the spacer 416 and the mask layer 410 are used as an etch mask to etch the material layer 412 located in the second region 420 to expose the etch stop layer 408. In one embodiment, since the material layer 412 and the substrate 400 include germanium, the substrate 400 in the first region 418 is simultaneously etched during the etching of the material layer 412, while an opening 419 is formed in the substrate 400 of the first region 418. The etching process described above can include dry etching (eg, plasma etching, reactive ion etching, or other suitable etching process).

Please refer to the 3F, 4F, and 5F, and the etching is at the second. The etch stop layer 408 of the region 420 is exposed to the substrate 400. Then, the substrate 400 under the opening 419 of the first region 418 is etched, and the substrate 400 of the second region 420 is simultaneously etched to form a first trench 422 and two in the substrate 400 of the first region 418 and the second region 420. A second trench 424, wherein the first trench 422 has a first width w1 and the second trench 424 has a second width w2. The etching process described above includes dry etching (eg, plasma etching, reactive ion etching, or other suitable etching process). In the present embodiment, an opening 419 is formed in the substrate 400 of the first region 418 (as shown in FIG. 4E), so after the trench etching process, the first trench 422 is located in the first region 418. The depth D1 will be deeper than the depth D2 of the second trench 424 located in the second region 420.

In addition, in the present embodiment, the thickness of the material layer 412 can be controlled by The width and the width of the spacer 416 (i.e., the thickness of the second material layer) are varied to change the dimensions of the first width w1 and the second width w2. In this embodiment, the first width w1 may be greater than the second width w2. In another embodiment, the first width w1 may be equal to the second width w2.

Next, sidewalls and bottoms of the first trench 422 and the second trench 424 A dielectric layer, such as hafnium oxide, is formed on the portion to serve as the gate dielectric layer 430. Thereafter, a metal barrier layer (not shown) or an adhesive layer such as titanium, tantalum, titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof may be selectively formed on the gate dielectric layer 430.

Next, a mask layer 410 and a spacer 416 on the substrate 400 are covered with a conductor layer (not shown) and filled into the first trench 422 and the second trench 424. In an embodiment, the conductor layer comprises tungsten (W) or other suitable gate material and may be formed using physical vapor deposition or other suitable deposition process. A planarization process (eg, a chemical mechanical polishing (CMP) process) can be applied to the conductor layer to the exposed The gap wall 416 is exited.

After the planarization process, the conductor layer is etched back The process is such that a dummy gate layer 426 is formed in the first trench 422 and a gate layer 428 (as a word line) is formed in the second trench 424. In this embodiment, since the first width w1 of the first trench 422 is greater than the second width w2 of the second trench 424, the etch back rate of the conductor layer in the first trench 422 is greater than that in the second trench 424. The etch back rate of the conductor layer, which in turn causes a first distance D3 between the upper surface of the substrate 400 and the upper surface of the dummy gate layer 426, is greater than a distance between the upper surface of the substrate 400 and the upper surface of the gate layer 428. Two distances D4. In some embodiments, the difference between the first distance D3 and the second distance D4 is 10 nm.

Please refer to FIG. 3G, FIG. 4G and FIG. 5G on the substrate 400. The mask layer 410 and the spacer 416 are covered with a first insulating layer 432 and filled in the first trench 422 and the second trench 424. In an embodiment, the first insulating layer 432 may include tantalum nitride and may be formed using chemical vapor deposition or atomic layer deposition (ALD). Next, a planarization process (for example, a chemical mechanical polishing (CMP) process) is performed on the first insulating layer 432, wherein the material layer 412 under the spacers 416 is used as a planarization stop layer to remove the spacers 416 to stop and expose A layer of material 412 located below it.

Please refer to the 3H, 4H, and 5H for an etching process. The process is to remove the material layer 412. In an embodiment, the etching process includes dry etching (eg, plasma etching, reactive ion etching, or other suitable etching process) or wet etching. Next, a second insulating layer 434 is formed on the yttrium oxide layer 406 and the first insulating layer 432 and filled in a space formed by the material removing layer 412. In some embodiments, the second insulating layer 434 has the same material as the yttrium oxide layer 406 and can be used. Formed by vapor deposition. The second insulating layer 434 is then subjected to a planarization process (eg, a chemical mechanical polishing (CMP) process) to expose the first insulating layer 432.

Finishing the structure as shown in Figures 3H, 4H, and 5H Thereafter, doped regions 18 and 19 (ie, source/drain regions) may be formed in active region 404 of substrate 400 using conventional metal oxide half (MOS) transistor processes, metallization processes, and capacitor processes, and A bit line contact window 20, a bit line 22, a capacitive contact window 24, and a storage capacitor 26 are formed over the substrate 400 to complete a dynamic random access memory device 600, as shown in FIG.

According to the above embodiment, the first depth D1 of the first trench 422 is greater than The second depth D2 of the second trench 424 can thus be blocked from the surface of the gate layer 428 in the second trench 424 by applying a negative bias voltage to the dummy gate layer 426 in the first trench 422. The path of electrons to adjacent memory devices, thereby improving the phenomenon of word line interference between adjacent memory devices.

Furthermore, since the first width w1 of the first trench 422 is larger than the second trench The second width w2 of the trench 424, such that the first distance D3 between the upper surface of the substrate 400 and the upper surface of the dummy gate layer 426, may be greater than the second distance between the upper surface of the substrate 400 and the upper surface of the gate layer 428 Distance D4. As a result, the dummy gate layer 426 is longer than the adjacent doping region 19 (eg, the drain region) compared to the gate layer 428, and thus a negative bias is applied to the dummy gate layer 426. It can reduce or prevent the occurrence of gate-induced buckling leakage current to improve or maintain the performance of the memory device.

In addition, since the first trench 422 and the second trench 424 are in the same etch Formed in the engraving process, and the subsequent gate layer 428 and the dummy gate layer 426 can be formed by a self-alignment process, so the first trench 422 and the second trench The groove 424 does not produce a displacement that is inconsistent with the original design, so that an increase in contact resistance between the doped region 19 and the capacitive contact window 24 due to a decrease in contact area can be avoided.

Please refer to FIG. 7 , which illustrates the dynamics of another embodiment of the present invention. The random access memory device 700. The same components as those in the seventh embodiment are denoted by the same reference numerals and the description thereof will be omitted. Different from the dynamic random access memory device 600 of FIG. 6, the first width w1 of the first trench 422 in the dynamic random access memory device 700 of the embodiment is equal to the second width w2 of the second trench 424, so that the substrate A first distance D3 between the upper surface of the 400 and the upper surface of the dummy gate layer 426 is equal to a second distance D4 between the upper surface of the substrate 400 and the upper surface of the gate layer 428.

According to the embodiment, similarly, due to the first of the first trenches 422 The depth D1 is greater than the second depth D2 of the second trench 424, thereby improving the phenomenon of word line interference between adjacent memory devices. Moreover, since the first trench 422 and the second trench 424 are formed in the same etching process, and the subsequent gate layer 428 and the dummy gate layer 426 are formed through a self-aligned process, the doped region can be avoided. The contact resistance is increased between the contact opening window 19 and the capacitor contact window 24 due to a decrease in contact area.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can be modified and retouched without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

18, 19‧‧‧Doped area

20‧‧‧ bit line contact window

22‧‧‧ bit line

24‧‧‧Capacitive contact window

26‧‧‧ Storage Capacitor

400‧‧‧Base

404‧‧‧active area

422‧‧‧ first trench

424‧‧‧Second trench

426‧‧‧Dummy gate layer

428‧‧ ‧ gate layer

430‧‧ ‧ gate dielectric layer

W1‧‧‧first width

W2‧‧‧second width

D1‧‧‧first depth

D2‧‧‧second depth

D3‧‧‧First distance

D4‧‧‧Second distance

600‧‧‧ Dynamic Random Access Memory

Claims (10)

A manufacturing method of a dynamic random access memory device, comprising: forming two mask layers spaced apart from each other on a substrate; forming a material layer on the substrate having the mask layers to make the material Forming a recessed region between the mask layers; forming two spacers on opposite sidewalls of the recessed region to define a first region between the spacers and at the spacers Two second regions are defined between the mask layers; the mask layer and the spacers are used as an etching mask to perform a multiple etching process to the substrate in the first region and the second regions Correspondingly, a first trench and two second trenches are formed, wherein a depth of the first trench is deeper than a depth of the second trenches; and a dummy gate layer is filled in the first trench And filling a gate layer in the second trenches. The method of manufacturing a dynamic random access memory device according to claim 1, wherein an etch stop layer is formed on the substrate between the mask layers before forming the material layer. The method of fabricating a dynamic random access memory device according to claim 2, wherein the multiple etching process comprises: etching the material layer to expose the etch stop layer in the first region; etching is located in the first region The etch stop layer to expose the substrate; etching the substrate in the first region and simultaneously etching the material layer in the second regions to form an opening in the substrate of the first region and exposing The etch stop layer located in the second regions; Etching the etch stop layer in the second regions to expose the substrate; etching the substrate under the opening and the second regions to form the substrate in the first region and the second regions a first trench and the second trenches. The method of manufacturing a dynamic random access memory device according to claim 1, wherein the first trench has a first width, and the second trench has a second width, the first width being greater than The second width. The method of manufacturing a dynamic random access memory device according to claim 4, wherein the first width is greater than the second width by controlling a thickness of the material layer and a width of the spacers. The method of manufacturing a dynamic random access memory device according to claim 4, wherein the upper surface of the substrate and the upper surface of the dummy gate layer have a first distance, and the upper surface of the substrate is There is a second distance between the upper surfaces of the gate layer, and the first distance is greater than the second distance. The method of manufacturing a dynamic random access memory device according to claim 6, wherein the difference between the first distance and the second distance is 10 nm. The method of manufacturing a dynamic random access memory device according to claim 1, wherein the first trench has a first width, and the second trench has a second width, the first width being equal to The second width. The method of manufacturing a dynamic random access memory device according to claim 8, wherein the first width is equal to the second width by controlling a thickness of the material layer and a width of the spacers. The method of manufacturing a dynamic random access memory device according to claim 8, wherein an upper surface of the substrate and an upper surface of the dummy gate layer There is a first distance between the upper surface of the substrate and the upper surface of the gate layer, and the first distance is equal to the second distance.