TW200814215A - Overlay mark, method for forming the same and application thereof - Google Patents

Overlay mark, method for forming the same and application thereof Download PDF

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Publication number
TW200814215A
TW200814215A TW95134174A TW95134174A TW200814215A TW 200814215 A TW200814215 A TW 200814215A TW 95134174 A TW95134174 A TW 95134174A TW 95134174 A TW95134174 A TW 95134174A TW 200814215 A TW200814215 A TW 200814215A
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Taiwan
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ditches
wafer layer
pattern
layer
strip
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TW95134174A
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Chinese (zh)
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TWI313904B (en
Inventor
Chih-Hao Huang
Chin-Cheng Yang
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Macronix Int Co Ltd
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Publication of TWI313904B publication Critical patent/TWI313904B/en

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Abstract

An overlay mark for checking the alignment accuracy between a lower layer and a lithography process for defining an upper layer is described, including a part of the lower layer having two first x-directional trenches, two first y-directional trenches, two second x-directional trenches and two second y-directional trenches therein, and two x-directional and two y-directional photoresist bars thereover that are surrounded by the trenches and formed in the lithography process. When the lower layer is fully aligned with the lithography process, the intersection of the central line of the two first x-directional trenches and that of the two first y-directional trenches, the intersection of the central line of the two second x-directional trenches and that of the two second y-directional trenches and the intersection of the central line of the two x-directional photoresist lines and that of the two y-directional photoresist lines coincide with each other.

Description

200814215 P950095 21324twf.doc/006 九、發明說明: [發明所屬之技術領域】 本發明是有關於-種IC製程所用的重疊標記㈣柳 證幻,且特別錢於可用以檢查-下晶圓層與用以定義-上曰圓層之《彡製程之卩⑽對準度(alignment accuracy)的 重豐標記,其製造方法,以及其在對準度檢查上的應用。 【先前技術】 • ^著ic製程的線寬持續縮小,元件❺關鍵尺寸㈣⑽ dimension ’ CD)的控制愈來愈重要。當製程需要在一晶圓 層上形成圖案配置型態不同的兩區域時,常須對兩區域之 光阻層進行曝光條件不同的兩:欠曝光 程’則吏各區域料有預定的關鍵尺寸。為 ,兩區域與勉另—晶圓層之間的對準度,先前技術會在 该另-晶圓層被圖案化之前,以下述方法形成重疊標記。 請參照® 1A,在使用—光罩對晶目1〇〇之第一元件區 1〇2曝光時,即同時於非元件區之部分下晶圓層106上的 光阻層108中形成兩γ向條狀曝光區⑽與⑽ =式起見’在此圖及以下各圖中所用之光罩及元件區丄 下曰曰圓層(圖案)、光阻層(圖案)等皆省略未繪出。 =參照圖1B’接著使用另一光罩對第二元件區1〇4 开it即同時於該部分下晶圓層106上的光阻層舰中 =成兩條X向條狀曝光區114a與114b。各曝光區ii2a、 、114a及114b中的光阻材料會在後續的顯影 4件區中的曝规_被除去,因此在後仙以形成一 5 200814215 P950095 21324twf.doc/006 弟二70件區1〇2、104之下晶圓層圖案的侧製程中,兩停 Y向溝渠心與122b及兩條χ向溝渠伽與⑽會形 成在該部分下晶圓層1〇6中,如圖1C所示。 ,請參照圖1C,於後續之上晶圓層(未緣示)形成後,以 -微影製朗時形成元件區的光賴案,以及作為重疊 記之一部分的二X向及二Y向條狀光阻圖案⑽。以上各 溝木122a、122b、124a、124b及條狀光阻圖案13〇的位 安排方式是:當該微影製程與第—元件區撤在X方向完 全對準時’與第-元件區l02同時定義之兩條γ向溝渠 =2a與」22b的中線與二γ向條狀光阻圖案⑽的中線重 :’當該微影製程與第二元件㊄1〇4在γ方向完全對準 =1二元件區104同時定義之兩條X向溝渠伽盘 124b的中線與二X向條狀光阻圖案⑽的中線重合。” 因此,量測二丫向條狀光阻圖案m 渠一:既的距離⑽咖,即可得知該微影製程= -兀件區102在X方向上的對準度;量測二χ向條狀 圖案m的中線與χ向溝渠⑽⑽的距離13切⑽, 即可知該微影製程與第二元件區刚在γ方向的對準度。 然=使用上述重叠標記時並無法求得該微 f 一讀區搬在γ方向上的對準度,以及其與第1元;牛 區104在X方向上的對準度。因此 度檢查上的功⑽^全。 在對準 【發明内容】 本發明提供一種重疊標記,用以檢查一下晶圓層與用 6 200814215 P950095 21324twf.doc/〇〇6 以定義 工曰日lij層之微影製程之間的 本發明並提供一種上述重疊標記的製^ 本發明並提供一種檢查對準度的方 / 疊標記,以檢查由雙重曝光製 之成上述重 以定義一上晶圓層之微影製程之_=;了晶圓層和用 本發明之重豐標記包括下晶圓声一 二X向及二γ向條狀光阻圖案。1曰:;=及其上方的 有二第-X向溝渠、二第—中 述:、ί::二? 二γ向條狀光阻圖案被前 过各溝木所I,且疋由前述微影製程所 下晶圓層與郷製程^完全解時 7田= 渠之中線與該二第一 γ向溝渠之中線的交== =之中線與該二第二γ向溝渠之中線的交點,以及二乂 ϋ光阻圖案之中線及二γ向條狀光阻圖案之中線的交 點三者重合。 在某些實施例中,前述下晶圓層由第一與第二曝光步 驟所定義,第-X向溝渠及第-Υ向溝渠由第—曝光步驟 =疋義’第,X向溝渠及第二γ向溝渠由第二曝光步驟所 疋義。此第一與第二曝光步驟例如是組成一雙重曝光製 私’其中第-與第二曝光步驟例如分別用來定義該下晶圓 層的-圖案密集區與-圖案稀疏區。圖案密集區例如是一 記憶胞陣列區,且圖案稀疏區例如是一周邊電路區。該圖 案則例如是接觸窗開口的圖案。 在某些實施例中,雨述二第—χ向溝渠位於二第二χ 7 200814215 P950095 21324twf.doc/006 向溝渠的外側,同時 J 汁不’丨儿於二弟二γ向溝渠 的外側。在-較佳實施例中,當前述下 程 之間完全對準時,二第-X向溝渠與二第一丫向二二 ί::Γ且二第X二X向溝渠與該二第二γ向轉定義出 形’且―χ向及—γ向條狀光阻圖案定義 形0 本發明之重疊標記的製造方法如下。此 下晶圓層的同時,於其-部分中形成二第_χ^在;^ 第- γ向溝渠、二第二X向溝渠及二第二γ向溝= =後續的微影製程中’於該部分下晶圓層的上方:成二 寸;及:^向條f光阻圖案,其被前述各溝渠所圍繞。當 刖逑下晶圓層與微影製程之間完全對準時,二一 渠之中線與二第一 Y向溝渠之中線的交點、 ^ ^中線與二第二γ向溝渠之中線的交點,以 者^圖案之中線及向條狀光阻圖案之中線的交點三 f上述方法的某些實施例中,下晶圓層是 —曝光步驟所定義,第一 x向溝渠及第一 二弟 曝光步驟所定義,且第1向溝渠及第 弟一 暖本丰挪私―μ 一 h丹木汉弟一 γ向溝渠由第二 :七‘所疋義。弟—與第二曝光步驟例如是組成一雔 *光抽。此時在該部分下晶_巾形成前述x ^ j的方法例如是下述者。首先利用第一 = 土:晶圓層之光阻層中形成二第—x向條狀曝光 向條狀曝光區,其分別對應前述二第一 X向溝渠及一 第。 。 。 。 。 。 。 It is used to define the "heavy mark" of the "10" alignment accuracy of the upper layer, the manufacturing method thereof, and its application in the alignment check. [Prior Art] • The line width of the ic process continues to shrink, and the control of the component ❺ key size (4) (10) dimension ’ CD is becoming more and more important. When the process needs to form two regions with different pattern configurations on one wafer layer, it is often necessary to perform two exposure conditions for the photoresist layers of the two regions: underexposure process, then each region has a predetermined critical dimension. . For the alignment between the two regions and the other wafer layer, the prior art would form an overlap mark in the following manner before the other wafer layer is patterned. Please refer to ® 1A to form two γ in the photoresist layer 108 on the wafer layer 106 under the portion of the non-element region when the photomask is used to expose the first element region 1〇2 of the crystal lattice 1〇〇. To the strip exposure areas (10) and (10) =, the masks and component regions used in this figure and the following figures are omitted (not shown), the photoresist layer (pattern), etc. are omitted. . Referring to FIG. 1B', the second element region 1 〇 4 is then turned on using another reticle, that is, simultaneously in the photoresist layer on the portion of the lower wafer layer 106 = two X-direction strip-shaped exposure regions 114a and 114b. The photoresist material in each of the exposed regions ii2a, 114a and 114b will be removed in the subsequent development of the 4 regions, so that it will form a 5 200814215 P950095 21324twf.doc/006 In the side process of the wafer layer pattern under 1〇2, 104, the two stop Y-direction trench cores and 122b and the two trench trenches (10) are formed in the lower wafer layer 1〇6, as shown in Fig. 1C. Shown. Referring to FIG. 1C, after the formation of the wafer layer (not shown), the light-emitting case of the component region is formed by the lithography process, and the two X-directions and the second Y-direction are used as a part of the overlap. Strip photoresist pattern (10). The above-mentioned trenches 122a, 122b, 124a, 124b and the strip photoresist pattern 13 are arranged in such a manner that when the lithography process is completely aligned with the first component region in the X direction, 'the same as the first component region 102 The definition of the two γ-direction trenches = 2a and 22b of the center line and the center line of the two γ-direction strip-shaped photoresist pattern (10): 'When the lithography process is completely aligned with the second element 〇1〇4 in the γ direction= The center line of the two X-direction trenches 124b defined by the two element regions 104 coincides with the center line of the two X-direction strip photoresist patterns (10). Therefore, the measurement of the two-direction strip-shaped photoresist pattern m: one distance (10) coffee, can be known that the lithography process = - the alignment of the element region 102 in the X direction; The distance between the center line of the strip pattern m and the distance 13 from the channel to the trench (10) (10) is cut (10), and the alignment degree of the lithography process and the second element region in the γ direction is known. However, the above overlapping mark cannot be obtained. The alignment of the micro-f read zone in the gamma direction, and its alignment with the first element; the bull zone 104 in the X direction. Therefore, the work on the degree check (10) is complete. The present invention provides an overlay mark for inspecting the wafer layer and the invention between 6 200814215 P950095 21324 twf.doc/〇〇6 to define the lithography process of the work layer lij layer and providing an overlay mark as described above. The present invention also provides a square/stack mark for checking the alignment to check the lithography process by double exposure to define an upper wafer layer. The invention of the heavy mark includes the lower wafer sound one-two X-direction and two-γ-direction strip-shaped photoresist pattern. 1曰:;= and above There are two first-X ditches, two first-mentioned:, ί:: two? two γ-direction strip-shaped photoresist patterns are passed through the trenches I, and the wafer layer is formed by the aforementioned lithography process When the complete process is completed, the intersection of the middle line of the channel and the line of the first γ to the middle of the ditch == = the intersection of the middle line and the line of the second γ to the ditch, and the second line The intersection of the tantalum photoresist pattern line and the intersection of the lines of the two gamma-direction strip-shaped photoresist patterns. In some embodiments, the foregoing lower wafer layer is defined by the first and second exposure steps, the first - The X-direction ditches and the first-direction ditches are defined by a second exposure step by the first exposure step = the first step, the X-direction ditches and the second γ-direction ditches. The first and second exposure steps are, for example, one. The double exposure process is in which the first and second exposure steps are respectively used to define a pattern-dense area and a pattern-sparse area of the lower wafer layer, respectively. The pattern-dense area is, for example, a memory cell array area, and the pattern sparse area is for example Is a peripheral circuit area. The pattern is, for example, a pattern of contact window openings. In some embodiments, the rain is described as a ditches于二第二χ 7 200814215 P950095 21324twf.doc/006 To the outside of the ditch, while the J juice is not on the outside of the second dynasty gamma ditches. In the preferred embodiment, when the aforementioned downtime is completely When aligned, the second-X-direction ditches and the second first 丫 ί ί Γ Γ 二 二 二 二 二 二 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 且 且 且 且 且 且The photoresist pattern defines the shape 0. The method for manufacturing the overlap mark of the present invention is as follows. At the same time as the lower wafer layer, two _ χ 在 在 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ Ditch and two second gamma groove = = in the subsequent lithography process 'below the lower part of the wafer layer: two inches; and: ^ to the strip f photoresist pattern, which is surrounded by the aforementioned trenches. When the underlying wafer layer and the lithography process are perfectly aligned, the intersection of the middle line of the two-channel and the middle line of the two first Y-channels, the ^^ center line and the second second γ-direction trench line The intersection of the pattern and the intersection of the line and the line of the strip-shaped photoresist pattern. In some embodiments of the above method, the lower wafer layer is defined by the exposure step, the first x-ditch and The first two brothers are defined by the exposure steps, and the first ditches and the younger brothers are warm and privately--μ一h 丹木汉弟一 γ向沟渠 is the second: seven's righteousness. The brother-and the second exposure step is, for example, a composition* light pumping. The method of forming the aforementioned x ^ j in this portion of the undergarment is, for example, the following. First, using the first = soil: the photoresist layer of the wafer layer forms a second-x-direction strip-shaped exposure to the strip-shaped exposure area, which respectively corresponds to the two first X-direction ditches and one

在上述方法的某些實施例中,在該部分下晶圓層中形 成各溝渠的方法例如包括下列步驟。首先利用第一曝光步^ 驟在用以定義下晶圓層之光阻層中形成分別對應前^二^ X向溝渠及二第一 Υ向溝渠的二第一 X向條狀曝光區 及二第一 γ向條狀曝光區。接著利用第二曝光步驟在光阻 層中形成分別對應前述二第二X向溝渠及二第二υ向溝渠 200814215 21324twf.doc/006 黛著利用第二曝光步驟在光阻芦中开Μ 弟二X向條狀曝光區及-繁你兀丨且智中形成二 應前述二第二X向溝Γ ϋ曝光區,其分別對 影夢程除去冬眼#厂:及—弟一 γ向溝渠。然後利用一顯 衣締去各曝趣巾的紐㈣ j 刻下晶圓層,之後再除去光阻層。 w層為罩幕飿 本發明之檢查對準度的方法如下田 =其步驟包括:於定義下晶圓層的同時,m =第-曝光步驟所定義的二第_x向溝渠及二= 向溝朱,以及由第二曝光步驟 二第_ Y6、、番泪· + A 丨心我扪一弟一 X向溝渠及 弟一 γ向“,在進行之後的微 下晶圓層上形成二x向及二¥向 ;„分 二,,狀,案之中線及:Y向條狀光』 回木、水的父點、一第一 X向溝渠之中線與二第一 γ白 溝渠之中線的交點,以及二第二Μ溝渠之中線盘二第二 Υ向溝渠之中線的交點三者重合。接著量測前述二χ向及 二γ向條狀光阻圖案相對於上述各溝渠的位置,以估算下 晶圓層與前述微影製程之間的X、Υ方向對準度。斤 9 200814215 21324twf.doc/006 = =:=區及二第二Y向條狀曝光區。然後 湘心4除去各曝光區中的光阻材料 為罩幕㈣下晶_,紐再去除光阻層。 曰 所本發明之重疊標記,即可檢查第—曝光製程In some embodiments of the above methods, the method of forming the trenches in the portion of the lower wafer layer includes, for example, the following steps. Firstly, using the first exposure step, two first X-direction strip exposure regions corresponding to the front and the second X-direction ditches and the two first ditches are formed in the photoresist layer for defining the lower wafer layer and the second The first gamma is oriented toward the strip. Then, using the second exposure step, the two second X-direction ditches and the second second ditches are respectively formed in the photoresist layer, and the second exposure step is used in the photoresist reed. The X-direction strip-shaped exposure area and the formation of the two-in-one and the middle of the wisdom should be the second and second X-direction gully ϋ exposure areas, which respectively remove the winter eye #厂: and - the brother-γ gully. Then, using a display, the wafer layer of each of the exposed towels is cut, and then the photoresist layer is removed. The w layer is the mask. The method for checking the alignment of the present invention is as follows. The steps include: while defining the lower wafer layer, m = the first _x direction ditch and the second direction defined by the first exposure step Ditch Zhu, as well as by the second exposure step two _Y6,, tears + A 丨 heart, I 扪 one brother, one X-ditch, and the other one, ", on the micro-wafer layer after the formation of two x Toward and two ¥ direction; „2,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, The intersection of the center line and the intersection of the second line of the second and second ditches to the middle line of the ditch. Then, the positions of the second and second γ-direction strip-shaped photoresist patterns relative to the trenches are measured to estimate the alignment of the X and Υ directions between the lower wafer layer and the lithography process. Jin 9 200814215 21324twf.doc/006 = =:= area and two second Y-direction strip exposure areas. Then, Xiangxin 4 removes the photoresist material in each exposed area as a mask (4), and then removes the photoresist layer.曰 The overlap mark of the present invention can be used to inspect the first exposure process

晶圓層與之後微影製程所定義之上晶圓層 =^兩方向上的對準度,並檢查第二曝光製程所定義 之另ϋ下晶圓層與上晶圓層在χ&γ兩方向上的對準 度,而能提供更佳的對準度檢查效果。 為讓本發明之上述和其他㈣、特徵和優點能更明顯 易懂,下文特舉較佳實補,魏合所關式,作詳細說 明如下。 【實施方式】 圖2Α〜2C繪示本發明較佳實施例之重疊標記的製造 方法,其中圖2C繪示該重疊標記及其使用情形的示意圖。 雖然此較佳實施例之重疊標記是用以檢查由雙重曝光製程 所定義之下晶圓層和用以定義上晶圓層之微影製程之間的 對準度,但本發明之重疊標記的應用並不僅限於此,其例 如亦可用以檢查任何由非屬雙重曝光製程之兩次曝光步驟 所定義的下晶圓層和之後的微影製程之間的對準度。 請參照圖2Α,在對晶圓200之第一元件區202進行第 一曝光步驟時,即同時在位於非元件區中之部分下晶圓層 206上的光阻層208中形成兩Υ向條狀曝光區212a與212b 及X向條狀曝光區212c與212d,其中非元件區通常是切 割道(scribe line)區。第一元件區202與第二元件區204例 200814215 21324twf.d〇c/〇〇6 t有^圖案密集區’另—者是圖案稀疏區。圖案密 區例如是-記憶胞陣列區,圖案稀疏區例如是—周邊ςς 區’而該圖案例如是接觸窗開σ的圖案,此時 】 即是一介電層。 mmAlignment between the wafer layer and the wafer layer = ^ two directions defined by the subsequent lithography process, and checking the other underlying wafer layer and the upper wafer layer defined by the second exposure process are in χ & γ Alignment in the direction, which provides better alignment check results. In order to make the above and other (four), features and advantages of the present invention more comprehensible, the following is a better example, and the details of the invention are as follows. [Embodiment] Figs. 2A to 2C illustrate a method of manufacturing an overlay mark according to a preferred embodiment of the present invention, wherein Fig. 2C is a schematic view showing the overlap mark and its use. Although the overlay mark of the preferred embodiment is used to check the alignment between the wafer layer defined by the double exposure process and the lithography process for defining the upper wafer layer, the overlay mark of the present invention The application is not limited thereto, and it may, for example, also be used to check the alignment between any of the lower wafer layers defined by the two exposure steps other than the double exposure process and the subsequent lithography process. Referring to FIG. 2A, when the first exposing step of the first device region 202 of the wafer 200 is performed, that is, two bisector strips are formed in the photoresist layer 208 on the lower wafer layer 206 in the non-element region. Exposure regions 212a and 212b and X-direction strip exposure regions 212c and 212d, wherein the non-element regions are typically scribe line regions. The first element region 202 and the second element region 204 are examples of 200814215 21324 twf.d〇c/〇〇6 t having a pattern dense region and the other is a pattern sparse region. The pattern dense area is, for example, a memory cell array area, and the pattern thinning area is, for example, a peripheral ςς area, and the pattern is, for example, a pattern of contact window opening σ, which is a dielectric layer. Mm

、」青參照圖2B’接著使用另一光罩對第二元件區2〇4 進打第二曝光步驟時,即同時於該部分下晶圓層細上的 光阻層208中形成兩Y向條狀曝光區214a與21仆及X向 條狀曝光區214c與214d。各曝光區212a〜212d及21如〜 214d中的光阻材料會在後續的顯影製程中與元件區中的 曝光區同時被除去’因此在其後用以形成第—第二元件區 202、204之下晶圓層圖案的蝕刻製程中,對應之第一 γ向 溝渠222a與222b、第- X向溝渠2咖與而、第二γ 向溝渠224a與224b及第二X向溝渠2旅與224d會形成 在該部分下晶圓層206中,如圖2C所示。其中,溝準222&〜 222d由第-曝光步驟所定義,溝渠施〜2施則是由第二 曝光步驟所定義。 請參照圖2C,於-上晶圓層(未纷示)形成之後,進行 二微影製程關時形成元件區的光_案,以及作為重疊 標兄之-部分的二X向及二丫向條狀光阻圖案23〇,其位 在該部分下晶圓層206上,且被溝渠222a〜222d'及 224a〜224所圍繞。在以上製程中,溝渠222&〜2创、 224a〜224及條狀光阻圖案23〇的位置安排滿足以下條# : S下曰曰圓層與该微影製程之間完全對準時,兩條第一 X向 溝渠222c與222d之中線與兩條第一 γ向溝渠222a與22孔 11 200814215 P950095 21324twf.doc/006 之中線的交點、兩條第二χ向溝渠224c與224d之中線與 兩條第二Y向溝渠224a與224b之中線的交點,以及二又 向條狀光阻圖案230之中線及二γ向條狀光阻圖案23〇之 中線的交點三者重合。 另外,上晶圓層例如是一金屬層,此時溝渠222a〜222d 及224a〜224的位置即可藉由此金屬層的反射率變化來偵 測。在-貫施例中,下晶圓層為一介電層,其中圖案為接 觸自開口的圖案,且上晶圓層為一金屬層,此金屬層有部 分填入接觸窗開口,且有部分將被定義成導線。 接著,量測二Y向條狀光阻圖案23〇的中線與第一 γ 向溝渠222a/222b的距離232a/232b,柯得述 程與&第一元件區2〇2之下晶圓層圖案在x方向 度,里測二X向條狀光阻圖案230的中線與第一 χ向溝準 2-22-c/r^r離232e/232d,即可彳_述微影製程與第 -^二ϋΛ之下晶圓層_在γ方向上的對準度。量測 t阻圖案23G的中線與第二γ向溝渠施/ =4=34a/234b,即·彡製餘第二元件 二狀光I^FI^ P層圖案在X方向上的對準度;量測二Χ向 ^ 2st 234d ; X 224c/224d ^Referring to FIG. 2B', a second exposure step is performed on the second element region 2〇4 using another mask, that is, two Y-directions are simultaneously formed in the photoresist layer 208 on the portion of the lower wafer layer. The strip exposure regions 214a and 21 serve X-direction strip exposure regions 214c and 214d. The photoresist materials in each of the exposed regions 212a 212212 and 21, such as ~ 214d, are removed simultaneously with the exposed regions in the device regions in subsequent development processes, and thus are used to form the second - second component regions 202, 204 thereafter. In the etching process of the underlying wafer layer pattern, the corresponding first γ to the trenches 222a and 222b, the first-X ditches 2, the second γ to the ditches 224a and 224b, and the second X ditches 2 and 224d Will be formed in this portion of the lower wafer layer 206, as shown in Figure 2C. Wherein, the grooves 222 & 222d are defined by the first exposure step, and the trenches are defined by the second exposure step. Referring to FIG. 2C, after the formation of the upper wafer layer (not shown), the light pattern formed in the element region when the two lithography process is closed, and the two X-directions and the second direction as the overlap-parts A strip photoresist pattern 23 is placed on the portion of the lower wafer layer 206 and surrounded by trenches 222a-222d' and 224a-224. In the above process, the positions of the trenches 222 & 2, 224a to 224 and the strip photoresist pattern 23 are arranged to satisfy the following: #: S when the round layer is perfectly aligned with the lithography process, two The intersection of the first X-direction ditches 222c and 222d and the intersection of the two first γ-direction ditches 222a and 22 holes 11 200814215 P950095 21324twf.doc/006 and the two second ditches 224c and 224d The intersection with the line between the two second Y-direction trenches 224a and 224b, and the intersection of the two lines of the strip-shaped photoresist pattern 230 and the line of the two γ-direction strip-shaped photoresist patterns 23〇 coincide. Further, the upper wafer layer is, for example, a metal layer, and the positions of the trenches 222a to 222d and 224a to 224 at this time can be detected by the change in reflectance of the metal layer. In the embodiment, the lower wafer layer is a dielectric layer, wherein the pattern is a pattern contacting the opening, and the upper wafer layer is a metal layer, and the metal layer is partially filled with the contact opening and has a portion Will be defined as a wire. Next, measuring the distance 232a/232b between the center line of the two Y-direction strip-shaped photoresist patterns 23〇 and the first γ-direction trenches 222a/222b, and the wafers below the first element region 2〇2 The layer pattern is in the x-direction, and the center line of the two X-direction strip-shaped photoresist pattern 230 is measured and the first direction of the strip is 2-22-c/r^r away from 232e/232d, which can be used to describe the lithography process. The alignment of the wafer layer _ in the gamma direction with the first ^^. Measure the alignment between the center line of the t-resist pattern 23G and the second γ-drain channel /=4=34a/234b, that is, the alignment of the second element dimorphic light I^FI^P layer pattern in the X direction ; measurement of the second Χ 2 ^ ^ 234d ; X 224c / 224d ^

Md,即可得知該微影製 下晶圓層圖案在γ方向上的對# 凡件£ 204之 光製程還是第二曝α此’不論是第一曝 微影製程之間的對===層圖案’其與該 準度也就是下晶圓層H _ @上μ量測。此對 卞該微衫製程所定義之上晶圓層 200814215 ι^υυν) 21324twf.doc/006 圖案之間的對準度。 、另外,以本發明之重豐標記量測以兩次曝光製程所定 義之下晶圓層圖案與後續微影製程之間的對準度^方法旅 不僅限於上述者。以X方向的對準度量測為例,其可先求 出第一 Y向溝渠222a與相鄰之第二Y向溝渠224a的(第 一)中線位置、第一 Y向溝渠222b與相鄰之第二γ向溝渠 22仙的(第二)中線位置,以及二Υ向條狀光阻圖案no的 (第二)中線位置,再計算比較第一第三中線位置之間的距 離以及第二第三中線位置之間的距離。 另外,溝渠222a〜222d、224a〜224的較佳排列方式是 如圖2C所示之第一 X向溝渠222c與222d位於第二X向 溝渠224c與224d的外側’同時第一 Y向溝渠222a與222b 位於第二Y向溝渠224a與224b的外侧;或是第一 χ向溝 渠222c與222d位於第二X向溝渠224c與224d的内側, 同時第一 Y向溝渠222a與222b位於第二γ向溝渠224a 與224b的内側。亦即,由第一曝光製程所定義之溝渠圍繞 第二曝光製程所定義之溝渠,或是前者被後者所圍繞。 在一較佳實施例中,溝渠222a〜222d、224a〜224及X 向、Y向條狀光阻圖案230的配置方式是:當下晶圓層與 該微影製程之間完全對準時,第一 X向溝渠222c與222d 及第一 Y向溝渠222a與222b定義出第一矩形242,第二 X向溝渠224c與224d與第二Y向溝渠224a與224b定義 出第二矩形244,且X向及Y向條狀光阻圖案230定義出 最小的第三矩形250,3個矩形242、244與250的中心皆 13 200814215 tyDvvyj 21324twf.doc/006 重合。第二矩形244可在第一矩形242之内,如圖2C所 示;但反過來第一曝光製程所定義之溝渠所定義的第—矩 形在第二曝光製程所定義之溝渠所定義的第二矩形之内也 可以。 雖然本發明已以較佳實施例揭露如上,然其並非用以 限定本發明,任何熟習此技藝者,在不脫離本發明之精神 和範圍内,當可作些許之更動與潤飾,因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1A〜1C繪不習知一種重疊標記的製造方法,直中圖 1C繪示此重疊標記及其使用情形的示意圖。 八 圖2^〜2C綠示本發明較佳實施例之重疊標記的製造 =法’其中圖2C!會示該重疊標記及其使用情形的示意圖。 【主要元件符號說明】 100、200 :晶圓Md, it can be known that the lithography of the wafer layer pattern in the γ direction of the pair of parts of the light process of 204 or the second exposure of the 'this is the first exposure between the lithography process == = layer pattern 'which is measured with the accuracy of the lower wafer layer H _ @μ. The alignment between the patterns of the wafer layer 200814215 ι^υυν) 21324 twf.doc/006 defined by the micro-shirt process. In addition, the alignment between the wafer layer pattern and the subsequent lithography process defined by the double exposure process by the heavy mark measurement of the present invention is not limited to the above. Taking the alignment measurement in the X direction as an example, the first (first) center line position of the first Y-direction ditches 222a and the adjacent second Y-direction ditches 224a, and the first Y-direction ditches 222b and phases may be obtained first. The second (second) center line position of the adjacent second γ to the trench 22 sen, and the (second) center line position of the two-way strip photoresist pattern no, and then calculated between the first and third center line positions The distance between the distance and the second third centerline position. In addition, the preferred arrangement of the trenches 222a-222d, 224a-224 is that the first X-direction trenches 222c and 222d are located outside the second X-direction trenches 224c and 224d as shown in FIG. 2C while the first Y-direction trenches 222a and 222b is located outside the second Y-direction ditches 224a and 224b; or the first ditches 222c and 222d are located inside the second X-direction ditches 224c and 224d, while the first Y-direction ditches 222a and 222b are located in the second γ-direction ditches The inside of 224a and 224b. That is, the trench defined by the first exposure process surrounds the trench defined by the second exposure process, or the former is surrounded by the latter. In a preferred embodiment, the trenches 222a-222d, 224a-224 and the X-direction and Y-direction strip-shaped photoresist patterns 230 are arranged in such a manner that when the lower wafer layer is completely aligned with the lithography process, the first The X-direction ditches 222c and 222d and the first Y-direction ditches 222a and 222b define a first rectangle 242, and the second X-direction ditches 224c and 224d and the second Y-direction ditches 224a and 224b define a second rectangle 244, and the X-direction The Y-direction strip-shaped photoresist pattern 230 defines a minimum third rectangle 250, and the centers of the three rectangles 242, 244, and 250 are all coincident with each other, 200814215 tyDvvyj 21324twf.doc/006. The second rectangle 244 can be within the first rectangle 242, as shown in FIG. 2C; but in turn, the first rectangle defined by the trench defined by the first exposure process is the second defined by the trench defined by the second exposure process. It is also possible within the rectangle. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Figures 1A to 1C illustrate a method of manufacturing an overlay mark, and Figure 1C shows a schematic view of the overlap mark and its use. 8 Figures 2^ to 2C Green illustrate the fabrication of the overlay mark of the preferred embodiment of the invention = method where Figure 2C! shows the overlay mark and its use. [Main component symbol description] 100, 200: Wafer

102、104 :曝光條件不同的元件區 106、206 :部分之下晶圓層 108、208 :光阻層 112a、112b · Y向條狀曝光區 114a、114b : X向條狀曝光區 122a、122b : Y 向溝竿 124a、124b : X 向溝渠 130 · X向及γ向條狀光阻圖案 132a、132b、134a、134b :距離代號 200814215 P950095 21324twf.doc/006 202、204 :曝光條件不同的元件區 212a、212b:第一 Y向條狀曝光區 212c、212d:第一 X向條狀曝光區 214a、214b:第二Y向條狀曝光區 214c、214d:第二X向條狀曝光區 222a、222b :第一 Y向溝渠 222c、222d :第一 X向溝渠 224a、224b :第二Y向溝渠 224c、224d :第二X向溝渠 230 : X向及Y向條狀光阻圖案 232a〜232d、234a〜234d :距離代號 242、244、250 ··矩形 I-Γ、ΙΙ-ΙΓ :剖面線 15102, 104: element regions 106, 206 having different exposure conditions: partially underlying wafer layers 108, 208: photoresist layers 112a, 112b · Y-direction strip-shaped exposure regions 114a, 114b: X-direction strip-shaped exposure regions 122a, 122b : Y-direction groove 124a, 124b: X-direction trench 130 · X-direction and γ-direction strip-shaped photoresist patterns 132a, 132b, 134a, 134b: distance code 200814215 P950095 21324twf.doc/006 202, 204: components with different exposure conditions Areas 212a, 212b: first Y-direction strip-shaped exposure areas 212c, 212d: first X-direction strip-shaped exposure areas 214a, 214b: second Y-direction strip-shaped exposure areas 214c, 214d: second X-direction strip-shaped exposure areas 222a 222b: first Y-direction ditches 222c, 222d: first X-direction ditches 224a, 224b: second Y-direction ditches 224c, 224d: second X-direction ditches 230: X-direction and Y-direction strip-shaped photoresist patterns 232a-232d , 234a~234d: distance code 242, 244, 250 · · Rectangular I-Γ, ΙΙ-ΙΓ: section line 15

Claims (1)

200814215 P950095 21324twf.doc/006 十、申請專利範圍: 1. 一種重疊標記,用以檢查一下晶圓層與用以定義一 上晶圓層之一微影製程之間的對準度,包括: 該下晶圓層的一部分,其中有二第一 X向溝渠、二第 一Y向溝渠、二第二X向溝渠及二第二Y向溝渠;以及 二X向及二Y向條狀光阻圖案,位於該部分之該下晶 圓層的上方,且被該些溝渠所圍繞,該二X向及二Y向條 狀光阻圖案是由該微影製程所形成的,其中 當該下晶圓層與該微影製程之間完全對準時,該二第 一 X向溝渠之中線與該二第一 Y向溝渠之中線的交點、該 二第二X向溝渠之中線與該二第二Y向溝渠之中線的交 點,以及該二X向條狀光阻圖案之中線及二Y向條狀光阻 圖案之中線的交點三者重合。 2. 如申請專利範圍第1項所述之重疊標記,其中該下 晶圓層由第一與第二曝光步驟所定義,該二第一 X向溝渠 及該二第一 Y向溝渠由該第一曝光步驟所定義,該二第二 X向溝渠及該二第二Y向溝渠由該第二曝光步驟所定義。 3. 如申請專利範圍第2項所述之重疊標記,其中該第 一與該第二曝光步驟組成一雙重曝光製程。 4. 如申請專利範圍第3項所述之重疊標記,其中該第 一與該第二曝光步驟分別用以定義該下晶圓層的一圖案密 集區與一圖案稀疏區。 5. 如申請專利範圍第4項所述之重疊標記,其中該圖 案密集區為一記憶胞陣列區,且該圖案稀疏區為一周邊電 16 200814215 P950095 21324twf.doc/006 路區。 # 6·如申睛專利制第丨項所述之重叠標記,其中該二 第X、向/冓渠位於該二第二X向溝渠的外側,且該二第一 Y向溝渠位於該二第二Y向溝渠的外側。 7.如申請專利範圍第6項所述之重疊標記,其中當該 下晶圓層與該微影製程之間完全對準時,該二第一 χ向溝 渠與該二第一 γ向溝渠定義出一第一矩形,該二第二X向 P 溝渠與該二第二Y向溝渠定義出一第二矩形,且該二X向 ‘及二Υ向條狀光阻圖案定義出一第三矩形。 8·一種重疊標記的製造方法,該重疊標記是用以檢查 圖案化之一下晶圓層與用以定義一上晶圓層之一微影製程 之間的對準度,且該方法包括: 在圖案化該下晶圓層的同時,於該下晶圓層的一部分 中形成二第一 X向溝渠、二第一 γ向溝渠、二第二χ向 溝渠及二第二γ向溝渠;以及 在該微影製程中,於該部分之該下晶圓層的上方形成 υ 二χ向及二γ向條狀光阻圖案,其被該些溝渠圍繞,其中 當該下晶圓層與該微影製程之間完全對準時,該二第 一 X向溝渠之中線與該二第一 γ向溝渠之中線的交點、該 二第二X向溝渠之中線與該二第二γ向溝渠之中線的交 點,以及該一 X向條狀光阻圖案之中線及二γ向條狀光阻 圖案之中線的交點三者重合。 9·如申請專利範園第8項所述之重疊標記的製造方 法,其中該下晶圓層由第一與第二曝光步驟所定義,該二 17 200814215 P950095 21324twf.doc/006 f ΓΒΧ=#渠及該二第―Y向溝渠由該第—曝光步驟所定 光步驟所定義。 Υ向溝^⑭一曝 、本9項所述之重疊標記的製造方 Γι j/1弟第—曝光步驟組成—雙重曝光製程。 11.如申請專利範㈣K)項所述 法找下_切成麵_^包括 阳爲由弟—曝光步驟’在用以定義該下日日日圓層之一光 ; ,刺用^了—/—χ向溝渠及該二第—γ向溝渠; 弟r ί光步驟,在該光阻層中形成二第二χ向 :X二::及一第二γ向條狀曝光區,其分別對應該二第 一X向溝渠及該二第二丫向溝渠; 利用/貝影製程除去上述各曝光區中的光阻材料; 以5亥,阻層為罩幕餘刻該下晶圓層 ;以及 除去該光阻層。 ί; 法 又清專利範圍第10項所述之重疊標記的製造方 _第二曝光步驟分則來定義該下晶圓 層的-圖案密集區與一圖案稀疏區。 法,如^請專利範圍第12項所述之重疊標記的製造方 /、中忒圖案饴集區為一記憶胞陣列區,且該圖案稀疏 适為一周邊電路區。 、去,如申請專利範圍第8項所述之重壘標記的製造方 一中該一第一 χ向溝渠位於該二第二X向溝渠的外 18 200814215 P950095 21324twf.doc/006 侧’且n γ向溝渠位於該二第二Y向溝渠的外侧。 15.如申請專顺圍第14項所述之重疊標記的製造方 法,其中當該下晶圓層與該微影製程之間完全對 二第一 χ向溝渠與讀二第—Υ向溝狀義出-第-矩形: 该一弟向溝渠與該二第二Υ向溝紋義出-第二矩 形且j X向及—Υ向條狀光阻圖案定義出一第三矩形。 =-種檢查對準度的方法,心檢錢雙重曝 所疋義之-下晶圓層和用以定義一 之間的對準度,其中該雙重曝光製程包 ^ = 步驟,該方法包括: ,、弟一曝先 形成一重$標記,其步驟包括·· 下晶圓層時,於該下晶圓層的-部分中 形成由該弟一曝本半瞬α * 第- 丫向_ 疋義的二第I向溝渠及二 二二二;及二曝=驟所定義的二第 在進仃邊微影製程時,於該 ,形成二X向及二¥ :::= 準時,該-㈣製狀間完全對 干了必—入向條狀光 光阻圖案之中線的交點,以=二/向條狀 溝渠之中線與ΐ:第二^ί、Γ以及該二第二χ向 合;以及/、Λ α /'乐之中線的交點三者重 里測石亥—x向及二γ向條狀光阻圖案相對於各該溝渠 19 200814215 P950095 21324twf.doc/006 的位置,以估算該下晶圓層與該微影製程之間的χ方 準度與γ方向對準度。 τ 、π·如申請專觸m第16項所述之檢查檢查對準 方法,其中形成該些溝渠的方法包括: 利用該第-曝光步驟,在用以定義該下晶圓層之 阻層中,成分別對應該二第—χ向溝渠及該二第—Y 渠的=第—ί向條狀曝光區及二第—Y向條狀曝光區;/ 二第曝光t驟’在該光阻射形成分別對應該 光&及-第D ’ :及—第一γ向溝渠的二第二χ向條狀曝 先&及一弟二Υ向條狀曝光區; J、 利用i影製程除去各曝光區中的光阻材料; 亥光阻層為罩幕钱刻該下晶圓層;以及 去除該光阻層。 法 盆二H利视圍第16項所述之檢查對準度的方 恩與该第二曝光步驟分別用來定義該下曰η 層的-圖案密集區與—圖案稀疏區。 彡/下曰曰Η 法,二如該申圖;專二=第」8严述之檢查對準度的方 區為-周邊電路厂’…己仏胞陣列區’且該圖案稀疏 法 法 側 圍第19項所述之檢查對準度的方 -mi案為接觸窗開口之圖案。 々 =申^專利,第16項所述之檢查 且向溝渠位於該二第二χ向溝_卜 斗γ向溝渠位於該二第二丫向 20 200814215 P950095 21324twf.doc/006 22.如申請專利範圍第21項所述之檢查對準度的方 法,其中當該下晶圓層與該微影製程之間完全對準時,該 二第一 X向溝渠與該二第一 Y向溝渠定義出一第一矩形, 該二第二X向溝渠與該二第二Y向溝渠定義出一第二矩 形’且該二X向及二Y向條狀光阻圖案定義出一第三矩形。 C/ 21200814215 P950095 21324twf.doc/006 X. Patent application scope: 1. An overlay mark to check the alignment between the wafer layer and a lithography process for defining an upper wafer layer, including: a part of the lower wafer layer, wherein there are two first X-direction ditches, two first Y-direction ditches, two second X-direction ditches, and two second Y-direction ditches; and two X-direction and two Y-direction strip-shaped photoresist patterns Between the lower wafer layer of the portion and surrounded by the trenches, the two X-direction and two Y-direction strip photoresist patterns are formed by the lithography process, wherein the lower wafer When the layer is completely aligned with the lithography process, the intersection of the line between the two first X-direction trenches and the line of the two first Y-direction trenches, the second and second X-direction trenches and the second line The intersection of the lines of the two Y-direction trenches and the intersection of the lines of the two X-direction strip-shaped photoresist patterns and the lines of the two Y-direction strip-shaped photoresist patterns overlap. 2. The overlay mark of claim 1, wherein the lower wafer layer is defined by first and second exposure steps, and the two first X-direction trenches and the two first Y-direction trenches are The two second X-direction trenches and the two second Y-direction trenches are defined by the second exposure step as defined by an exposure step. 3. The overlay mark of claim 2, wherein the first and the second exposure steps comprise a double exposure process. 4. The overlay mark of claim 3, wherein the first and second exposure steps are respectively used to define a pattern dense area and a pattern sparse area of the lower wafer layer. 5. The overlap mark according to item 4 of the patent application, wherein the pattern dense area is a memory cell array area, and the pattern sparse area is a peripheral power 16 200814215 P950095 21324twf.doc/006 road area. #6· The overlapping mark according to the second aspect of the patent application system, wherein the two Xth, the direction, and the channel are located outside the second X channel, and the two first Y channel are located in the second Two Y to the outside of the ditch. 7. The overlap mark of claim 6, wherein when the lower wafer layer is completely aligned with the lithography process, the two first directional ditches and the two first gamma gullies are defined a second rectangle defines a second rectangle between the second X-direction P-ditch and the second Y-direction trench, and the two X-direction and the second-direction strip-shaped photoresist pattern define a third rectangle. 8. A method of fabricating an overlay mark for inspecting alignment between a patterned lower wafer layer and a lithography process for defining an upper wafer layer, and the method comprises: Forming the lower wafer layer, forming two first X-direction ditches, two first γ-direction ditches, two second ditches and two second γ-direction ditches in a portion of the lower wafer layer; In the lithography process, a second bismuth and a gamma ray strip pattern are formed over the lower wafer layer of the portion, and surrounded by the trenches, wherein the lower wafer layer and the lithography When the processes are completely aligned, the intersection of the two first X-direction trench line and the two first γ-to-ditch line, the second X-ditch line and the second γ-ditch The intersection of the center line and the intersection of the line of the one X-ray strip resist pattern and the line of the two γ-direction strip-shaped photoresist patterns coincide. 9. The method of manufacturing the overlay mark according to item 8 of the patent application, wherein the lower wafer layer is defined by the first and second exposure steps, the second 17 200814215 P950095 21324twf.doc/006 f ΓΒΧ=# The channel and the two first-Y ditches are defined by the light step of the first exposure step. Υ 沟 ^ 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 11. If the method described in the application patent (4) K) finds the _ cut into the surface _ ^ including the yang is the younger - the exposure step 'in the light used to define the next day of the Japanese yen layer; χ 沟 沟 及 及 及 及 及 及 及 及 及 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; The first X-direction ditches and the second second ditches should be removed; the photoresist material in each of the exposed regions is removed by a /Biking process; and the lower wafer layer is engraved with a resist layer of 5 hai; The photoresist layer is removed. The method of manufacturing the overlay mark described in item 10 of the patent scope is defined by the second exposure step to define a pattern-dense area and a pattern sparse area of the lower wafer layer. For example, the manufacturer of the overlapping mark/the medium-sized pattern 饴 collecting area described in Item 12 of the patent scope is a memory cell array region, and the pattern is sparsely suitable as a peripheral circuit region. And, as in the manufacturer 1 of the heavy barrier mark described in claim 8 of the patent scope, the first first ditches are located on the outer side of the second X-direction ditches 200814215 P950095 21324twf.doc/006 side and n The γ-direction ditches are located outside the two second Y-trench channels. 15. The method for manufacturing an overlay mark as described in claim 14, wherein when the lower wafer layer and the lithography process are completely opposite to each other, the first slanting trench and the second slanting trench are The right-first rectangle: the first brother defines a third rectangle to the trench and the second second-direction groove-second rectangle and the j-X and --direction strip-shaped photoresist pattern. = - a method of checking the alignment, the double exposure of the heart test - the lower wafer layer and the definition of the alignment between the two, wherein the double exposure process package ^ = step, the method includes: The younger brother first forms a heavy $ mark, and the steps include: when the lower wafer layer is formed in the lower portion of the lower wafer layer, the first half of the lower wafer layer is formed by the younger one. The second I-direction ditches and the two-two-two-two; and the two-exposure--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- The shape is completely dry - the intersection of the line into the strip-shaped light-resistance pattern, the line between the =2/direction strip-shaped trench and the ΐ: the second ^, Γ and the second χ And /, Λ α / 'the intersection of the middle line of the music is measured by the position of the Shihai-x and γ-direction strip-shaped photoresist pattern relative to each of the trenches 19 200814215 P950095 21324twf.doc/006 to estimate The alignment between the lower wafer layer and the lithography process is aligned with the gamma direction. τ, π· The application of the inspection inspection alignment method described in Item 16 wherein the method of forming the trenches comprises: using the first exposure step in the resist layer for defining the lower wafer layer , respectively, corresponding to the second - χ 沟 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 该 该 该 及 及 及 及 及 / / / / / / / / / / / / / / / / / / / / / The formation of the light corresponding to the light & and - D ': and - the first γ to the ditches of the second χ 条 strip exposure & and a younger two Υ strip strip exposure area; J, the use of i shadow process Removing the photoresist material in each exposed region; the photoresist layer is a mask layer for etching the underlying wafer layer; and removing the photoresist layer. The inspection alignment and the second exposure step described in item 16 of the method are used to define the pattern-dense area and the pattern-sparse area of the lower 曰 layer, respectively.彡/下曰曰Η法,二如如申图;二二=第8” The square area of the inspection alignment is - peripheral circuit factory '... 仏 cell array area' and the pattern sparse method side The square-mi case of the inspection alignment described in item 19 is a pattern of contact window openings. 々=申^ patent, the inspection described in item 16 and located in the ditches in the second and second ditches _ _ γ y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y The method for checking the alignment according to the item 21, wherein when the lower wafer layer and the lithography process are completely aligned, the two first X-channels and the two first Y-channels define one The first rectangle defines a second rectangle 'the second X-direction trench and the second Y-direction trenches, and the second X-direction and the second Y-direction strip-shaped photoresist pattern define a third rectangle. C/ 21
TW95134174A 2006-09-15 2006-09-15 Overlay mark, method for forming the same and application thereof TWI313904B (en)

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