200814180 九、發明說明： 擎 【發明所屬之技術領域】 ' 树财關-種料體裝魏程，_是有_金氧半導 體(MOS)電晶體元件製程中對於間隙壁之移除。 【先前技術】 隨著半導體製程進入到深次微米時代，例如65奈米(nm) _ 以下之製程，對於MOS電晶體元件的驅動電流(drive 的提昇已顯得曰盈重要。為了改善元件的效能，目前業界已發 展出所謂的「應變矽(straineddlicon)技術」，其原理主要是使閘 極通道部分的石夕晶格產生應變，使電荷在通過此應變之閉極通 迢吋的移動力增加，進而達到*M〇s電晶體運作更快的目的。 基本上，矽晶格的應變可以藉由以下兩種方式達到··第一 種方式是则形成在電晶體周_應力薄膜，例如沈積在多晶 •石夕閘極上的應力膜(P〇ly stressor)或者在金屬石夕化物層形成後才 沈積的接觸洞蝕刻停止層(contact etch stop layer，CESL)，此方 式又被稱做「製程誘發應變(pr〇cess-induced strain)」；另一種方 式則疋直接利用應變石夕晶圓進行元件的製作。後者之應變石夕晶 圓的作法係在晶格常數較矽大的半導體基材上成長出應變矽 層。目前，大部分晶圓製造業者都是採用前者來進行元件效能 的改善與提昇’而且主要是利用具有伸張應力(tensile stress)的 一 氮化矽膜來改善1^1^08元件的效能。如熟習該項技藝者所知， 200814180 伸張應力可以提昇電子的移動力，相反的，壓縮應力 — (compressive stress)則可以提昇電洞的的移動力。 習知之 MOS (metal-oxide_semiconductor)裝置之製造，利用 建置間隙壁之技術以幫助控制及定義摻質植入]^1〇8之源極區 與汲極區。第1圖顯示習知之半導體屬〇8電晶體元件製程中 移除間隙壁的方法的截面示意圖。習知2NM〇s電晶體裝置通 φ 常包含一半導體基底。此半導體基底含有一矽層16,在矽層16 中形成有源極18以及與源極18藉由通道區域22互袓分隔的汲 極20。通常，半導體麵08電晶體元件另有淺接面源極延伸 π以及淺接面汲極延伸19，分別與源極區18與汲極區2〇鄰 界。在通域22上形成有—閘極介電層14，在_介電層 14上則形成有閘極12 ’其中閘極12 —般包含有複晶梦。閘極 介電層14隔離閘極12與通道區域刀。半導體丽⑽電晶體 元件10的源極18以及汲極20為植入石申、録或_ N+摻雜區 域。通道區域22則為植入硼的p型摻雜區域。在閘極12的侧 壁上形成有氮化石夕間隙壁32。在氮化石夕間隙壁Μ與閉極〇的 搬之_缝卵㈣3G，其通“二減賴構成。半導 體NMOS電晶體元件的裸露石夕表面，包括沒極/源極及間極， 則形成金屬石夕化物層42。目前，利用自動對準金屬石夕化物 (sdf-aligned silicide，salicide)製程來形成金屬石夕化物層；，舞 形成源極/汲麵之後，鍍或沈積方法，再形成一銘 ，（〇>)、鈦㈤、韻(N金屬騎紐馳/汲極區與閘極結構 7 200814180 上方’然後進行一快速高溫製程(rapid thermal process，RTP)使 金屬與閘極結構、源極/汲極區中的矽反應，形成金屬石夕化物來 降低源極/没極區的片電阻(sheet resistivity)。 於習知之M0S製造技術中，往往於製造LDD (lightly doped drain)區時使用間隙壁以達成源極/没極區與jldd區不同濃度之 摻雜。可藉由間隙壁之寬度與熱驅動循環而控制Ldd區。LDD φ 區與源極/汲極之植入深度可為彼此獨立而不相干。於65 nm或 更小尺寸之技術中，通道遷移率需要加強，此可進一步藉由在 移除間隙壁後於半導體基底表面沉積高度應變之介電層，使其 儘量靠近通道而達成。然而，移除間隙壁，尤其是氮化矽間隙 壁，是為關鍵，因為移除間隙壁之時，可能會損壞鄰近的結構， 例如：金屬矽化物層、閘極、及底下之矽基底。如第丨圖所示， 驾知之技術，係於完成金屬矽化物層後，直接以钕刻製程34 移除間隙壁。乾蝕刻之例，例如，使用混合有〇2與凡之四氟 _ 化峡對氮化石夕進行姓刻。濕钮刻之例，例如，使用之熱 磷酸(HsPO4)製程移除氮化矽間隙壁。但是，容易損壞金屬矽化 物層，尤其在間_切氮化物而金射化物層域砍化物 時，鎳石夕化物很容易在侧中受損，而影響晶圓允收測試⑼命 acceptance test)項目中之片電阻烛⑽_咖％)。 因此，仍需要一種較佳之移除間隙壁之方法及製造金氧半 产 導體(M〇S)電晶體元件之方法，以移除製程中形成的間隙壁而 200814180 不才貝告金屬秒化物層。 【發明内容】 本發明之目的是提供一種移除 氧半導體_s)電晶體元件 夂套種一 電晶體元件。於本發明之方c種金氧半導難叫 «近之例如自行鱗金屬魏物層2_壁時’不會損害其 右tl康本發明之移除間隙壁之方法，包括提供一基底，其且 ΐ二t’電極之至少—侧壁上具有，基底與電歡 = 積—保護層，使得保護層在_壁上的第-厚 於在物貝層上的第二厚度。接著，進行—第―韻刻製程 ^刀移除保護層’使得在_壁上的保護層大致上被移除殆 '，而在物質層上的保護層仍有殘餘厚度。最後，進行一第二 ==以移__，其中_騎於賴層而言具有侧 依據本發明之製造金氧半導體(M0S)電晶體元件之方法， 匕括於—半導縣底上形成—電極及於電極兩卿半導體基底 上形成-汲極/源極區域。接著，於電極之至少_側壁上形^ ’導體基底上進行一製程操作’製程操ς吏用間隙 土文為遮罩及於汲極/源極區域與電極之表面或頂部產生一物 200814180 質層。然後’於物質層及間隙壁上沉積一保護層，其中保護層 f間隙壁上的第—厚度係小於在物質層上的第二厚度。進行一 第蝕刻衣私，以部分移除保護層，使得在間隙壁上的保護層 被移除殆盡而在物f層上的保護層仍有殘餘厚度 灯第一钱刻製程以移除間隙壁，其中間隙壁對於保護層而言 具有钕刻選擇性。形成一接觸洞侧停止層覆蓋電極及沒極/ 源極區域。 依據本發明之金氧半導體(M0S)電晶體元件，包括一半導 體基底二電極位於半導體基底上、一沒極/源極區域位於電極 兩侧的半導縣底上、—物f層位於祕/祕區雖電▲之 =^部、-保護層赌_上、及—接觸_停止純 於电極及汲極/源極區域上。 /於本發明中’係於移除間隙壁之前，先於物質層(例如，自 :trb物層)及間隙壁上沉積一保齡 I、土的厚度小於在物質層上的厚度，如此，在進行钱刻製 程以部分移除保護層時，可使得保護層在間隙壁上的厚度大致 =為零，而在物質層上仍有殘餘。因此，在進行钱刻製程以移 除間隙壁時，因為物質層上受有殘餘之保護層保護，在選用對 =間隙壁具有較高之_選擇比的勤清，可輕易移除間隙 ^而不會損壞物質層，例如自對準金屬石夕化物層，此在製造 應變矽電晶體時，更是有利。 200814180 【實施方式】 明茶閱弟2至7圖，其顯不的是本發明之製造半導體m〇s 電晶體元件之一具體實施例的方法的截面示意圖，其中相同的 元件或部位仍沿用相同的符號來表示。需注意的是圖式僅以說 明為目的，並未依照原尺寸作圖。 本發明係關於一種製造積體電路中的NM0S、PM0S電晶 體元件或者CMOS元件的方法。如第2圖所示，準備一半導體 基底1其-般包含树層16。前述的半導體基底可以是石夕基底 或者是石夕覆絕緣(smcon*insulat〇r，s〇I)基底。於半導體基底 上形成-電極’例如—閘極12。於閘極12兩侧之石夕層W中步 :淺接面源極延伸17以及淺接面没極延伸19。淺接面源極延 伸π與淺接面汲極延伸19之間隔著一通道22。 、曾可在通道22上形成1極介電層14，以關閑極η 、。_12通常包含有複轉。閘極介電層14可由二 ::然而，在本發明之另一實施例中; 亦可由⑥介電常雜㈣胸所構成 = ，常成， —偏移嶋⑽―），編崎^ 200814180 示0 在形成氮化矽間隙壁32之後，可進一步進行一離子佈植製 程，將N型摻質物種，例如砷、銻或磷等植入矽層16中，或 將P型摻質物種，例如硼等植入矽層16中，藉此形成凡^^^ 或PMOS元件的源極區18以及汲極區2〇。在完成汲極源極的 摻雜後，半導體基底通常可以進行一回火(annealing)或活化 (activation)摻質的熱製程，此步驟亦為該行業者所熟知的，不 再加以陳述。 於閘極12、露出的源極區18、及露出的汲極區2〇上形成 一物質層，例如一金屬矽化物層(metal siHcide layer) 42。利用 自動對準金屬矽化物(self_aligned silicide，salidde)製程來形成 金屬石夕化物層；例如，在形成祕/錄區域之後，_賤鍵或 沈積方法，再形成一包括鎳之金屬層覆蓋於源極/汲極區域與閘 極結構上方’，然後進行一快速高溫製程(RTp)使金屬與閘極結 構、源極/汲極區域中的碎反應，形成鎳矽化物。RTp溫度可在 700。。至 l〇〇〇〇c 之間。 接著’如第3圖所示，於金屬石夕化物層42、間隙壁幻、及 閘極12的表面或頂部，形成一保護層44，使得保護層料在間 隙壁32上的厚度小於在金屬石夕化物層42上的厚度。例如，第 3圖中所示之Tl小於T2，較佳，Μ $ 〇·9。保護層的材料 12 200814180 可依間隙壁的材料而定，以便與間隙壁具有不同的钱刻速率。 =如’當間隙壁為魏化物時，可使用魏化物做為保護層; #間隙壁為石夕氧化物-石夕氮化物-石夕氧化物(ΟΝΟ)層時，可^石夕 亂化物料保制。形祕護層的方式，可使關如(但不限於) 電漿加強化學氣相沉積法(PECVD)、一種以狐氣體做為主要 反應氣體之SILPE Base製程、或高密度電漿氣相沉積法(騰 CVD)進仃㈣’彻沉積方法之不均勻階梯覆蓋性，或者進一 ⑩步搭配反錢體的魏、或純偏_ias)料，以麵所沉積 的保護層於間隙壁上的厚度較於半導體基板及閑極頂部之橫= 平面上的厚度薄。舉下述例子做為說明，但不受限於此例，使 用SILPE Base製程’於4〇〇〇c之溫度及7托耳之麈力下，以 seem之SiH4、noo sccm之、丨細〇 sccm之取氣體進 行麟約9·5秒之沉積，形成—ρΕ〇χ膜，其在間隙壁上的厚 度、力為7〇人’在半導體基板及閘極頂部之橫向平面(即，金 化物層42)上的厚度約為95人。 ;、、;後進行餘刻製程(未示出），例如等向或非等向之乾 ⑽或濕儀刻，以將部分厚度的保護層44移除。因為保護層 44在間隙壁32 _L的厚度小於在金屬石夕化物層42上的厚度，所 以進行餘刻時，位於間隙壁32上之保護層容易被移除殆盡(厚 度大致上為零）’而此時，在金屬石夕化物層42上仍有殘餘之保 羞層，如第4圖所示之保護層4如，以於後續移除間隙壁&時 - 做為保屬石夕化物層42的硬罩(hard mask)。例如，選用乾钱 13 200814180 刻方法時，以45度角進行，可有較快的 膜於咖增私祕及於金細_ ㈣㈣形，在部分雜保護層後 幻的保護層厚度可為约磁。 〜屬石夕化物層 接者，進行-綱製程46，以移關_ 32 Φ =:式進行，一，較佳為= 曰D’對於間隙壁具有較高之兹刻選擇比的配方。例 ,ΐ™ 為料物 於石夕氮化物具有高選擇比者；而當保護層 伴具有*選擇比者；或是再細調整配方。如此， 保遵層44a可對金射化物層42具有保護作用，當間隙壁^ 被移除時’降低對金屬雜物層42的損害。 如第5圖所示，移除間隙壁32後，僅在閘極侧壁上留下約 呈L型的襯塾層3〇及在金屬石夕化物層们上留下殘餘之保護 θ 44a。襯墊層不—定呈L型’亦可以進行—較溫和的飯刻製 程，略紐_墊層，以賴其厚度。在其它實關中，襯塾 層可被完全去除。襯㈣之厚度可為約略介於0至500A之間。 保護層44a可留在結構中，或可進—步被移除。 6圖 第6圖顯示保護層物未進—步去除的實施例。如第 14 200814180 所示，於移除間隙壁32之後，可依需要進行下一製程，例如， 應變石夕之製作或其解諸製程技狀進行。例如，可於半導 成一接觸洞崎止層48，例如一均勾沉積的氮化 石夕盖層’其厚度較佳在勘至2_之間。氮切蓋層與觀 電晶體讀的閘極12側壁上的襯藝層3〇直接接壤，亦與保護 層他結合在一起。使接觸洞姓刻停止層48於沈積時先設定沈 積在一 _應力狀_如，_αι咖至_3咖之間，對於PM 或-拉伸應力狀_如，W Gpa至3咖之間，對於議S)， ^此’使得通道_22在通翁向财對應之壓 =:善樹版遷料。__㈣48應力狀 〜 '可以_錯離子佈植或其他習知之方法進行。 7 7騎示，軸—層間介· 5Q覆蓋於觸洞兹刻停 曰上°然後’進行-侧製程，例如乾_，於層間介電 層50上形成一孔洞(未示_轴刻停止層48。再進行一 製程’例如濕侧，將孔洞裏的儀刻停止層48及殘餘之保護声 4域穿，露出金屬魏物層42，亦即，形成接觸孔&直務 錄/源極區域，以在後續製程中填入金屬形成插塞 性 連接之用。私庄 -弟7圖顯示殘餘之保護層44a未經移除而製造廳s電晶 體疋件之具體實關。第8 _顯示本發明之另—具體實 =曰 例’其中’殘餘之保護層細已在形成接觸洞侧停止層牝 15 200814180 之前以例如蝕刻而移除。 • 再者，在間隙壁移除後，或是將殘餘的保護層移除後，可 發現在電極結構侧壁上、殘餘的保護層上、或是物質層(例如金 屬矽化物層)上可能產生有機類的聚合物層，但其並不對元 製程有害。 ^ 馨 與習知之技術比較之，於本發明之方法中，移除間隙壁之 前，使用便利之方式，先於源極/汲極區域與閘極上的物質層(例 如自對準金屬矽化物層)及間隙壁上沉積一保護層，再部分移除 保護層，使得保護層在物質層上仍有殘餘，而在移除間隙壁時^ 物質層可受有保護層的保護，輕易的解決了習知技術中片電阻 不良的情形。再者，在間隙壁移除後，可將殘餘的保護層2去 或是留在結構中，與後續形成之接觸洞蝕刻停止層結合，例如 保護層為砍氮化物層，而接觸洞蝕刻停止層亦為矽氮化物層 _ 時’ 1不會林&影響。 9 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖顯示習知之MOS電晶體元件製程中移除間隙壁的方法 的截面示意圖。 16 200814180 第2圖至第7圖顯示依據本發明之製造M〇S電晶體元件的方 法的具體實施例的截面示意圖。 第8圖顯示依據本發明之方法之另〆具體實施例製得的M〇s 電晶體元件的截面示意圖。 【主要元件符號說明】200814180 IX. Description of invention: 擎 【Technical field of invention】 'Yuancaiguan-planting body, Weicheng, _ is the removal of the gap wall in the process of MOS-oxide semiconductor (MOS) transistor components. [Prior Art] As the semiconductor process enters the deep submicron era, such as the process of 65 nm (nm) _ or less, the drive current of the MOS transistor component (the improvement of the drive has become important. To improve the performance of the component) At present, the so-called "straineddlicon" technology has been developed in the industry. The principle is mainly to strain the Shixi lattice of the gate channel portion, so that the moving force of the charge passing through the closed-end passage of the strain increases. In order to achieve the purpose of faster operation of the *M〇s transistor. Basically, the strain of the germanium lattice can be achieved by the following two methods. The first way is to form a film around the transistor, such as deposition. The contact etch stop layer (CESL) deposited on the polycrystalline stellite gate or the contact etch stop layer (CESL) deposited after the formation of the ceramsite layer is called " Process-induced strain (pr〇cess-induced strain); another method is to directly use the strained stone wafer to fabricate the component. The latter strain is based on the lattice constant. A strained germanium layer is grown on a large semiconductor substrate. Currently, most wafer manufacturers use the former to improve and improve component performance' and mainly use a tantalum nitride film with tensile stress. To improve the performance of the 1^1^08 component. As is known to those skilled in the art, the tensile stress of 200814180 can increase the mobility of electrons. Conversely, compressive stress can increase the mobility of the hole. The fabrication of a conventional MOS (metal-oxide_semiconductor) device utilizes the technique of creating a spacer to help control and define the source and drain regions of the dopant implant. 1 shows the conventional semiconductor genus. A schematic cross-sectional view of a method for removing a spacer in a process of a 电8 transistor device. A conventional 2NM〇s transistor device φ often includes a semiconductor substrate. The semiconductor substrate includes a germanium layer 16 that is active in the germanium layer 16. a pole 18 and a drain 20 separated from the source 18 by a channel region 22. Typically, the semiconductor face 08 transistor element has a shallow junction source extension π and a shallow junction drain extension 19, Adjacent to the source region 18 and the drain region 2, respectively, a gate dielectric layer 14 is formed on the via region 22, and a gate 12 is formed on the dielectric layer 14, wherein the gate 12 is generally The polysilicon dream is included. The gate dielectric layer 14 isolates the gate 12 from the channel region. The source 18 and the drain 20 of the semiconductor (10) transistor component 10 are implanted, recorded or _N+ doped regions. The channel region 22 is a p-type doped region implanted with boron. A nitride spacer spacer 32 is formed on the sidewall of the gate 12. In the nitriding eve gap gap 闭 and the closed pole 搬 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Metallic stone layer 42. At present, a metal stellite layer is formed by a sdf-aligned silicide (salicide) process; after the source/kneading is formed, a plating or deposition method is performed, and then Form a Ming, (〇 >), titanium (five), rhyme (N metal riding New Zealand / bungee zone and gate structure 7 200814180 above 'and then carry out a rapid thermal process (RTP) to make metal and gate The ruthenium reaction in the structure and source/drain regions forms a metal-lithium compound to reduce the sheet resistivity of the source/drain region. In the conventional MOS manufacturing technology, LDD (lightly doped drain) is often used. The spacers are used to achieve doping of different concentrations of the source/nomogram and the jldd region. The Ldd region can be controlled by the width of the spacer and the thermal drive cycle. LDD φ region and source/drain Into depth can be independent of each other. At 65 n In the m or smaller size technique, the channel mobility needs to be enhanced, which can be further achieved by depositing a highly strained dielectric layer on the surface of the semiconductor substrate after removing the spacers, as close as possible to the channel. The spacers, especially the tantalum nitride spacers, are critical because when the spacers are removed, adjacent structures may be damaged, such as metal halide layers, gates, and underlying germanium substrates. As shown, the technique of driving knows that after the completion of the metal telluride layer, the spacers are directly removed by the engraving process 34. For example, dry etching is used, and a mixture of bismuth 2 and PTFE is added to the nitride. In the case of wet engraving, for example, the hot phosphoric acid (HsPO4) process is used to remove the tantalum nitride spacer. However, it is easy to damage the metal telluride layer, especially in the inter-cut nitride and gold-emitting layer. When the domain is cleaved, the nickel-lithium compound is easily damaged in the side, and affects the sheet resistance candle (10)_coffee% in the wafer acceptance test (9). Therefore, a better removal is still needed. Method of spacer A method of forming a gold oxide semi-conducting conductor (M〇S) transistor element to remove a spacer formed in the process, and 200814180 does not disclose a metal second layer. [Invention] The object of the present invention is to provide a removal. Oxygen semiconductor _s) transistor element 夂 a kind of transistor element. In the present invention, the type of MOS is difficult to call «near, for example, the self-scale scaly metal layer 2 _ wall will not damage its right tl The method of removing a spacer according to the present invention comprises providing a substrate having at least a sidewall of the second electrode, a substrate and a protective layer, such that the protective layer is on the wall - thicker than the second thickness on the shell layer. Next, the -first rhyme process is performed. The knife removes the protective layer so that the protective layer on the wall is substantially removed, and the protective layer on the material layer still has a residual thickness. Finally, a second == to shift __, wherein _ riding on the lamella layer has a method of manufacturing a metal oxide semiconductor (MOS) transistor component according to the present invention, which is formed on the bottom of the semi-conducting county - an electrode and a drain/source region formed on the electrode semiconductor substrate. Then, a process operation is performed on at least the sidewall of the electrode on the conductor substrate. The process is used as a mask and a material is generated on the surface or top of the drain/source region and the electrode. Floor. A protective layer is then deposited on the layer of material and the spacer, wherein the first thickness on the spacer of the protective layer f is less than the second thickness on the layer of matter. Performing an etching process to partially remove the protective layer, so that the protective layer on the spacer is removed and the protective layer on the layer of material f still has a residual thickness. a wall, wherein the spacer has an engraving selectivity for the protective layer. A contact hole side stop layer is formed to cover the electrode and the gate/source region. A metal oxide semiconductor (MOS) transistor device according to the present invention comprises a semiconductor substrate with two electrodes on a semiconductor substrate, a immersed/source region on the bottom of the semi-conducting county on both sides of the electrode, and a layer of material f located at the secret/ The secret zone is electrically ▲ = ^, - protective layer gambling _ upper, and - contact _ stop pure on the electrode and drain / source area. / In the present invention, before the removal of the spacer, a thickness of the shelf life I is deposited on the material layer (for example, from the trb layer) and the spacer, and the thickness of the soil is less than the thickness on the material layer. When the engraving process is performed to partially remove the protective layer, the thickness of the protective layer on the spacers can be made substantially = zero, and there is still residue on the material layer. Therefore, when the engraving process is performed to remove the spacers, since the material layer is protected by the residual protective layer, the gap can be easily removed by selecting the clearing ratio with a higher ratio of the spacers. It does not damage the material layer, such as the self-aligned metallurgical layer, which is more advantageous when manufacturing strained germanium crystals. 200814180 [Embodiment] A view of a method of manufacturing a semiconductor m〇s transistor component of the present invention is shown in the drawings of Figures 2 to 7, in which the same components or parts are still used in the same manner. The symbol to represent. It should be noted that the drawings are for illustrative purposes only and are not plotted in the original size. The present invention relates to a method of fabricating an NMOS, PMOS transistor or CMOS device in an integrated circuit. As shown in Fig. 2, a semiconductor substrate 1 is prepared which generally includes a tree layer 16. The aforementioned semiconductor substrate may be a stone substrate or a smcon*insulat〇r(s) substrate. An -electrode ', for example, a gate 12 is formed on the semiconductor substrate. In the step of the stone layer W on both sides of the gate 12: the shallow junction source extension 17 and the shallow junction no pole extension 19. The shallow junction source extension π is spaced from the shallow junction drain extension 19 by a channel 22. A 1-pole dielectric layer 14 may have been formed on the via 22 to turn off the idle pole η. _12 usually contains a reversal. The gate dielectric layer 14 can be two:: However, in another embodiment of the present invention; it can also be composed of 6 dielectric constant (four) chests =, often, - offset 嶋 (10) -), Kawasaki ^ 200814180 After forming the tantalum nitride spacer 32, an ion implantation process may be further performed to implant an N-type dopant species such as arsenic, antimony or phosphorus into the germanium layer 16, or a P-type dopant species, For example, boron or the like is implanted in the germanium layer 16, whereby the source region 18 and the drain region 2 of the PMOS device or the PMOS device are formed. After completion of the doping of the drain source, the semiconductor substrate can typically be subjected to an annealing or activation of the dopant thermal process, which is well known to those skilled in the art and will not be further described. A material layer, such as a metal siHcide layer 42, is formed on the gate 12, the exposed source region 18, and the exposed drain region 2A. Forming a metallization layer by a self-aligned silicide (salidde) process; for example, after forming a secret/recording region, a 贱 bond or a deposition method, and then forming a metal layer including nickel overlying the source The pole/drain region is above the gate structure, and then a fast high temperature process (RTp) is performed to react the metal with the gate structure and the source/drain region to form a nickel telluride. The RTp temperature can be at 700. . Between l〇〇〇〇c. Then, as shown in FIG. 3, a protective layer 44 is formed on the surface or top of the metallization layer 42, the gap wall, and the gate 12 such that the thickness of the protective layer on the spacer 32 is smaller than that in the metal. The thickness of the layer of stone on the 42. For example, T1 shown in Fig. 3 is smaller than T2, preferably Μ $ 〇·9. The material of the protective layer 12 200814180 can be determined according to the material of the spacer so as to have a different rate of money than the spacer. = such as 'When the gap is Wei, you can use Wei compound as a protective layer; #隔墙 is Shi Xi oxide - Shi Xi nitride - Shi Xi oxide (ΟΝΟ) layer, can be messed up Material protection. The shape of the secret layer can be such as (but not limited to) plasma enhanced chemical vapor deposition (PECVD), a SILPE Base process using fox gas as the main reaction gas, or high density plasma vapor deposition. Method (Teng CVD) into the 四 (4) 'Uneven step coverage of the deposition method, or a 10 step with the anti-money Wei, or pure _ias) material, the protective layer deposited on the surface of the gap The thickness is thinner than the thickness of the semiconductor substrate and the top of the idler = plane. The following examples are used for illustration, but are not limited to this example, using the SILPE Base process 'at a temperature of 4 〇〇〇c and a force of 7 Torr, to SiH4, noo sccm, and fine The sccm gas is deposited for about 9.5 seconds, forming a ρΕ〇χ film whose thickness on the spacer is 7 〇 in the transverse plane of the semiconductor substrate and the top of the gate (ie, the metallization The thickness on layer 42) is about 95 people. After that, a residual etching process (not shown), such as isotropic or non-isotropic drying (10) or wet etching, is performed to remove a portion of the thickness of the protective layer 44. Since the thickness of the protective layer 44 at the spacer 32_L is smaller than the thickness on the metallic layer 42, the protective layer on the spacer 32 is easily removed (the thickness is substantially zero). At this time, there is still a residual shy layer on the metal lithium layer 42, such as the protective layer 4 shown in Fig. 4, for the subsequent removal of the spacers & A hard mask of the layer 42. For example, when using the dry money 13 200814180 engraving method, it can be carried out at a 45 degree angle, and there may be a faster film in the coffee and a fine _ (four) (four) shape, and the thickness of the protective layer after the partial protective layer may be about magnetic. The genus is a lithograph, and the process 46 is carried out in the manner of shifting _ 32 Φ =:, and preferably 曰D' has a higher selectivity to the spacer. For example, ΐTM is a material with a high selectivity ratio for Shixia nitride; and when the protective layer has a *select ratio; or finely adjust the formula. Thus, the protective layer 44a can have a protective effect on the gold shot layer 42 and reduce the damage to the metal clutter layer 42 when the spacers are removed. As shown in Fig. 5, after the spacer 32 is removed, only the L-shaped lining layer 3 留下 is left on the gate sidewall and the residual protection θ 44a is left on the ruthenium layer. The liner layer is not - L-shaped can also be carried out - a milder engraving process, slightly _ pad layer, depending on its thickness. In other realities, the lining layer can be completely removed. The thickness of the liner (4) may be between approximately 0 and 500 A. The protective layer 44a may remain in the structure or may be removed in advance. Figure 6 Figure 6 shows an embodiment in which the protective layer has not been removed step by step. As shown in the 14th 200814180, after the spacer 32 is removed, the next process can be performed as needed, for example, the fabrication of the strained stone or its processing techniques. For example, a semi-conducting contact relief layer 48, such as a uniformly deposited nitride layer, may preferably have a thickness between 2 and _. The nitrogen capping layer is directly bordered by the lining layer 3 on the sidewall of the gate 12 of the crystal read, and is also bonded to the protective layer. The contact hole name engraving stop layer 48 is first set to deposit in a _stress state _, _αι咖 to _3 coffee, for PM or - tensile stress _ such as, W Gpa to 3 coffee, For the discussion of S), ^ this 'make the channel _22 in the Tongwen to the corresponding pressure =: Shanshu version of the material. __(4) 48 stress patterns ~ 'Can be _ wrong ion implantation or other conventional methods. 7 7 riding, shaft-to-layer intervening · 5Q covering the hole in the hole and then performing a 'side-side process, such as dry_, forming a hole in the interlayer dielectric layer 50 (not shown) 48. Perform a further process, such as the wet side, to pierce the inscription stop layer 48 and the residual protective sound 4 in the hole to expose the metal wafer layer 42, that is, form a contact hole & direct register/source The area is filled with metal in a subsequent process to form a plug-in connection. The private-sister-picture 7 shows that the residual protective layer 44a has not been removed to create a concrete reality of the chamber s. Show another embodiment of the present invention - where the residual protective layer fine has been removed by, for example, etching before forming the contact hole side stop layer 2008 15 200814180. • Again, after the spacer is removed, or After removing the residual protective layer, it may be found that an organic polymer layer may be formed on the sidewall of the electrode structure, on the residual protective layer, or on the material layer (for example, the metal telluride layer), but it is not correct. The meta process is harmful. ^ The method of the present invention is compared with the technique of the prior art. Before removing the spacers, a protective layer is deposited on the source/drain region and the material layer on the gate (for example, the self-aligned metal telluride layer) and the spacers in a convenient manner, and then partially removed and protected. The layer causes the protective layer to remain on the material layer, and the material layer can be protected by the protective layer when the spacer is removed, which easily solves the problem of poor sheet resistance in the prior art. After the wall is removed, the residual protective layer 2 may be left or left in the structure, and combined with the subsequently formed contact hole etch stop layer, for example, the protective layer is a nitride layer, and the contact hole etch stop layer is also a nitrogen nitride. The chemical layer _ '1 does not affect the forest & 9 The above is only a preferred embodiment of the present invention, and all changes and modifications made in accordance with the scope of the present invention should be within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a method of removing a spacer in a conventional MOS transistor device process. 16 200814180 FIGS. 2 to 7 show an M〇S transistor device fabricated in accordance with the present invention. Method A schematic section of an embodiment thereof. FIG. 8 show a schematic cross-sectional M〇s 〆 transistor device obtained in Example According to another particular embodiment of the method of the present invention. The main element REFERENCE NUMERALS
12 16 18 20 閘極 石夕層 源極 汲極 30 襯墊層 42 金屬矽化物層 44a 殘餘之保護層 48 接觸洞蝕刻停止層 52 接觸孔 14 閘極介電層 17 淺接面源極延伸 19 淺接面沒極延伸 22 通道區域 32間隙壁 44保護層 46程 5()層間介電層12 16 18 20 gate slab source drain drain 30 liner layer 42 metal sulphide layer 44a residual protective layer 48 contact hole etch stop layer 52 contact hole 14 gate dielectric layer 17 shallow junction source extension 19 Shallow junction, no pole extension, 22 channel region 32, spacer 44, protective layer 46, 5 () interlayer dielectric layer