TWI344182B - Metal-oxide-semiconductor transistor and method of forming the same - Google Patents

Description

1344182 IX. Description of the invention: [Technical field to which the invention belongs] This is a method for producing a metal oxide semiconductor (metal_〇xide_semic〇ncjuct〇r, MOS) tasa body, especially a strain having a strain-n) A method of fabricating a MOS transistor. [Prior Art] • Recording semiconductor transistors is an electronic component that is often used in integrated circuits. The material of the recording body is _ pole, source (so- and drain) The semiconductor component composed of a single electrode, the basin mainly uses the channel effect (Ch_el effect) formed by the MOS transistor at different gate voltages as a digital between the source and the pole. (dlgltaliZed)_Switch' is used in conjunction with other forests in a variety of logic and memory integrated circuit products. Please refer to the figure to figure 3, the reason is that the production of metal oxide semiconductor shy. As shown in Fig. 1, first, a semiconductor substrate 16 is provided. A dielectric layer 14 and a gate structure are formed on the + conductor substrate 16. Then, the semiconductor on both sides of the interpole 12 is collapsed - shallow junction _ 17 17 Take the money to the extreme extension (four) _ for the money semiconductor _ domain 22. [N turn fresh conductor transistor = channel area 17 and shallow junction bungee extension 19 # for example, the junction source extension is considered N-type dopants such as arsenic, antimony or phosphorus, j3441^2 species. After 'on the sidewall of the gate 12 A spacer layer (Hner) is formed on the surrounding sidewall of the spacer 32. A lithography process is performed on the surrounding sidewall, and an ion implantation process is performed to implant the dopant into the semiconductor substrate. The side of the semi-guided Zhao basement 16 is a two-in-one ^

It is 8 and a job domain 20, which constitutes a gold-oxygen semiconductor micro-electrode Zhao 34. For example, the I stone Φ type gold conductor transistor 'where the ion implantation process can be an N-type dopant species such as arsenic, antimony or phosphorus. As shown in Fig. 3, a stress-covering layer milk is formed on the semiconductor substrate, and the surface of the conductor transistor 34 is formed. The stressor layer 46 is covered by a nitride nitride and the silicon oxide semiconductor transistor 34 is stretched. In the female, the stress-covering process is activated, and the stress is memorized into the channel region 22 of the gold-oxygen semiconductor electric solar body 34 by an activation process. As is known to those skilled in the art, as the stress of the stress overburden is higher, the disk layer 46 should read the crystal of the semiconductor substrate 16 that can pull the channel region 22 to enhance the ion gain of the MOS transistor 34. When the stress value of the gold-oxygen semiconductor layer 46 is large to a certain extent, the structure of the stress cladding layer 46 = the conductor transistor 34 may be broken, so that the effect of the cladding layer 46 is greatly reduced, and even the gold is damaged. Oxygenation 1344182 SUMMARY OF THE INVENTION Accordingly, it is a primary object of the present invention to provide a method of gold oxide, wherein the stress covering layer exposes the body of the gate structure and the conductor transistor has better operational efficiency. & 吏 氧 半 根据 根据 根据 根据 根据 根据 根据 根据 according to one of the preferred embodiments of the invention. First, a gated sister is formed on the semi-conducting impurity. The semiconductor substrate has a connection between the semiconductor substrate and the vine structure, and the first strip has a connection with the second strip. After that, a stress-coated wire was formed on the bottom of the semi-conducting county to cover the structure. Thereafter, remove some of the nails, >. Connection between two strips ^ Exposing the first strip and the second embodiment According to another preferred embodiment of the present invention, the present invention further provides a transistor. Gold __纽彳—“峨, —^ semi-conductive region” and—covers the gate structure, the source region, and the =ΓΓ stress cladding layer. The pole structure has a first strip that is not parallel to each other. ', 帛 - strip-shaped part' has a connection between the first strip and the second strip, where the 'stress covering layer exposes the connection between the first strip and the second strip The above objectives, characteristics, and advantages of Ming are more obvious and easy to understand, 1344182

The «V - material x/fi implementation method" and the closed type are described in detail below. However, the following preferred embodiments and SJ are for reference and use only, and are not intended to limit the invention. [Embodiment] Referring to Figs. 4 8) to 1G, Wei is a schematic diagram of a method for fabricating a MOS transistor according to a first preferred embodiment of the present invention, and Fig. 4 is a diagram of Fig. 5: "The schematic diagram of the gold oxide body transistor extending along the section line AA, and the same elements or parts are indicated by the same symbols. It should be noted that the illustrations are for illustrative purposes only and are not plotted in the original size. In addition, the detailed lithography and the remnant process associated with the method of mounting the MOS transistor in the present invention in Figures 4 to (1) are not expressly known to those skilled in the art. In the picture. For example, a semiconductor substrate 16 is provided first, for example, a substrate dielectric layer (10), a substrate, etc., and a base dielectric layer is formed on the semiconductor substrate 116. 114 and one is closed. The gate dielectric layer 114 and the gate thereon (1) ion implant = 113. Then, using the opening 112 as a decorative mask, the semiconductor substrate 116 on both sides of the -= 112 is divided into a -f-plane source extension 117 and a secret-extreme (four) 9, the shunt junction 2 extends 1 Π and the shallow junction极极延仲 ^ 122 〇 ^ , 仃 仃 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 112 112 112 112 112 112 112 112 112 112 112 112 112 112 112 The sub-material layer is subjected to a non-specific etch process (anis〇tr〇pjC etCh) such that the material layer forms a liner layer 30 and a sidewall sub-132. As shown in Fig. 5, the gate 113 has a strip portion 15A, a strip portion 152 and a strip portion 154, wherein the strip portion 50 and the strip portion 152 are connected at an angle of about 9 degrees. A τ-shaped structure, and the strip portion 152 and the strip portion 154 are connected at a lost angle of about 9 G degrees to form an L-shaped structure.

The gate 112 usually includes a conductive phase material doped with a doped P. lysi Hcon, and the gate dielectric layer 114 may be a dioxide dioxide (excellent, eg, (10)) or gasified (· on Insulating material having a dielectric constant such as nitride). The pad layer HQ is located on the surrounding sidewall of the > 112, while the sidewall sub-132 is located on the profile layer (10). Wherein the lining layer 130 may be an offset sidewall, the material may comprise oxidized stone, etc., and the cross-section is usually L-shaped, and the material of the sidewall 132 may include a Nitrogen compound or a Wei-transfer Layer or composite_layer. In the present embodiment, the produced half (four) transistor can be called - N# P type gold oxide body electric hybrid, compared with the N type recording material electric type gold oxide semiconductor transistor, the invention can be # _ ' 11 , ^ The material N or the special N-type dopant species on the material substrate U6 - N _ sub-planting process. For the p-type metallographic transistor, the present invention can be used to perform a -P type ion implantation process. + Conductor substrate 116, another ion cloth, as shown in FIG. 6 after forming the side wall sub-132, followed by the 9 1344182 implantation process, using the closed-pole structure (1) as an implantation mask to implant the dopant into the semiconductor substrate 116, in the closed The material substrate 116 t on both sides of the pole 112 respectively forms a source area m and a drain region 12 〇. In addition, after completion of the doping of the source region ι8 and the drain region 120, the semiconductor substrate 116 is selectively subjected to an activation process, such as a rapid thermal annealing or annealing process, to activate the shallow junction source extension. (1), the shallow junction drain extension 119, the source region 118, and the pusher in the gate region 12〇, and simultaneously repair the lattice structure of the surface of the semiconductor substrate 116. It should be noted that due to the fact that the subsequent process orders may also include other high temperature activation processes, the activation process may not be performed here. Then, as shown in FIG. 7, a self-aligned metal telluride process is performed to sputter at least one metal layer (not shown) on the surface of the semiconductor substrate 116, such as a nickel metal layer, and overlying the gate 112. The source region 118, the drain region 12A, and the surface of the semiconductor substrate 116. A rapid thermal annealing process is then performed to react a portion of the metal layer with the gate Β 112, the source region 118, and the drain region 12 to form a metal telluride layer 142. Subsequent 'reuse of a selective wet characterization, such as a mixture of ammonia and cerium peroxide (Ammonia peroxide/Η20/Η20, ammonia hydrogen peroxide mixture 'APM) or a mixture of sulphuric acid and nitrogen peroxide (H2s〇4/H2〇2 , sulfliric acid-hydrogen peroxide mixture, SPM) or the like to remove a metal layer that is not reacted into a metal halide. As shown in Fig. 8, a stress coating layer 146 is formed on the semiconductor substrate 116 to cover the surface of the sidewall spacer 132 and the metal halide layer 142. In the preferred embodiment 10 1344182, the stress covering layer 146 can be subjected to a plasma-enhanced chemical vapor deposition (PECVD) process or a sub-atmospheric pressure chemicai vap〇r. Dep〇siti〇n, SACVD) process or high-density plasma chemical vapor deposition (HDpcVD) process and other deposition processes to form a thickness of about U) angstroms to 3 () 00 angstroms. The stress covering layer M6 may contain any material layer capable of generating stress, such as a nitriding compound layer or a rock oxide compound layer or the like. As shown in Fig. 9, a portion of the stress covering layer 146' is removed by a lithography and side process to form two stress relief openings (10). For example, a stress relief opening 162 exposes the junction of the strip 15Q and the strip 152, and another stress relief opening 162 exposes the junction of the strip 152 and the strip 54. Then, the stress coating layer 146 is subjected to an activation process, such as a UV Curing process, an annealing process, a thermal spi ce_eal process, or an electron beam (e_beam) process. Wait. The stress of the stress covering layer 146 is memorized into the MOS transistor 134 by the activation process, and the lattice arrangement of the semiconductor substrate of the channel region 122 is enlarged, thereby increasing the electron mobility of the channel region 122 and the MOS transistor. 134 drive current. It should be noted that the number, size and shape of the stress σ of the present invention need not be limited to the teachings of the first preferred embodiment, as long as the fold of the closed-pole structure (1) or the conventional strain-trained si can be exposed. „_) The manufacturing method of the MOS transistor is observed to be prone to cracks.

spirit. X 11 1344182 as in the third) _ show 'Next deposition on the conductor substrate (10) - dielectric please. The N electrical layer 148 can be an oxygen cut, an oxygen cut or a low dielectric constant material, and the like. After the ' _ stress covering layer 146 as a - touch stop layer (tank h stop .aye, CESL), 148 〇 _ privately ordered to the surface of the stress covering layer 146, the process parameters can be adjusted to cover the f A plurality of contact holes formed in the layer 146 and the dielectric layer 148 respectively reach the gate 112, the source region 118 and the drain region (10) of the gold-half-transistor 134.

Then, according to the general plug process, a conductive material such as copper, shovel, crane or alloy thereof is filled in the contact hole (10) to form a contact plug to the MOS transistor 134 (not shown). Medium), the preferred embodiment is completed. Another aspect is that the stress covering layer of the present invention can also be applied to a polygravity poly stressor. Please refer to FIG. 9 to FIG. 15 , and FIG. 15 to FIG. 15 are schematic diagrams showing a method for fabricating a money semiconductor transistor according to a second preferred embodiment of the present invention. FIG. 11 is a view of FIG. A schematic cross-sectional view of a MOS transistor extending along a section line B-B'. As shown in Fig. u, a semiconductor substrate is first provided, and then the steps shown in Fig. 4 and the steps shown in Fig. 6 form a MOS semiconductor transistor 234 on the bottom 116 of the semiconductor. As described above, the MOS transistor 234 may be an N-type MOS semiconductor body or a P-type MOS transistor, preferably an N-type MOS transistor, a MOS transistor 234. The utility model has a gate structure, and the gate structure comprises a gate 12 1J44182 -, a second electrical layer U4 and a gate 112 . Alternatively, the MOS transistor 234 may optionally include a sidewall sub-m and a liner layer (10) on the surrounding sidewalls of the gate structure. The channel region 122 of the MOS transistor 234 is located in the semiconductor substrate 116 below the gate junction 1 and the semiconductor substrate U6 on both sides of the channel region 122 includes a source region ι 8 and a drain region 12 〇. As shown in FIG. 11, the gate structure 113 has a strip portion 150, a strip portion 152 and a strip portion 154, wherein the strip portion 150 and the strip portion 152 are connected at an angle of about 9 (degrees) to form a The strip-shaped portion 152 is connected to the strip portion 154 at an angle of about 90 degrees to form an L-shaped structure. The deposition process shown in Fig. 13 can be formed on the surface of the semiconductor substrate 116 by a deposition process such as an electro-elastic chemical vapor deposition process, a human chemical vapor deposition process or a high-density chemical vapor deposition process. Stress overlay 146. The stressor layer 146 can comprise any layer of material that can create stress, such as a Nitrox chemistry layer or a sulphur oxide layer. As shown in Fig. 14, a portion of the stress covering layer 146 is removed by a lithography and side process to form two stress relief openings 162. A stress relief opening 162 exposes the junction of the strip 15 and the strip 152, while another stress relief D 162 exposes the junction of the strip 152 and the strip 154. Then, the stress coating layer 146 is subjected to an activation process, for example, an ultraviolet curing process, an annealing process, a high temperature peak annealing process, or an electron beam treatment. • The wire activation process arranges the lattice of the semiconductor substrate U6 of the channel region 122 of the stress-storing human MOS transistor of the stress coating layer (10), and further, the electron mobility of the phase region 122 and the metal oxide material « Crystal 234 drive 13 1344182 kinetic current.

As shown in Fig. 15, the stress blanket 146 is subsequently completely removed using an etching process. Thereafter, a self-aligned metal telluride process is performed on the surface of the semiconductor substrate ΐ6, which is entirely made of at least gold (not shown), covering the gate m' source region 118, the drain region 120, and the semiconductor substrate. 116 surface. A rapid thermal annealing process is then performed to react the metal layer with the gate 112, the portion of the source region 118 that is in contact with the drain region 120, into a metallurgical layer 42. Thereafter, the metal layer which has not been reacted into the metalloid compound is removed by SPM or APM or the like to complete the second preferred embodiment of the present invention. When the gate structure has a f-fold of 4, the stress covering layer covering the gate structure is easy to break the gate structure (4) and the gate structure at the bend is also susceptible to fracture. The fracture phenomenon of the noisy structure will not only seriously affect the metal oxide semi-conductor «crystal_operation, and even cause the MOS transistor to be completely ineffective. The main spirit of the present invention is to remove the stress covering layer around the gate structure (4) to avoid the occurrence of cracking. In view of the above, the gate structure of the present invention need not be limited to a T-shaped structure or an L-shaped structure. The ridges of the difficult structure may have an angle of any angle. In addition, the application range of the present invention does not require the N-type MOS transistor or the p-type MOS transistor shown in the foregoing embodiment, and the port has a convex structure of f-fold on the semiconductor substrate, and covers The stress-receiving layer on the raised structure exposes the f-fold of the raised structure, which can conform to the essence of the present invention. For example, the present invention can also be applied to a complementary metal-oxide semiconductor (CMOS) transistor or a lateral difflised metal-oxide semiconductor (LDMOS) transistor. A strain 矽 MOS transistor prepared by a growth process of a selective seiective area epitaxiai (SAE) or the like. Through repeated experiments and tests, it can be found that the present invention can effectively avoid the fracture phenomenon of the stress coating layer and the MOS transistor, and at the same time, can improve the electron mobility of the channel region and the driving current of the MOS transistor. The above is only the preferred embodiment of the present invention, and the equivalent changes and modifications made by the scope of the present invention are in the scope of the present invention. A brief description of the i-graph] ^ Figure to Figure 3 shows a conventional method for fabricating a MOS transistor. The m-sample is a gold-oxide semi-conductor =:= is the hair (4) ____ _ _ _ _ _ _ _ [Main component symbol description] Gate semiconductor substrate source region 14 17 Gate dielectric layer shallow junction source extension shallow junction drain extension 19 18 1344182 20 drain region 22 channel region 30 lining layer 32 sidewall spacer 34 MOS semiconductor transistor 46 stress capping layer 116 semiconductor substrate 112 gate 113 gate structure 114 gate dielectric layer 117 shallow junction source extension 118 source region 119 shallow junction 汲 · pole extension 120 > 122 channel region 130 pad layer 132 sidewall spacer 134 MOS transistor 234 MOS transistor 142 metal germanide layer 146 stress cap layer 148 dielectric layer 150 strip portion 152 strip portion 154 strip portion 160 contact hole

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Claims (1)

1^44182 X. Patent application scope: L A method for fabricating a MOS transistor, comprising: providing a semiconductor substrate; (4) forming a scale on a thousand substrates, and having a second strip of the pole structure 1 Between the second portion and the second strip - there is a joint 'and the first strip and the second strip are not parallel to each other And a = stress covering layer is formed on the semiconductor substrate to cover the joint between the strips of the stress covering layer of the interposing portion of the interposing structure. To expose the first-strip with the second = as in the patent application (four)! The ninth strip portion and the second strip portion of the MOS transistor are formed into a shape.丨, such as the scope of patent application! The method for producing the first strip-shaped portion and the strip-shaped portion of the article, as described in the "Patent Range No. 1", in which the metal oxide semiconductor electrode body is formed, After the structure, the method of the conductor electric Japanese and Japanese body, into a source (four) 舆 1 health domain ^ = ^ "in the resignation of the base shape is located on the two sides of the m. 4 face Shun Cheng polar region is divided into 5. 'One please A method for fabricating a MOS transistor is described in detail above. 344182, after forming the source region and the drain region, further comprising a surface of the gate and the source region and the gate region The step of forming a metal ruthenium compound is carried out - m 6. The method for fabricating the oxy-oxide body crystal according to claim 5, after the stress reduction of the removed portion, further includes a pair The stress coating layer is subjected to an activation process. 7 The method for fabricating a MOS transistor according to claim 6, wherein after the activation process, the method further comprises: forming a dielectric layer on the semiconductor substrate Electric layer; and the ride on the f layer and the occupational force Carrying out a butterfly process, so that the dielectric is occupied by 20% of the plurality of seals, and the scale bribery hole exposes the structure, the source i domain and the bungee region. An oxygen semiconductor electro-crystal method, wherein the cap layer is subjected to - activating the impurity during the removal of the portion of the stress coating layer. The material contains a stress-dependent coating. 9. The method described in claim 8 The method of removing the stress covering layer on the side of the shoe. The method of removing the stress covering layer on one side is 18 1344182 i. The gold oxide produced in the ninth application of the patent application is fully moved. In addition to the Gu (4) shape, the method of the body of the electric body, :: the source area and the surface of the _ domain formed - metal == step 11. As described in the scope of the patent application, the production of gold The method in which the stress (four) layer comprises a - _ _ _ 4, 12. a MOS transistor, comprising: a semiconductor substrate; - a gate structure 'on the semiconductor substrate, a nanopole structure and The first connecting portion Μ the strip portion and the second strip portion are not parallel to each other; a region located within the semiconductor substrate; a drain region located within the semiconductor substrate; a channel region, (4) within the semiconductor substrate under the drain structure, between the source region and the polar region; 1 should cover the interpole structure, or the upper portion and violently exit the joint between the first strip portion and the second strip portion. !3·If the application is specified in item 12 Gold __^_: a layer of metal material, located on the gate structure, the source region and the surface of the drain region. 19 1344182 14. The MOS transistor according to claim 12, The first strip and the second strip form a T-shaped structure. 15. The MOS transistor according to claim 12, wherein the first strip and the second strip form an L-shaped structure. 16. The MOS transistor of claim 12, wherein the stressor layer comprises a layer of a ruthenium compound. 17. The MOS transistor according to claim 12, wherein the gate structure comprises: a gate dielectric layer on the semiconductor substrate; a gate on the gate dielectric layer; And a sidewall is located on the sidewall of the gate. XI. Schema: 20