TW200814075A - Method of error correction coding for multiple-sector pages in flash memory devices - Google Patents

Abstract

A flash memory system, including a flash memory device and a controller, and having improved efficiency error correction coding (ECC), is disclosed. Each page in the flash memory device has the capacity to store multiple sectors' worth of data. However, partial page programming (i. e,. followed by a later write to fill the page) is prohibited for reliability reasons. A scratchpad block within the flash memory device is designed, and stores both user data and control data. ECC efficiency is improved by encoding the ECC, or parity, bits over the entire data block corresponding to the user and control data in the page. Retrieval of a particular sector of data requires reading and decoding of the entire page. Especially for codes such as Reed-Solomon and BCH codes, the larger data block including multiple sectors' data improves the error correction capability, and thus enables either fewer redundant memory cells in each page or improved error correction.

Description

200814075 IX. Description of the invention: [Technical field of invention] A month is in the field of non-volatile memory, and more clearly and anciently related to the error correction in the flash type non-volatile solid-state memory device... Prior Art] As is well known in the art, the second step is to smear your body, and the electric 1 erases the semiconductor hidden body, which can be erased and rewritten by relatively small blocks.

It is not as good as before to erase the programmable read-only memory device: based on the wafer range or larger block. In this way, the flash memory becomes non-volatile (i.e., the capital, temple after the power-off) in which the data is stored, and it is not necessary to re-write the application with a relatively low frequency. Examples of popular applications of memory include portable audio players, telephone numbers and telephone activities in mobile phones: "(4)" card storage: bit = electricity ~ and Weizhi station, thumb button &quot ; removable storage devices, storage devices for digital cameras, and the like. Don't use many commercially successful non-volatile memory products, especially

In addition, the use of one or more. Shipboard two A integrated circuit wafers to achieve - a small factor of the flash eeprom stone body array - 卞 form. A memory controller (usually in the same way as the memory array is a dry ~ knife away from the integrated circuit chip) interface control::, -=: ... and control card in the φ4 σσ version including a micro Virtual W^ lL L (Reading Bu-Volatile Random f °., some non-volatile read-only memory special circuits, for example, used in the (four)... 'seven special stylized and read data period = And reading into the memory and from the 4, between the work through the controller on the implementation of a wrong I20874.doc 200814075 correction code (ECC) one of the encoder and decoder. Modern and commercially available flash card COMPACTFLASH (CF) card, multimedia card (MMC), secure digital (SD) card, personal label (p•tag) and memory stick card. This can be used: the traditional host system of flash memory card includes personal computer, notebook type 2 personal digital assistants (PDAs), various f-communication devices, digital phase honeycombs, portable audio players, car sound systems and class-type devices. Removable flash memory cards in some systems Does not include one: the controller 'in this case, the host itself controls the internal memory of the card Examples of such a system include a smart media card and a (3) card. Depending on the type 2 memory card, the control of the memory array can be controlled by a software in the card or not for the software. The card of the controller function is realized by the software in the host. In addition, in addition to the memory card implementation, the wide-ranging type can be embedded in each type of host system instead. In the movable::: In the application of the two, the "host data is stored in the memory array according to the memory control soft". One of the important recent advancements in the volatile memory technology will be so 11 configuration. Cheng, TM "memory instead of "service" memory. As is known in the employee technology, the position of the flash memory system in parallel with the source line is green /, should be set to one memory unit. Access - move, ::: - The specific cell is driven by its word line (control idle). The inch keeps the other cells in the row off, so that the current between the bit line and the source line is one. ^ Take the status of early squatting to decide. The memory cell in the D memory is connected in series, between the bit line and the source line. Accessing the specific unit in the NAND line 120874.doc 200814075 Therefore, it is necessary to use the active word line level All cells in the row, and an intermediate word line level is applied to the cell to be accessed, so that the current between the bit line and the source line is also determined by the state of the access unit. It is known that each bit of NAND flash memory is much smaller than the area of each bit of dirty (four) memory, the main 22: NOR § recall, and the memory requires fewer conductors (and Therefore, the access transistor can be shared among a large number of cells in a NAND configuration. In addition, conventional NAND flash memory facilitates serial access, such as by successively accessing cells along the rows, rather than as random access memory in the case of memory. N A N D memory (4) is especially suitable for music and audio storage applications. Another important recent advancement in the field of flash memory is in the technology _ multi-bit quasi-programming unit (10). According to this scheme, only two programs on the memory unit are made possible by the "programming of the field technology". In the traditional binary data store, each memory unit is stylized into a -"〇·, or -τ state. This type of binary is made by applying a single control voltage to the address memory unit and making the idle pole so that it is programmed to -T, the transistor is turned on at the state, and remains at 0; through the addressed memory Unit sense: Ankou and restore the stylized state of the single. In contrast, according to the typical example of Ml /, for each memory unit, four possibilities are defined: 'Generally corresponding to binary values 00, οι, ίο, 11. In effect, the two values correspond to the two early 'partially programmed levels between the fully erased and fully stylized states. Some implementations of MLC flash memory with up to eight 120874.doc 200814075 states or three binary bits per cell are known. The ability to store two or three bits of data on each memory soap element is immediately added or tripled to a flash memory chip. An example of a MLC flash memory single μ including a memory of such a cardiac unit is described in U.S. Patent No. 5, η 2, 338, and U.S. Patent No. 6,747, 892 Β 2, both of which are commonly assigned and incorporated by reference. Incorporated herein.效率 The efficiency of combining MLC technology with NAND flash memory architecture has resulted in a significant reduction in cost per bit for semiconductor non-volatile library and improved system reliability, and a higher for a given form factor Data capacity and system functionality. Modern flash memory devices (especially those NAND architectures and such flash memory devices involving MW cells) are configured using, "block" and "pages". A block is a wipe unit and defines the |meta group that is erased simultaneously in a single erase operation. In general, f, a unit block is the most unit group that can be erased. A page refers to a stylized unit and is defined to simultaneously privateize or write to a group of cells in a single programming operation. Each block typically includes multiple pages. In general, arranging cells into pages and blocks is based on the phantom of cryptosystems. For example, in many Nand memory arrays, 'a page of memory cells are defined by such cells sharing the same word line' and a block is retained by the same "na>jd" For example, if a nAND chain includes 32 memory cells in series, a block will include 32 pages. Historically, the organization of data stored in a flash memory has always followed the combination of magnetic The file system used by the disk storage, so it is based on, section, and. 120874.doc 200814075 A section is generally a fixed size - the same time ... 枓 group, such as 512 byte system Some number of management bytes are in the middle. In many current files, the operating system of a computer or other host system configures the data into segments to write data to and from the non-volatile storage: In order to facilitate flash memory loading == non-volatile storage devices in such systems and applications, many modern (four) memories map logical "segment" addresses to flash memory in a similar way. The physical address within the volume array. The size and capacity of flash memory devices have been greatly increased, from the memory array of more than 1 million cells. In such arrays, the line can be extended to more than 2 memory cells. So many memory cells are placed on the same page or stylized unit. Therefore, in such large-scale flash memory, each page now includes multiple segments. Thus, the host system communicates the data units to the flash memory. The data unit is smaller than the smallest stylized unit in the device. Traditional flash memory has been writing a section into a page by processing "partial page stylization". To perform a partial page stylization, for example During the stylized-in-page process of four segments, the word line of the page receives a high private voltage, but only the memory cells that are being programmed on the word line within the segment (and of course, the memory cells in the sector that will receive a stylized data state) receive the enabled stylized source and the immersive voltage (via the bit line and other cells within the NANd chain) So, you can The segments are written separately into the same page. However, the device geometry continues to shrink so that in a flash memory 120874.doc -10- 200814075 two:: more memory capacity, the memory cells The reliability of the floating gates is more fragile, and it has been observed that the stylized electrode is driven onto the word line or the floating gate transistor < γ η β ^ Tend to two: a transistor that is not being programmed. For example, in a page with four segments and each segment being individually written, each cell will receive three additional stylized cycles over the body segment. And thus will receive four times the strain received from the only-single-stylized cycle. Thus, the =:: flash memory device will disable partial page stylization to keep it loaded. . Under this constraint, the flash memory device or memory control = flush data for individual segments until all segments within the page can be programmed in the same stylized operation. The use of more backgrounds, in a large number of data storage devices and storage systems, and in the Bellows communication system for error correction coding (ECC) is a basic error in this technology. Storage and communication of poor bits and shirts or extra bits ("commonly known as parity bits: code bits, sum check codes, etc.". For example, in the case of Ecc for lean storage, the actual data is used to encode a codeword that has more bits than the actual data. In order to retrieve the library material, the stored code is decoded according to the same code used to encode the codeword. Because the code points are too much to specify the actual data portion of the codeword, it can tolerate some number of error bits 7L, and there will be no actual data evidence loss after decoding. Many coding schemes for ECC are in this The technology is well known. : The substantial impact on the manufacturing yield and device reliability that can be provided by such coding schemes. These traditional error correction coding systems are especially useful in large-scale memory. 120874.doc 200814075 Useful / A flash memory is included to describe a device having a number of unprogrammable or damaged cells as available. Of course, there is a trade-off between yield retention and the cost of providing additional memory cells to store the code bits ( In this case, some ECC codes are more suitable for flash memory devices than others; in general, Ecc codes for flash memory devices tend to be larger than those used for beech applications. It may have a code rate as low as 1/2) with a higher code rate (ie, a lower ratio of coded bits to data bits). Examples of general-purpose flash memory storage devices that are familiar with ECC codes include Reed Solomon Code, other BCH code, Hamming code, and the like. In general, the error correction code used in conjunction with the flash memory is "system" because the data portion of the last codeword and the actual data in the code No change, code or same: The bit is attached to the data bits to form a complete codeword. Hunting from other backgrounds' Figure 1 illustrates the actual data in the multi-session page 8 of the conventional flash memory device ( "Effective bearer" data) and the configuration of the code bit. As shown in Figure!, page 8 includes four segments 1〇〇 to 1〇" each segment includes a data portion 11, an ECC bit portion, and ;;;# ss 7 Q ^ and Titanium 13. The data portion 11 generally occupies a majority of the units within a given section 10; for example, a typical section 10 of a 528 group includes 512 bytes As the data portion η and the other _bytes are used for the Ecc bit portion 12 and the header 13. Further, as in the old, the data portion u of each segment 10 in the page 8 can store different data. In page 8 of Fig. 1, the data section 2 of the section 1〇, 1〇1, 1〇2 is stored, and the user" Includes information generated by the application or user of the non-volatile recording system on page 8. Section 1〇3 of the poor portion "storage" control information, such control information is included in the exercise 120874.doc 200814075 Useful information in the non-volatile memory, such as the logic to 1, address mapping address table, erase count, status information, and the like ^ Control in the data portion i 1 of the segment 1 〇 3 The data may or may not belong to the user data in the data portion η of the segment ^ 〇 to 1 〇 3, and may or may not be in time. It is synchronized with the user data (that is, it may already be - the actual f is different from the use The time of the data is written). The header portion η for each segment stores (4) information for its segment, such control information including identification information for its associated segments, and status information about the data within its associated data portion. i. As described above, the control system reads data from the memory containing the page 8 and writes the data to the operating system thereof. The data is configured in a segment form, similar to (or equivalent to) storing the data as if it were stored in a disk drive. . Thus, if a large amount of data is written into the volatile memory, the data is concentrated in the sector (for example, 512 bytes) and provided to the memory controller or other device for influencing the writing of the data to the non-volatile memory. The logic of volatile memory. Page 8 for flash memory - controller or other logic uses the effective bearer (user or control) for a given segment to calculate the ECC for that segment Positioned. In the case of 5, the ecc bits for a sector depend only on the material used for the segment, and not on the content of the data in any other segment of the page. The number of ECC bits generated for a codeword of a given size depends on the particular stone horse in use', and of course depends on the length of the data block in the code. Once the data is written to the data portion n of a selected segment, the β, etc. is written to the ECC bit portion 12' for that segment, along with the appropriate header information to the header portion. . Moreover, once the data portion of the selected section of the 120874.doc 200814075 选定-read section reads the content of the section of the section of the section, the contents of the section 1 of the section of the section are read and used for detection (possibly Correction) An error in the data from the data section π. As mentioned above, the number of code bits generated by a conventional ECX code depends on the number of bits in the code: the body. Considering the ratio of the number of these additional code bits to the number of nurturing bits in the numerator, consider the "efficiency" of one code; this efficiency is another - the stomach-sense measurement system "the code rate" The ratio of the number of bits to the total bit (the code bit plus the data bit). With other backgrounds, conventional ECC codes (such as Chen De Solomon and BCH coding) tend to be more efficient in sizing horses. SUMMARY OF THE INVENTION "Therefore, the present invention is directed to providing an operation-implementation--a method of more efficient error correction of a flash memory device of a coding scheme. Another object of the present invention is to provide a minimum stylization The unit includes such a large-scale NAND flash memory in a plurality of data sections. The other object of the present invention is to provide (4) such large-scale NAND flash memory in which partial page programming is prohibited. Such methods. • With reference to the following description and the drawings, those skilled in the art will understand that other objects and advantages of the present invention are disclosed. The present invention can be implemented in an operation in which a page (or stylized unit) is configured to be stored. Method for flash memory device of multiple data segments. According to the present invention, the error correction code is applied by combining the data of the section # of the page into the unitary data block. The code is based on a data block containing information from all the data sections of the page from 120874.doc -14-200814075. Thus, the buffalo strip section can be of different types, for example The user data and the control data not included in the user data are included. In order to read a specific segment from a page, the entire page is read and decoded, and then the desired segment data is selected and output. The present invention will be described in conjunction with the preferred embodiments of the present invention.

A multi-level memory cell (MLC) stylized financial flash memory can be used in one. The invention is expected to be particularly advantageous in such applications. However, it is also contemplated that the present invention may provide benefits in other memory applications. For example, the present invention can be used in combination with various solid non-volatile (or even volatile) memories, including, for example, rewritable memory, erasable memory, and a memory of a known (QTP) s memory. Body type. Therefore, it should be understood that the description of the present invention is provided by way of example only and is not intended to limit the true scope of the invention. Referring now to Figure 2, the construction of a flash memory module 15 in accordance with a preferred embodiment of the present invention will now be described in detail. Figure 2 illustrates a consumption structure of a flash memory device (or module) constructed in accordance with the present invention. It is expected that the flash memory 胄5 will generally be constructed into a body circuit, and thus the W person pulls 4^ π Τ, which is connected to any of the memory controller or the memory controller logic, as follows: ♦ φ / Explain in detail. It is also contemplated that the architecture of the flash memory device 15 as shown in FIG. 2 is only for understanding the present invention and that the implementation of the flash memory device architecture shown in FIG. 2 is only 120874.doc. 200814075 Invention. The storage capacity of the flash memory device 15 resides in the flash memory array 。. As is known in the art, array 16 includes + programmable and erasable memory cells arranged in columns and rows. Although shown in FIG. 2 - a single column 16, it is of course contemplated that the array 16 can be implemented as a plurality of sub-arrays, each sub-column having a separate peripheral circuit instance, such as the one described below with respect to FIG. Part or all of the address, data or control circuitry. It is expected that the skilled artisan will readily be able to implement the present invention in conjunction with such multiple sub-array architectures after reference to this specification. In this example, the memory cell unit gate metal oxide semiconductor (10)S) crystal is configured such that each such transistor corresponds to a memory cell, which can be electrically programmed and can be electrically Erase. According to a preferred embodiment of the present invention, the array 16 is poorly imperfect, and the Bu Liza-_^ Pingyin 5 is a 5dfe body early 多 multi-level memory unit (MLC): because of its programmable Forming two or more data states (i.e., any one of two or more threshold voltages) is passed to cause each such early element to store a multi-bit digit value. And in accordance with the preferred embodiment of the present invention, From the following instructions

As will be understood, the memory cells are preferably configured in a NAND mode such that the memory cells are generally not randomly accessed but are serially accessed, such as for mass storage. application. Of course, the present invention can also be used in conjunction with a binary memory unit (i.e., storing only a single bit unit) in combination with a memory unit 2NOR configuration. According to this! In the preferred embodiment of the invention, the common input/output terminals 1/01 to I/0n are provided and connected to the input/output control circuit 20. As is known in the NAND type flash memory technology, (4) the memory device ^120874.doc -16- 200814075 operating system is mostly controlled by receiving and executing commands, which are passed through the wheel input/output terminal 1 /01 to 1/〇11 are conveyed as a digital block and executed by the technical logic 18. Thus, the input/output control circuit 20 receives the control command, the address value, and the input data via its driver and receiving circuit in communication with the input/output terminals 1/〇1 to I/〇n, and presents the current status information and Output the feed. It is expected that the number n of input/output terminals 1/01 to I/On will generally be 8 or 16, but of course any number of such terminals may be provided. Commands received via input/output control circuit 20 are forwarded to control logic 18 for decoding and execution to control the flash memory device. The production. By the wheel input/output control circuit 2〇 at the input/output terminal 1/〇1 to

The address value received by the ί/〇η is buffered in the address register π; the column portion of such an address is decoded by the column decoder 23, and the line portion is decoded by the line decoding jie 21 (each The decoder typically includes a one-bit address buffer to efficiently select a desired memory unit or a plurality of memory single lights within the array 16 in a conventional manner. The input/output control circuit 20 also performs bidirectional communication with the billet temporary storage H 19 via the bus DATA-Bus, transfers the data to the data register 丨9, and receives the output from the data register 19. Information, depending on the direction of data transmission to be performed. Control logic 18 also receives various direct control signals from external to flash memory device 15, such signals including (10) by way of example) wafer enable, command latch enable, address latch enable, write and read enable signals . As is known in the art, the command latch enable and address latch enable signals indicate whether a command or address is being provided on the input/output terminal/end 1/〇1 to _, while the write enable and read Enable signal ^ is not used as data strobe in write and 5 buy operations. I20874.doc 200814075 In accordance with a preferred embodiment of the present invention, memory array 16 is configured as a block; a block corresponds to a minimum group of cells that can be erased by an erase operation. Each block corresponding to this configuration includes a plurality of pages; the page corresponds to a minimum group of cells that can be stylized by a program or write operation. As described above, with respect to the memory d organization according to the preferred embodiment of the present invention, the memory cell page is defined by the same word line =: the cells are defined, so the block system is defined as Saved in phase (four) Na "

The pages within the chain. It is contemplated that, according to modern standards, the size of the memory array 16 in accordance with this preferred embodiment of the present invention is relatively large, resulting in data corresponding to a plurality of "segments" for each page. For example, each page of the memory bank is expected to correspond to at least four segments, each segment corresponding to the actual data of 512 bytes and managed at two bytes and at the level of the ECC data. In this example, it is also contemplated that the blocks will be included at 32 page levels such that the wealth chains within the memory array 16 include 32 or more memory cells. Of course, other segments, pages and block sizes can be alternatively implemented by the memory array 16 within the scope of the present invention. In the preferred embodiment of the present invention, the blocks of the memory array 16 are designated as "cache" block 24. The particular block within the memory array 16 as the scratch pad block 24 is arbitrary and may vary during operation of the flash memory module 15 in accordance with this embodiment of the present invention. In view of the fact that partial page stylization is disabled in the flash memory array 16 in accordance with this preferred embodiment of the present invention, as will be explained in more detail below, the gate speed memory block 24 is used as a write-to-memory memory. The array 16 - the temporary block of the H & bedding material of the final block - acts as a non-volatile buffer 120874.doc -18- 200814075. One embodiment of a flash memory device (or module) 15 within memory card 25. As shown in FIG. 3, the flash memory card 25 itself includes at least "2" 15 and also includes the controller 3G. Although FIG. 3 illustrates a single-fast memory device 15 having the above-described single-character array 16, it is contemplated that the flash memory card 25 can include one or more modules having a plurality of memory arrays 16. Multiple arrays of this type define multiple "planes,' as is known in the art. For the sake of clarity, this specification will be referenced to the -5 memory array 16 in a single flash memory module; however, it is expected that the present inventors can easily apply the present invention to the present invention with reference to the present specification. Multiple quick

The structure of the face. T controller 3 _ main Μ Μ W, HOST TF main branch, first supply and manage an external interface ~, such as a personal computer or laptop, - high-performance digital camera, - car sound system, or One ~ text this number of bribes to say that J '-type devices, such as a digital sound y, literary, personal digital assistant (PDA), bee information through the ten-day; hand-held electric clean mobile phone or different memory card 25 two And similar. The interface job T-if can also correspond to flashing into various hosts ^ external terminal' (four) memory card 25 is constructed as a plug-in == one of the universal flash memory cards, such a technology knows one,隹 了 了 了 了 此项 此项 此项 此项 此项 此项 此项 此项 此项 此项 此项 此项 此项 此项 此项 此项 此项 此项 此项 此项 此项 此项 此项 此项 此项 此项 此项 此项 此项 此项.... 'Panel ticket quasi-included one's branch: Medium:: Know 'some types of flash memory cards or devices do not work (such as controlling cry 3 0), j * at main) in this case the host system ( Example I20874.doc -19- 200814075,) The operation of the memory array is controlled by the control software executing the host system. Examples of such memory systems include smart media cards and (7) cards. Although the example of Figure 3 is directed to a flash memory card that includes a controller 3, the present invention is also contemplated for use with such a controllerless flash memory card. As shown in the example of FIG. 3, flash memory device 15 is coupled to controller 30 in a manner consistent with the terminal shown in FIG. In this regard, an input/output bus system is formed by signal lines and (5) hearts that are connected to the terminals of the flash memory device 15 of the same name... control bus CTRL couples the controller 30 to flash The memory device i includes wires for the control signals described above with respect to FIG. As is known to those skilled in the art, the controller 3 is expected to be constructed substantially in accordance with the conventional fast = memory control H architecture, modified as necessary to affect the operations described in this specification. More specifically, Figure 4 illustrates the functional architecture of control (4) in accordance with a preferred embodiment of the present invention. In this regard, it is also contemplated by those skilled in the art that, after reference to this specification, it is understood that within the controller 30, the logical hardware, program instructions, or ports of the operating mode functions are used with =:%. From the perspective of the hardware, as described above, it is expected that the conventional control = 1130' is preferably implemented by means of a programmable processor that executes a sequence of deductions stored in the program memory. As such, it is further contemplated that readers of the art should be able to easily make such modifications to the specific state, as appropriate, without undue experimentation. • The control unit 3 0 includes a system shown as one of the host interface circuits 32, the system, which controls the communication and communication to and from the host system through the interface HOST_IF, and controls the system to and from the back end. 34. Signals and Resources 120874.doc -20 - 200814075 The 'backend' system 34 communicates with the flash memory module 15 (Fig. 3). The backend system 34 includes control to and from the memory module 15. Data section: data flow and sequencing function for sorting and transmission' and also includes media management function, which is the block and page structure of the flash memory redundancy module 15 and the logical data storage in the page structure. The functions include command sequencer %, low level ordering benefit 38, and flash control layer 42, and the media management functions include address transfer force 35, table controller 37, and erase block manager. The command sequencer 36 combines the address translation function Qiu Zuo to map according to the logical sector address: the physical address (translated by the address translation function 35), and the host and the fast =. Inter-configuration and sequencing data transmission. Low-order quasi-sequencer function: combined dimension For the control table information of the flash memory module 15, the management is 3 7 to generate a lower level control sequence for communicating with the flash memory module 15. The JA class table includes a free block table, Indexes and tables of such obsolete or updated states in the flash memory array = in-and-out blocks, and the like, etc. The erase block manager function 39 maintains the erase blocks, including maintaining , erase count and average read and write of flash memory module 15 ... coffee, n = flash control layer 42 derivation and translation of the appropriate signal sequence for use with the flash memory phantom, and 5 pass L, and through the input / Output lines 1/〇1 to "on and; no! Industrial bus CTRL, i and device interface 44 that drives and receives these control and input/output signals from the % memory module b. In a preferred embodiment of the present invention, the controller 3() rear end system 34 includes an error correction coding (ECC) engine 4, a # combination low level sequencer, or the data stream of the 34 尔 system 34 and Known for other functions within the sequencing function, U performs the appropriate encoding and decoding of the code bits for storage in Flash 12087 4.doc 200814075 fe body module 1 5 and from the # ^ ° member. The specific ecc code used by the ECC engine 40 can be any of the known error correction codes known in the technology φ, and A good one has a & m suitable for combining the code rate code used by the flash memory storage (ie - fully robust correction - a reasonable number of errors, without having to remember (four) column 16 too much The number of additional storage units is coded. The crimes of the Optima code include the Hirsch Reid Η Η code, and other BCH codes; in the case of the case - the preferred system is systemically. In detail, the next month, in accordance with a preferred embodiment of the present invention, the Ecc engine 40 encodes and decodes the methods employed by the group, i.e., segments. However, for the purpose of this book, the first use of the scratch pad block 24 of FIG. 2 illustrates an example of the operation of writing data to the flash memory array 16. I, as described in the 'Requires the flash memory device 写入 data write prohibition page °P page stylized' to reduce the occurrence of the same page caused by the use of separate stylized loops for each segment of the page The strain on the memory cells within the page 16 caused by the repeating unit stylization. However, as described above, the physical page boundary is such that the host system manages the data on a sector-by-segment basis, and the host system communicates the data by the segment to and from the controller % without closing the page boundary. Referring now to Figures 5 & 5f, the operation of controller 30 and flash memory module 15 in a processing sector write operation will be described in greater detail in accordance with a preferred embodiment of the present invention. Figure 5 a to 5 d „Children use the controller % of the horse speed temporary storage block 24 and the operation of the flash memory device 15. As shown in Figure 2, the high-speed temporary storage area (four) refers to the flash memory array An arbitrary location block within 16 that varies during operation of the flash memory device 15. For example, when used as a high speed temporary 20874.4 -22. 200814075 memory block 24, the block becomes full (ie, When the last page is written, the contents of the block are written to a new block that is then used as the scratch pad block 24, and the obsolete sector is discarded (ie, written to another "update" area a block or such a segment that has been replaced, so that additional space is present in the new scratch pad block. The block previously used as the scratch pad block 24 is erased and available for use. An example of the construction and operation of the high-speed temporary storage block used in the present invention is provided in the pending date of December 16, 2004, and entitled "High-speed temporary storage block", and the commonly assigned US patent application serial number. 1 1/01 6,285 and declared on July 27, 2005; ^ titled "There is a multi-stream update tracking Vol. 1 / 192, 220, Vol. No. 11/192,220, both of which are incorporated herein by reference. In Fig. 5a, a portion of one of the items of the scratch pad block 24 is shown. As described above, in the memory array 16 The inner block is configured as a page, and the page system is configured as a segment. The individual pages SBpi, SBp2, SBp3, SBP4, etc. of the high speed temporary storage block 24 each include a plurality of segment positions si, s3, in this example. S4. Of course, as mentioned above, the number of segments that can be stored in a page and the number of pages in a region Φ ghost depends on the particular architecture. For example, typical modern NAND flash memory arrays are organized as much as possible. Included are physical pages within a given block. Figure 5a also illustrates another block 16a of the memory array 16, which in this example will be used as a normal, update, block, term, Update, block • refers to a block within the memory array 16 that is used to store the data provided by the host system within the flash memory location 15. The particular selection of the update block 16a And configuration will depend on the particular group k used for flash memory and the official solution Therefore, the update block 丨6a can be used as a continuous update block (ie, continuous in the memory array 16) or as a "chaotic" update block (ie, 120874.doc -23 - 200814075 in the memory array 16 Select continuously) to select and manage. In either case, the update block 6a includes a plurality of pages, and four such blocks UBP1 to UBP4 are shown in Fig. 5a, and each block UBPj includes four sector positions §1 to S4. Of course, considering that any block (including update block 16a) can be designated itself as a scratch pad block 24 in time, update block 16a will typically include the same number of pages (and segments per page) as a high speed. Temporary block 24. Figure 5a illustrates the contents of the controller 3, the high speed buffer block 24 and the update block 16a in response to receiving a sector to be written. In this example, the data for a single segment #5 (such data includes its corresponding header information) is received by the controller 30 from the host. For clarity, the description of this operation of the preferred embodiment of the present invention will include both actual and valid bearer data, as well as any header information (e.g., as shown in Figure 1). As described above, the partial page stylization is prohibited in the flash memory device 15. However, the data received from the host in this first operation is for only one segment and is used to not align the data for one of the beginnings of a page. In contrast, in the fe example in which four sections are provided per page, the sections #〇, #4, #8, #12 are aligned page boundaries. Therefore, the controller 30 stores the content for the section #5 in the page SBP1 of the scratch pad block 24, and copies the written data with one of the current contents of the section #4 (as shown in FIG. 5a). The data is populated together. The result of this operation is that page SBP1 contains the data for sections #4 and #5, and since local page staging is disabled, this page SBP1 will not be written until the high speed is erased. After the block 24, the update block 16a remains vacant at this time. According to a preferred embodiment of the present invention, as will be explained in more detail below, the page SBP1 is written and read relative to conventional flash memory. Take the instruction of 120874.doc -24- 200814075 to provide improved error correction capability to write the internal sections of storage sections #4 and #5 together with their official and error correction code bits. This will be explained in detail in conjunction with Figure 6a. The actual storage data and management data configuration. Figure 5b shows that the controller 3 receives the next segment #6 ' from the host system (the content is written to the flash memory device 15 I, the scratch pad block) 24 and the content of the contiguous block 16a. As described above, for the section #6 Data. Does not fill a page and does not align a page boundary. If partial page programming is allowed, the controller 30 may have only written the data for the section #6 to the opposite area of the page SBP1. Within segment S3 (or more likely, only segment #6 is written directly into the appropriate physical segment of flash memory device 16 without the use of a cache pad 24). However, in accordance with this aspect of the invention For example, as shown in FIG. 5b, the control state 30 writes the sector #6 to the sector position of the new page sBp2. The S3 page is filled with the area previously written and retained in the page SBP1 of the scratch pad block 24. The contents of segment #4, #5. The update block heart has not been written yet. Φ , , According to this example, the control descent 30 then receives the data for the two segments #7 and #8. 7 of the poor material will of course be completed and also contains the section material, #5 and #6 兀t data page, the data for section #8 constitutes the first shell section for another page. In this scheme For one of the sections #4, #5, #6, and #7 • The full data page is thus written to the page of the update block "a" UBP1 (as part of the previous copy 4 for section #4 It The data is populated to the new data for the above sections #5, #6, #7. The controller 3 marks the contents of the pages SBP1, SBP2 of the scratch pad block as obsolete because the contents are now Stored in the update block. This tag may be, for example, manipulated by the table manager 120874.doc -25- 200814075 to 37 to write the corresponding control bar to a table or in the controller or in the flash The influence of other data structures stored in 15. The section #8 corresponding to a part of a different page is written to the page of the high speed temporary storage block. Because the pure segment is aligned - the page boundary and because it is not until the receipt of the data for at least one subsequent segment, it is written to update the block! 6 a, so no padding is required. Figure 5d shows the controller 3 receiving data for three sectors from the host system, i.e., for the areas U1(), #11, and #12. Because it is used for sections (4) and #11

The material system resides in the same page as the data for the segment #8, and since the segment #U is in the last region within the boundary of the -page, the controller 30 writes a complete page of data. The page side of the update block 16a includes information for the sections #8' #9' #10, #11. The padding is provided by a copy of the previous content of section #9 (such as the section material 9 shown in Figure 5d) to fill the page UBP2. In the scratch pad block 24, the contents of the segment 8 are already obsolete' and the third receiving segment #12 is written to the next page SBP4 of the cache memory segment 24 shown. In accordance with a preferred embodiment of the present invention, the controller 3G operates to use the available segment space within the scratch pad block 24 to store user data (i.e., execute an application generated data on the host) and Control within a single page or support for both. In accordance with the present invention, an example of such control or support material (referred to as control in the month θ) includes indexing for the cache block 24 itself. For example, such cached block index information includes The logical block address for the contents of the high speed temporary storage block 24, and the number of valid sectors currently stored in the high speed temporary storage block 24. m 120874.doc -26- 200814075 The first effective segment in the body 2 The segment shift index, an indicator to the next page of the high speed temporary storage block 24 that can receive new data, and the like. Other examples of the control data include the logical and physical block bits used in the flash memory device 15. Information, indexes, indicators and displacements of address tables and other data structures, tables and other information about the average read and write operations for blocks used in flash memory array 16 (eg, for each block of such blocks) Wipe the count, at least • and at most frequently erase the block table, etc.), and other control and support information for the operation and management of the flash memory device, and as described in detail below, this control is poor. Also includes an update block indicator a value that points to a physical page within the update block 16a that is to receive a page of the primary data to be written; in accordance with a preferred embodiment of the present description, the updated block indicator is used to manage the sector lean The most recent version, for example, the non-volatile memory and method, which is filed on July 27, 2005 and entitled "Multi-stream update tracking" and is incorporated herein by reference. /192,22〇. In general, and with explicit reference to the cached block index information, the control material may include information about the synchronization of user data content of other segments currently active and intended to be stored in the scratch pad block 24, And is not synchronized or otherwise independent of such user data and does not require simultaneous or consecutively written information with the user profile. • Referring to Figure 5e', after writing the contents of section 12 to page SBP4 (Fig. 5d), controller 30 also receives new material for section 14 from the host system. In accordance with this embodiment of the invention, the controller 3 determines that an additional segment (segment position S4) can be used within a page SBp4 even after writing the latest received segment #12 content. The previous received content for segment 12 is written 120874.doc -27- 200814075 to a new page SBP5 in the scratch pad block 24 within the segment location S1 of page SBP5 and will be used for the latest section 14 The received data is written to the sector position illusion; the sector position S2 is filled with the previously stored contents of the section "section 13", and the sector position S4 of page SBp5 receives the control data CTRL to fill the page. In this example, the control data CTRL includes an update block indicator having a value indicative of the position value of the page UBP3 for updating the block l6a, this page • updating the next erase page within the block 16&. Although the page SBP5 is displayed as filled (ie, all four segment positions s 1 to S4 contain stored data), it is not necessary to fill the control data c τ RL in one page of the scratch pad block 24 One page, for example, referring again to Figure 5a, control information CTRL may have been written to the segment position S3 of page SBP1 as needed. In accordance with this embodiment of the present invention, as described above, the inclusion of control information CTRL in the intra-memory block 24 is performed in a manner that provides improved error correction and correction capabilities relative to conventional ECC techniques. A preferred embodiment of the present invention will now be described with respect to FIG. 6a as being disposed within the page § Βρ5 of the cache block 24 in the state shown in FIG. 5e. Figure 6aD shows the user data for section #12 stored in a location 41 and the location of the sector 43 '4' for the location of the zone (4) 2 data. Similarly, the sector position S2 stores the user profile for section #13 (i.e., section material 13) and its header, while the section location S3 stores the user profile for section #14 and its header. The section s4 of the page gift 5 stores the control data CTRL and its header information. However, there is no segment location W to S4 for error correction coding for its individual user data (10) 120 120874.doc -28- 200814075 凡. Instead, portion 42 of page SBP5 of scratch pad block 24 stores the ECC bits, which have been calculated or derived for all segments within the page. In accordance with a preferred embodiment of the present invention, the ECC bits stored in portion 42 of page SBP5 are not one of the Ecc bits calculated for the individual segment user (and control data portion). . Instead, the ECC bits stored in the portion "are encoded as part of the user (and control) data portion of all segment positions si to S4. In other words, referring to the example of FIG. 6a, The Ecc bits in section 42 are encoded from a larger data block containing one of the user data and control data CTRL for segments 12, 13A, 14. In fact, the ECCs of portion 42 The bits need not be stored continuously in page SBP5, but may be distributed throughout the page as needed. In accordance with the present invention, however, the ECC bits stored in the page are based on a larger multi-segment data block that is considered a unit. To encode, it has been found that encoding multiple sectors of data in a single data block requires less Ecc bits than is required to correct the level of the same level error in the case of individual segments. To correct a given number of Ik machine distribution errors on a multi-session page. This feature of the preferred embodiment of the present invention can be illustrated by way of example. For the sake of clarity, the examples will reference a power. - Into (for example 5 12 bytes) size Section; in fact, the above-mentioned area will have a bedding portion of one size of one or two powers (for example, 5 12 bytes), with an extra byte (for example, 6 bytes) for a standard According to the well-known BCH code, for any integer, there is a binary BCH code having a block length, which includes the effective carrying data of the ^^ bits, and thus includes the n_k parity check (ECC) bits, of which 120874. Doc -29- 200814075 Plus. The minimum encoding of such codes "distance u dme2t+i; this code can detect up to dmin errors in n digits and correct up to t errors. The actual data of the byte size of the byte (4096 bits), the convenient example of the horse can be configured with m = 1 3 and t = 4. This code requires at least 13 = ΡΡη / Λ - bit 7L. Use this type of BCHU| In conventional applications of sector-wise ECC coding, additional ECC bits are often provided; for example, a common implementation defines the number of ECC bits as n_k=m(t+i)+i, or one-to-one; 1 3 and t 4 of the 4th 96-bit % of the politically-bearing data - 匕 曰 对应 对应 对应 对应 4096 4096 4096 4096 4096 4096 及其 及其In the codeword of the element (e.g., the 66 bits), as many as 4 error bits. '', and in accordance with a preferred embodiment of the present invention, the data of the plurality of segments is encoded into a single data. Blocks, regardless of the data class 1 contained in each section and not ringing 5 hai, etc., are accessed by the controller individually. The number of random errors to be corrected t may vary with the size of the data block. This increase is still awkward, because the stylized operation applied to the flash memory is a one-page method as described above. The number of random correctable errors per page (ie, each stylized operation) is determined. Successful completion of the stylized operation ^ In addition, non-random (ie, cluster) errors that exceed the limit number t can be corrected and cannot be corrected segment by section 'and cannot be corrected page by page (ie for (4), in either case in a segment The five errors within will not be corrected). As such, the present invention keeps the number of randomly distributed bit errors on the page constant. For an example of a four-segment page data, each segment has a size of 4096 bits (512 bytes), and the length of the block to be coded is n=i6384 bits. This point requires the parameter m to be at least l5 (n=2m.1)e as described above, even if the number of errors can be corrected for this model 120874.doc • 30· 200814075 t can keep the data block size four times in the example by nk= The minimum number of ECC bits defined by mt provides additional ECC bits as described above, for example, for t=4 and m=15, % t=4 will be provided, whereby in this case, the target is 60 bits. Preferably, n-k=m(t+l)+l; in this case

ECC bits. In either case, the memory unit is substantially less than the traditional scheme requires storage of ECC bits. In the conventional scheme, four sets of 66 ECC bits (one per sector) are required, which are totaled on the page. Bits without correcting random error corrections. Alternatively, the number of correctable errors t can be increased in accordance with the present invention by increasing the data block size _ ECC bit number n-k. In other words, for a number of ECC bits per page compared to a traditional segment-by-segment configuration (eg, 264=4χ66 ecc bits for a four-segment page), but by encoding the multi-session page into a single data block The number of correctable bits on the page can be substantially increased (for example, in this example to t=19). As mentioned above, the Reed Solomon code system is also commonly used for a subset of the code for error correction. According to Reed Solomon coding, the ECC bits are configured as octave symbols, and each symbol has a size of one m-bit, wherein the block length is a symbol. The number of ECC or parity check symbols n_k is defined as ^ k - 2t 1 is the number of errors that can be corrected, and the minimum coded distance min 1 is for the example port of four 5 12-bit segments in the consistent body page and m 9 For one of t==4 useful Reed Solomon code will need eight ECC symbols per segment, each ECC symbol m = 9 bits; according to the transmission, "filling area ^ and the way error correction scheme, this point Resulting in a total number of ECC bits per segment 'so a total of 288 bits for a four segment page. 120874.doc 31 200814075 And according to the invention 'increasing the size of the code word to include all segments in the page can be greatly Decrease the number of ECC symbols (and bits) to obtain the same random error = positive performance. For example, from the four 512-bit field _ P MM bits in the page - the code block of the group needs one m =ll Chende Solomon codeword 1 can correct the number of errors t (4) but then generate a person's coffee symbol on the whole page, each called a bit (a total of two ECC bits) Traditional way to apply error corrections one by one

The 28 ECC bits needed are much smaller. Similarly, the present invention can provide a higher error correction level (e.g., t > 4) e by using the same number of numbers required to compare the number of segments per section ^ or less. - Reed Solomon codeword implemented using the Norecc bit' can correct the number of errors t can be as high as t 1 3. It is contemplated that the skilled artisan can readily optimize the error correction level using the required number of gems or symbols for the particular embodiment of the present invention with reference to this specification. In the example of the above, relative to the figure, the page SBP5 in the cache pad 24 is written with user and control data, its individual headers, and the corresponding Ecc bits. . Once the host system provides the user profile for zone #15 to controller 30, a complete user profile page becomes available (i.e., for users of zones #12, #13, #14, and #15) data). Control 30 then writes a full page to the update block 丨6a, specifically to the update block page UBP3 as shown in FIG. 5f, such as the update area stored in the control data CTRL in the scratch pad block 24. The current value of the block indicator is indicated by 0 120874.doc -32- 200814075 In accordance with this particular embodiment of the invention, the write update block is executed on all segments of the single-data block for encoding purposes... The errors applied in the process correct the coding, rather than the four-part system based on the segments. Figure 6b illustrates the configuration of page UBP3 in update block 16a in accordance with this embodiment of the present invention. As in the efficient temporary page 5 of the figure, each of the segment positions 81 to 84 includes a user data portion 51 and a header portion 53. However, the update block page UBp3 also includes a single ecc bit portion 52 that stores the ECC bits encoded on all segments in the page, and the user profile for the segments is deemed to be used for A single data area & for encoding purposes. The content of the header portion 53 for each segment is encoded in this <column, but this additional information can also be used as if the data bit " is included in the error correction encoding. As described above with respect to this scheme applied to the scratch pad block 24, this preferred embodiment of the present invention provides a higher degree of error correction capability for the same number of memory cells per page in the memory array 16. Or, conversely, the number of memory cells required for ECC bits for a given error correction level can be reduced. This error correction encoding at the same time in the cache block 24 and update block 16a and other blocks within the memory array 16 also changes the manner in which the data is read from the memory array 16. The 'reading a data segment' in a conventional flash memory that implements the mEcc technique on a sector-by-segment basis involves sensing a memory cell corresponding to the segment (possibly along with other segments in other portions of the page sharing the same word line). . The data sensed for this zone also includes the actual user data (or possible control data) associated with the actual data, from which only the segment data can be used for the zone. Segment 120874.doc -33- 200814075 Data and implement ECC decoding (and correct errors detected in this decoding). In contrast, in accordance with a preferred embodiment of the present invention, ECC decoding is performed on a single page, even if only one other data segment is read. This is because the ECC bits for the page are encoded on a single data block that includes all of the segments in the page; instead referring to Figure 6a, the ECC bits in portion 42 cannot be resolved into ECC bit for each segment of the segments within page SBP5. Therefore, by way of example and with reference to FIG. 6a, if the data for the sector _ 14 is taken from the page SBP 5 in the south speed temporary storage block 14, the entire page is used as the code word, and not only the data is read and decoded. All of the material 'from segment locations s' through S4' also reads and decodes the ECC bits from portion 42. After the ECC decodes the entire page, the user data for the segment 14 can be retrieved and forwarded to the host system. As shown in FIG. 5f, after the contents are written to the update block i6a, the segment positions S1 to S3 of the scratch pad block page SBP5 are marked as obsolete. According to this embodiment of the invention, the control data Ctrl remains valid in the segment location • S3 and does maintain the same updated indicator value as the one written to the update block page UBP3 (ie, the self-pointing update block page) UBp3). The _ update indicator value thus indicates to the controller 30 that it is stored in the scratch pad block 24 for the segment 12, as described in the co-pending application Serial No. 11/192,22, incorporated herein by reference. The user profile has been replaced by writing to the update block UBP3 (which also includes user data for section 15). The control data CTRL having the updated block index value and other control and support information stored therein remains valid in the segment position S4 of page SBP5 as long as no further writes to the scratch pad block 24 are required, for example, as long as The main 120874.doc -34- 200814075 branches are written to page alignment. See the tea test chart 7 'combined Figures 5a to 5e, 6a and 6b and the above examples' will now be described in a contiguous manner in accordance with this particular embodiment of the present invention by the management of the scratch pad block 24 The data is written to the operation of the controller 30 during the flash memory device 15. In program 6G, controller 3() receives from the host system - or a plurality of segments of data along with a corresponding logical address for the poor material and writes the data to the appropriate flash memory device 15 Command or instruction. In decision 61, the control 叩3+0 determines whether the data segments received from the host system include data relative to the Wangwang page (in this example, the four segments are if the decision is yes). The Ecc engine 4 of the controller 30 then executes the program 62 to encode an error correction coding (ecc) codeword in all areas for the page. Since the full page data is received from the host system, The data generally corresponds to the user's material (ie, the host system is executing data generated by one of the applications). As described above, the encoding program 62 is based on a single data block corresponding to the data of all the sections and segments in the entire page. To generate an ECC bit or a parity bit. In this specification, the ECC engine 40 of the controller 3 performs the encoding (and decoding) operation in accordance with this preferred embodiment of the present invention. Other circuits or other functions within such controllers according to a particular architecture may perform such ECC encoding and decoding operations. Figure 8a illustrates an example of an encoding procedure a in accordance with this preferred embodiment of the present invention. 80 early Of a section index k. In the program 82, BCC engine 40 receives the location specific information to a section of the bow Shu lanyard obituaries Fo) of. Decision 83 determines if multiple segment data is still included in the current page; if it is (decision 120874.doc -35 - 200814075 83 is) then increments the index in program 85 and in the other instance of the program by the ECC engine 40. Receive data for the next segment location. Once the data for all segment locations within the page are received (decision M is no), at program 84, the ECC engine 40 forms all segments within the page. One of the user data blocks is a single data block. And in the program 86, the ECC engine 4G encodes the chat position on the single data block according to the required code implemented in the ecc engine 4〇. Preferably, the code used by the controller 3 is a system code such that the data bits remain in their original form, to which the ecc or co-located bits are attached. In combination with the tradition of the preferred embodiment of the present invention Examples of system codes include Reed Solomon codes of the desired code rate and code length and other BCH codes as are known in the art. Re-Machine 7 'Program 64 is then executed by controller 3G to include the encoding process The vehicular elements derived in 62 A page of data is written to a physical page of flash memory device 15. Program 64 includes configuring the codeword from program 62 along with header information and the like to, for example, a configuration as described above. With its low level sequencer function ^, flash control layer 42 and clothing & face 44, the controller 3 then generates appropriate control, command, position and data signals and applies the signals to the flash memory. The device 15 is used to program the UI update block or other physical location of the flash memory array 15. The control then returns to the program 6 for receiving and processing the additional user data to be written. The test 61, if a complete page of data is not received (decision 61 is no), the controller 3 then performs a decision 65 to determine whether the segment within the same page boundary as the receiving segment or segments is Appears in the high-speed temporary storage block J20874.doc -36- 200814075 65. An example of this situation has been described above with respect to Figure 5b, where the data for section #6 is received and used for section #4 and # The data of 5 is already present in the high speed temporary storage block page SBP1. If such a section already exists (decision is), then data corresponding to the sections is retrieved in program 66. Figure 8b illustrates a slave scratchpad block in program % in accordance with a preferred embodiment of the present invention. The operation of the controller 3 is captured in the data. According to the preferred embodiment of the present invention, the fetching program further corresponds to performing the reading of the segment data in any block from the flash memory device 15. The operation of the controller in the process, as long as the decoding of a data page is explained, the parsing of the segment data from the material code page is as shown in Fig. 8b, and the program 88 reads all the information for reading the page.

The data for the segment location (segment ^ to in this example) also reads its ECC code bits (eg, from ECC portions 42, 52). In the procedure 9, the ECC engine 4G of the controller 30 decodes the codeword (data plus the parity bit) into a single data block, and such decoding is performed in a conventional manner for the code in use. In this decoding procedure, it is known in the art that the error bit that has been read from the flash memory array 16 is corrected (at least as much as the code is wrong. Correct this force). The result is, for example, included in the (4) data-single data block read from the page of the flash memory array 16. In the program, only one of the header data used in the combination of the traditional readings in the technology selects the data corresponding to the required segment position Sk, and the segment data is rotated out to the controller 3(). The proper function. If the extra segment is to be read (decision 93 is YES), then the index k is incremented to the next segment location, and then the segment data is selected in the & 92-down-case item and repeated again until the capture Required section information. 120874.doc -37· 200814075 Re-testing Figure 7, if the same page as the section received in the program 6〇 does not exist in the high-speed temporary storage block 24 (decision 65 is no) or once 撷Taking such a segment already present in the south speed temporary storage block 24 (procedure 66), the controller 3 determines whether the segment received in the program 6 is tied to the last segment of the page boundary. According to the above example, wherein each page contains four items at the segment positions S1 to S4, the decision 67 determines whether the received segment corresponds to the segment position S4. #是是什么意思# Received from the host system and written to update block 1 (4). In this case, the controller 3 reads the segments from the flash memory device 15 (e.g., segment 9 of Figure 5d). Will be written in the human gastric sputum high-speed temporary storage block ^ inside ^ in the same page of the first - section of the first (four) storage data L "together together" considering the multi-segment Ecc coding better system at the same time For idle buffering and update block execution, such "fill," segment reads and decodes are performed in a similar manner as described above with respect to the ribs. Once 馨6 is fetched for all areas within the page The Ecc engine 4() executes the program 70 to encode the -ECC codeword on all segments of the page to be written in the manner described above with respect to Figure 8a. In the program 64, the above manner is followed by The m-page is written to the update block in the flash memory array 16. When the page is as before, the control returns to Sequence 60. On the other hand, if the segment receiving the autonomous (4) system does not correspond to the - last segment position within the page (decision 67 is no), then according to the embodiment of the present invention, the controller 30 proceeds Start Build - To write page to Cache: 24 operation. This is because less than - the entire page of user data has received 120874.doc -38- 200814075 from the host system, while disabling the flash memory array] The partial page of 6 is stylized, such that the cache block 24 is used to store user data equivalent to a partial page from the time store. In the program 71, the controller 3 then determines the control or support data along with the decision 67. And indicating whether the partial page of the user profile is available for temporary storage in the -page of the cache block block 24. If (decision 71 is YES), then at program 72, the controller 3 will control The data section is added to the control data section of the received host material; examples of such user beakers and & bedding pages are shown in Figure 5e and described above. If no control f is available or If such control information has been stored and not Need to update (decision is no) 'write a partial page to the cache block 24, for example as shown in Figure 5d and above. In either case, in program 74, if necessary, the intermediate section " The padding is to be written into the page of the cache block 24. In the program, the ECC engine 4G in the controller encodes a codeword on all segments of the data to be written to the human cache block 24. The coding of 76 follows the example described above with respect to the figure. In such coding, if the control data is written as shown in the figure, the control data is included in the same single data block as the user (4). If the arbitrarily-segment location does not contain data (whether or not it also includes control data), then the data for the uncomputed "〇" state (or possible T) of the memory cells is preferred. It is included in the data block in the code, just as such empty data was used as user data. After the encoding program %, a page of information is configured in the program 78, for example, if the control data is included, as shown in FIG. 8a or if the control data is not included, as shown in (10), and written by the controller 30 to the high speed temporary A page is available under the block 24 to complete the program redundancy. 120874.doc • 39- 200814075 Control then returns to program 60 for use in this manner to user and process additional and thus substantially improve the storage of data in accordance with a preferred embodiment of the present invention. Errors in the memory device process correct coding efficiency. This improvement efficiency is derived from the coverage of multiple segments encoding a larger data block regardless of the nature of the data (ie user data and irrelevant control data: the flat horse is up). This error correction coding efficiency improvement results in a higher number of error bits that can be corrected within a data segment, or a reduction in the page for one of the flash memory arrays required for a given error correction level: The number of redundant memory cells. The present invention is particularly advantageous in that it is compatible with a suffix device that prohibits partial page singulation, and thus obtains an extracriminal sinus effect of the constraint. In addition, the improved error code is used for storage and retrieval from the user area of the flash memory and also from the cache memory and other system resources. These benefits of the present invention are not only apparent in the implementation of the flash memory device itself but also include a flash memory device and a flash memory controller in a flash memory card or other system. The subsystem is more obvious. Although the present invention has been described in terms of a preferred embodiment of the present invention, it is to be understood that reference Modifications and alternatives to the advantages and benefits of the present invention. Such modifications and substitutions are not intended to fall within the scope of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram showing a conventional 120874.doc 200814075 configuration of a data page in a conventional flash memory device. 2 is an electrical diagram (block form) of a memory module constructed in accordance with a preferred embodiment of the present invention. Figure 3 is an electrical diagram (block form) of one of the flash memory cards constructed in accordance with a preferred embodiment of the present invention.

Figure 4 is a diagram showing the functional architecture of the controller in accordance with the present invention. Figures 5a through 5f illustrate a functional diagram (block form) of Figure 3 in accordance with a preferred embodiment of the present invention. High-Speed Temporary Storage and Update in Memory Figure 0. Memory of an Example of Management of Blocks Flash Memory Flash Recording Figures Figures 6a and 6b illustrate the configuration of a data page in accordance with the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S): A flow chart of the operation of the controller of FIG. 4 in accordance with a preferred embodiment of the present invention.

Figures 8a and 8b are flow diagrams respectively illustrating the application of the main components in the process of entering and reading data in accordance with the present invention. 4〇 Data 5 Flash Memory 8 Multi-Segment Page 9〇 Section Data 11 Data Section 12 ECc Bit Section 13 Header 120874.doc 200814075 13〇 15 16 16a 17 18 19 20

22 23 24 25 30 32

35 3 6 37 38 39 40 42 43 Section Data Flash Memory Device Flash Memory Array Update Block The text does not describe the control logic data register register input/output control line decoder address register register decoder "High-speed temporary storage" block flash memory card controller host interface circuit π back-end" system address translation function command sequencer table manager low-order quasi-sequencer erasure block manager ECC engine flash control layer Location Road 120874.doc -42- 200814075

44 Device Interface 51 User Data Section 52 ECC Bit Section 53 Header Section CTRL Control Data DATA_ .BUS Junction Bus HOST_ IF External Interface SI Section Position S2 Section Position S3 Section Position S4 Section Position SBP1 Page SBP2 Page SBP3 Page SBP4 Page SBP5 Page SBP6 Page UBP1 Block UBP2 Block UBP3 Block UBP4 Block 120874.doc -43 -

Claims (1)

200814075 X. Patent Application Scope: A method of operating a non-volatile solid state memory, the memory is configured with a memory unit page and each page corresponds to the memory unit that can be programmed in an individual stylized operation In one group, the method comprises the steps of: receiving data corresponding to a first plurality of segments, each segment corresponding to the amount of data 'so that the page of the memory has storage for the plurality of segments Capacity of the data; For a single data block, the coding error correction code (Ecc) is where the 'single data block contains data corresponding to the first __multiple segments; 'stylized one of the first regions of the memory The page reads the stylized first page of the memory by storing the encoded single-type data; and decoding the first page of the read using the ECC bits by the restored block, The single data area data bit corresponding to the data of the plurality of sections; and the data area of the single data block decoded by =4 are decoded. 2. The method of claim 1, wherein one of the pages of the medium-sized prints has a capacity for storing a plurality of sections for the brothers and at least one additional section; wherein the first plurality is used The receiving resource of the segment contains the user data; 'the element and the encoding step code is used for the operation of the single-type illegal data block to be included in the operation of the ECC bit of the memory data block. Doc 200814075 User data and control data. The method of claim 2, wherein the control data comprises a type of data selected from the group consisting of: a logical and physical block address table for the memory; and a data structure for the memory Index, indicator, and private, and the average read and write data used for the memory. 4. The method of claim 2, wherein the encoding step encodes an ECC bit for the single-type data block, the single-type data block containing user data, and one of the phantoms stored in the § memory A copy of the user data and control data useful in the operation of the memory. 5. The method of claim 2, wherein the memory system is configured by a block, each block includes a plurality of pages, and each block corresponds to a plurality of memory cells that can be erased in an erasing operation And wherein the control data includes an update block of one of the more memory. The method of claim 5, wherein the first page boundary is associated; /, the page is in one of the memory temporary buffer blocks; and the updated block indicator is used to point to the plurality of segments a user of a common plurality of segments, wherein the capturing step retrieves the data for the first data; and further comprising: another receiving within the common page boundary of the plurality of segments for the first a single breeding block, a segmental data, for the first plurality of regions coding error correction coding (ECC) bits 120874.doc 200814075 yuan; stylizing one of the second pages of the s memory to store the The data and the ECC bits, and the second page located within the updated block. 7. The method of claim 1, wherein the first plurality of segments are associated within a common page boundary; wherein the capturing step retrieves user data for the first plurality of segments; and further The method includes: receiving a credit for another section within a common page boundary of a plurality of sections; treating a single-type data block for corresponding to the first plurality of sections and the another zone Segment data, Encoding Error Correction Coding (ECC) bit; Stylizes a second page of the memory to store the data and the ECC bits. 8. A method of controlling writing and reading to a flash memory device, the flash memory device having a plurality of memory cells in a page configuration, each page having a memory segment corresponding to the plurality of segments The data has sufficient capacity, and the child page is configured as a block, and the method includes the following steps: • receiving the data for the at least one first segment to be written to the flash memory device; The received data smaller than a complete data page forms a data block, the data block includes the received data and further includes control data useful in the operation of the flash memory device; 120874.doc 200814075 in the data block An upper coding error correction coding (ECC) bit; and a first page of one of the first selected blocks in the spear-shaped sigma flash memory device to store the data of the data block and the £(:€ The method of claim 8, wherein the data block further comprises a copy of the data previously stored in the 4 flash memory device. 10. The method of claim 8, further comprising · Receiving data for a second segment corresponding to the same page as the data of the first segment; δ fetching the first page of the first selected block; decoding the read using an ECC bit such as σHai Taking the first page, recovering the 5 荨 data bit as a singular data block corresponding to the data of the first segment; ^ into the data containing the first and second segments a block; a code error correction coding (ECC) bit for the data block including the first and second sectors; and a second page of the memory to store the coded data block. Going with the person 10, where the second page is in the first selected block. 12. 12. The method of requesting item U, the # contains the tributary blocks of the first and second sections. Further contains control information. The method of requesting 1G, wherein "the second page is in the selected block of one of the flash memory devices; # and wherein the control data includes - updating the block indicator 1 to point to the selected area of the brother Piece. The method of claim 13, wherein the first selected block is a high speed temporary block 'and wherein the second selected block is an updated block. The method of claim 8, wherein the control data comprises a type of data selected from the group consisting of: an alpha code and a block address table for the flash memory device; The index L index and displacement of the data structure in the memory; and the average reading and writing data for the memory. 16: The method of claim 8, wherein the first selected block is a high speed temporary storage block. 1 7. A flash memory system, comprising: a flash memory device having a memory unit, a plurality of pages, a plurality of blocks, ... sufficient to store data for a plurality of segments: Memory unit, and each block has a plurality of pages; flash memory control crying, t set, including · ° ° eight-coupled to the flash memory device host '丨面' for the interface - host System; device interface, Futian μ into the controller circuit, 1 with = connected to the flash memory device; and the machine interface received: the machine = according to an operation sequence will be included in the main operation sequence: / + written to the flash memory device, for a single data bit, the single data block: block 'code error correction coding (ECC) host data; ^ '匕 & corresponds to a first a stylized first page of a plurality of sections, reading the stylized number = a single data block storing the code; 120874.doc 200814075, using the ECC bits, decoding the read _th page, To:,, and to include a single type of data corresponding to the plurality of sections Feedblock to restore such data bits; and a center to retrieve required information from the decoding section of the data block in a single formula. The system of claim 17, wherein the reading step is performed in response to receiving a read command at the host interface; and wherein the sequence of operations further comprises: The required segment data is forwarded to the host interface. 1 乂% of the system of claim 17 wherein at least one of the first plurality of segments includes host data received at the host interface, and wherein the encoding operation encodes a coffee for the single data block Bit, the single data block contains host data and control data useful in the operation of the flash memory device. 2〇·如明求! The system of claim 9, wherein the encoding operation encodes a chat bit for the single-type f block, the single-type data block includes the host data, 4 control money, and a host material previously stored in the (4) memory device One is too. [21] The system of claim 19, wherein the method comprises a type of material selected from the group consisting of: 孓贝枓·Logic and entity for the memory & a block address table for indexing, indexing, and shifting of the data structure in the device for use in the device; and for the flash data. The average read and write of the threshold hidden device 22. In the system temporary storage block of claim 21, wherein the first page is in the memory of one of the heights 120874.doc 200814075 and wherein the control data includes an update area Block indicator, used to refer to one of the memory update blocks. The system of claim 17, wherein the first plurality of segments are associated within a common page boundary; wherein the capturing step retrieves user data for the first plurality of segments; and further comprising : receiving data for another segment within a common page boundary of the first plurality of segments; treating as a single data block for another segment corresponding to the first plurality of pseudo-regions Data, Encoding Error Correction Coding (ECC) bit; Stylize a second page of the memory to store the data and the ECC bits, and the second page located within the updated block. The system of claim 17, wherein the first plurality of segments are associated within a common page boundary; wherein the capturing operation retrieves user data for the first plurality of segments; Further comprising: receiving data for another segment within a common page boundary of the first plurality of segments; treating as a single data block for another region corresponding to the first plurality of regions k and Paragraph data, Encoding Error Correction Coding (ECC) bit; 120874.doc 200814075 Stylized one of the ECC bits of the memory. Two pages to store the information and such I20874.doc