WO2007137013A3 - Error correction coding for multiple-sector pages in flash memory devices - Google Patents

Error correction coding for multiple-sector pages in flash memory devices Download PDF

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Publication number
WO2007137013A3
WO2007137013A3 PCT/US2007/068797 US2007068797W WO2007137013A3 WO 2007137013 A3 WO2007137013 A3 WO 2007137013A3 US 2007068797 W US2007068797 W US 2007068797W WO 2007137013 A3 WO2007137013 A3 WO 2007137013A3
Authority
WO
WIPO (PCT)
Prior art keywords
page
flash memory
data
error correction
ecc
Prior art date
Application number
PCT/US2007/068797
Other languages
French (fr)
Other versions
WO2007137013A2 (en
Inventor
Sergey Anatolievich Gorobets
Original Assignee
Sandisk Corp
Sergey Anatolievich Gorobets
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/383,841 external-priority patent/US20070300130A1/en
Priority claimed from US11/383,844 external-priority patent/US7809994B2/en
Application filed by Sandisk Corp, Sergey Anatolievich Gorobets filed Critical Sandisk Corp
Publication of WO2007137013A2 publication Critical patent/WO2007137013A2/en
Publication of WO2007137013A3 publication Critical patent/WO2007137013A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)

Abstract

A flash memory system, including a flash memory device and a controller, and having improved efficiency error correction coding (ECC), is disclosed. Each page in the flash memory device has the capacity to store multiple sectors' worth of data. However, partial page programming (i.e., followed by a later write to fill the page) is prohibited for reliability reasons. A scratchpad block within the flash memory device is designed, and stores both user data and control data. ECC efficiency is improved by encoding the ECC, or parity, bits over the entire data block corresponding to the user and control data in the page. Retrieval of a particular sector of data requires reading and decoding of the entire page. Especially for codes such as Reed-Solomon and BCH codes, the larger data block including multiple sectors' data improves the error correction capability, and thus enables either fewer redundant memory cells in each page or improved error correction.
PCT/US2007/068797 2006-05-17 2007-05-11 Error correction coding for multiple-sector pages in flash memory devices WO2007137013A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/383,841 2006-05-17
US11/383,841 US20070300130A1 (en) 2006-05-17 2006-05-17 Method of Error Correction Coding for Multiple-Sector Pages in Flash Memory Devices
US11/383,844 US7809994B2 (en) 2006-05-17 2006-05-17 Error correction coding for multiple-sector pages in flash memory devices
US11/383,844 2006-05-17

Publications (2)

Publication Number Publication Date
WO2007137013A2 WO2007137013A2 (en) 2007-11-29
WO2007137013A3 true WO2007137013A3 (en) 2008-07-17

Family

ID=38723960

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/068797 WO2007137013A2 (en) 2006-05-17 2007-05-11 Error correction coding for multiple-sector pages in flash memory devices

Country Status (2)

Country Link
TW (1) TW200814075A (en)
WO (1) WO2007137013A2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100458718C (en) * 2006-12-29 2009-02-04 福昭科技（深圳）有限公司 Method of correcting error code for multiple sector
TWI395222B (en) * 2008-12-05 2013-05-01 Apacer Technology Inc A storage device having a flash memory, and a storage method of a flash memory
US8214580B2 (en) 2009-10-23 2012-07-03 International Business Machines Corporation Solid state drive with adjustable drive life and capacity
US7954021B2 (en) 2009-10-23 2011-05-31 International Business Machines Corporation Solid state drive with flash sparing
WO2012079216A1 (en) * 2010-12-13 2012-06-21 Mediatek Singapore Pte. Ltd. Nor flash memory controller
CN102394114B (en) * 2011-11-14 2014-01-01 清华大学 BCH code error correction method capable of adaptive error correction

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030056141A1 (en) * 2001-09-18 2003-03-20 Lai Chen Nan Control method used in and-gate type system to increase efficiency and lengthen lifetime of use
US20030156454A1 (en) * 2002-02-21 2003-08-21 Jian Wei Direct memory swapping between NAND flash and SRAM with error correction coding
US20040123020A1 (en) * 2000-11-22 2004-06-24 Carlos Gonzalez Techniques for operating non-volatile memory systems with data sectors having different sizes than the sizes of the pages and/or blocks of the memory

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040123020A1 (en) * 2000-11-22 2004-06-24 Carlos Gonzalez Techniques for operating non-volatile memory systems with data sectors having different sizes than the sizes of the pages and/or blocks of the memory
US20030056141A1 (en) * 2001-09-18 2003-03-20 Lai Chen Nan Control method used in and-gate type system to increase efficiency and lengthen lifetime of use
US20030156454A1 (en) * 2002-02-21 2003-08-21 Jian Wei Direct memory swapping between NAND flash and SRAM with error correction coding

Also Published As

Publication number Publication date
WO2007137013A2 (en) 2007-11-29
TW200814075A (en) 2008-03-16

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