TW200807974A - Delta-sigma modulated fractional-N pll frequency synthesizer - Google Patents

Abstract

A delta-sigma modulated fractional-N PLL frequency synthesizer. The frequency synthesizer includes a phase frequency detector for receiving a reference signal with a reference frequency (Fref) and a overflow signal and outputting a phase difference signal after comparing the reference and overflow signals; a charge pump for generating an outputting current in response to the phase difference signal; a loop filter for smoothing the output current and outputting a corresponding control voltage; a voltage controlled oscillator for generating a voltage controlled signal with a voltage controlled frequency (Fvoc) in response to the control voltage; and a delta-sigma modulator having a clock input terminal for receiving the voltage controlled signal, a overflow output terminal for generating the overflow signal, and a integer input terminal for determining a ratio of the voltage controlled frequency (Fref) and the reference frequency (Fref).

Description

200807974 IX. INSTRUCTIONS: [Technical field to which the invention pertains] The present invention relates to a frequency synthesizer of the type Dyeda _ singapore Μο « ^ ^^Lcked L〇〇P ' PLL), and in particular About direct replacement of frequency

The number N phase-locked loop frequency synthesizer is implemented by Dailing Singer. [Prior Art] Due to the rapid development of communication systems (Commimicaticm System), such as hand-held • __ system, with higher resolution (Frcq deleted cy - ReSGlUtk) n) and faster frequency switching time (fequeney switching)

The "synthesis of Time" is a component that related technology developers are trying to develop. However, the above requirements are difficult to achieve. Please refer to the figure-picture, which is shown as a phase-loop frequency synthesizer with the integer (5) training. The phase locked loop 1〇〇 includes a phase frequency detector (Phase Frequency Detector) 1〇, a charge pump (charge)

Pump) 20, loop filter (L00p) 3〇, Voltage Controlled 〇scillator 40 and Divider =. Wherein, the reference signal having a reference frequency Fref is generated, for example, by a reference Oscillator (not shown), and the reference numeral and a frequency divided signal are simultaneously input to 200807974 = bit frequency. Detector 1G. The phase frequency detector (7) can detect the difference between the phase and the frequency between the spring=number and the frequency-divided signal, and then the out-phase difference signal (phase service (four)丨) to the electricity: = the person's charge The pump 20 according to the phase difference _ round current to the back _ two off 1 pressure control record to the command ^^; 0! 1) the output current 'and converted to milk - power plant sewing · 4 唬 with - pressure Control frequency 卩. ^ Output & number, and the round is divided by an integer N times, the production 5G can receive the round-out signal and _ 10, so the phase-locked loop frequency 3 is used to input to the phase frequency is obvious, because N is The integer ff is available for 匕. State Fref. (FVc.) must be the reference frequency of the frequency-locked loop frequency of the voltage-controlled frequency of the wheel to synthesize 'integer multiples, so 'in the past few years, the lock of the fractional N:, the frequency resolution is lower . Since N is a fraction, the round-out, road frequency synthesizer has appeared. The frequency is subdivided, therefore, the score; the control scale (Fve.) is a reference with a higher resolution of the cheek rate. , phase-locked loop frequency synthesizer wheel out Please refer to the second figure, which is drawn, frequency synthesizer. The second figure and the first figure of the lock-in phase (Divider) 55 having a score of N are: the difference is that the multi-integer frequency divider is complicated. The multi-integer addition of _ 5 = 'the circuit hardware design is also provided by the first integer (A) and the number N is controlled by a register inter-symmetric modulator) Tower 'Singerma modulator (with ',, ~ second integer. From the second figure can be 7 200807974 ^ Σ 魏 Wei 6G has - clock input end and wheel end, and Δ Σ 60 60 Time = value (the device 55 secret (four) n let the wheel into the know to connect to the multi-integer frequency divider 65. Second, the round-off end of the 6-turner is connected to an addition: distance $: sub-salen 7 〇 storage - integer A The register 70 outputs = 妾^ adder 65, and the frequency divider (Dg phase integer N is changed according to the output value of the adder 65. Δ二二(8) diagram, the 1 is shown as a digital Stacker (Digital

The realization of the - (Fim〇rder) ΔΣ modulator. For example, 'Brother 4: The size of the 62 is the d-bit (1)), with the $day pulse input, one-input (X), - second input (Y), one plus The total wheel end (X+Y) and the overflow (Overflow) output (9). Furthermore, the first input (X) can input a first value (n), the second, the input y (Y) and the total wheel end (χ + γ) are connected to each other, and the overflow wheel end (9) is visible. It is the output of the first-order ΔΣ modulator. a n=5, d=4 =, Table 1 below represents the output value of the total output (χ+γ) and the overflow output (〇) as the clock changes.

According to Table 1, it can be known that the total output (X+Y) and the overflow of the overflow wheel will be one cycle every 16 clocks, and the same round-out value will be repeated. Furthermore, on average every 16 clocks, the overflow output will be triggered (Toggle) 5 times in 200807974. Similarly, when the first value (n) is changed to 9, = average for each clock, the overflow wheel will be triggered 9: owe: due:, the brother-value (η) represents the average every 16 hours Pulse, overflow, the number of times the output will be triggered. The repetition period of the 16 clocks is determined by the size of the adder, and since d = 4, 24 represents 16 clocks. Therefore, when the size of the adder 62 is d bits and the first value is n, it represents 2d; ^^

The output of the bit wheel will be triggered n times, and the output value of the summed output (χ+γ) and the overflow output (〇) will repeat the same round out value every 2d clocks. The first-order ΛΣ modulator of the third (a) diagram can also be represented by the Discrete Time function, as shown in the third (b) diagram. As shown in the figure, when the stacker generates an overflow, since the value has exceeded the value that can be expressed by its size, the comparator 64 outputs, and Tian Jiazhai has not generated an overflow because the value does not exceed its size (&amp ; sink) can represent the value, so the comparator 64 will lose $ "〇,,,,,, = 64 is compared with the maximum value that the superimposer can represent as the threshold (Threshold). The second picture of Cang Kao is determined by the round of the clock-number divider 55 of the κΔΣ modulator (6). Xi Zheng d=4, μ~ This is the size of the ΛΣ modulator (,,,,,歹'Female 16 clocks, ΔΣ modulator 60 overflow output on the 0 mountain) will be triggered 5 times. That is to say, every 16 clocks, the other is (9) is not triggered, multi-integer, anti ^ When the overflow of the overflow wheel (9) is triggered, the multi-integer is divided; otherwise, when the average is de) n = tN = A + 1. Therefore, the integer (score, (four) is A + 5 / 16) =, N Can be regarded as a non-buried, the size of the transformer is 200,807,974. This has a sub-value of n, which will make the A cut 2' H lock (4), and the rate can be realized. Shows the phase-locked loop frequency with sub-(4) synthesizing i-number divider 55. = Design of the mating register 7 〇 蝴 成 Μ 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 复杂 复杂 复杂 复杂 复杂 复杂 复杂 复杂 复杂 复杂 复杂 复杂 复杂 复杂 复杂 复杂 复杂 复杂 复杂 复杂 复杂 复杂- no need to break other circuits (four) ~ except for the attack

Therefore, the single-integral image of the younger one is simple. Therefore, ^ will be more than the second figure of the multi-integer frequency divider 55 simple and eight teaching X b how to improve the above-mentioned missing, design a structure of the car-phase smashing phase-locked loop frequency synthesizer is the main purpose of the invention: SUMMARY OF THE INVENTION The present invention proposes a - reference signal and an overflow output signal having a fraction. There is a > frequency between the overflow output signal - phase and detection signal and: differential signal; a charge pump for receiving the phase flow; - a loop filter for receiving the round of the core; ::- After the current is turned on, the output is converted to electricity--the signal is generated; - the wheel is powered to receive the signal, and the scale is controlled according to the electric cover:: There are: 200807974 Voltage-controlled frequency-output signal; and a ΔΣ The transformer has a clock input terminal for receiving the output signal, and an input terminal for rounding out the overflow (4) of the overflow value for determining a ratio between the voltage control frequency and the frequency of the meal test. According to the above concept, when the size of the ΛΣ modulator is d bits and the integer value input terminal inputs η, the ratio is 2%, where read. Both are the whole modulators, which are --- (10) transformers. Cheng,: Τϊίί 'The first-order ΔΣ modulator is composed of - accumulators for shooting '1st benefit can have - first - wheel end and - second input is rotated by the summed output Two plus 婢, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , And the overflow trigger signal that is rotated by ^周❹ has a - adjustable arbitrator, = 妓 妓 妓 妓 妓 妓 : : : : - - - - - 相位 相位 相位 相位 相位 相位 相位 相位 相位 相位 相位 相位 相位 相位 相位 相位 相位 相位The magnitude of the difference signal with the overflow trigger signal ^ = test frequency is related to the = sign and according to the phase, the wave converter 11 200807974 converts and outputs a voltage control signal; a voltage controlled oscillator for receiving the voltage Controlling a signal and generating an output number having a voltage control frequency according to the voltage control signal; the previous down-converter is configured to divide the voltage control frequency by a first integer value and output a down-converted signal; and, a modulator having an output of the clock wheel that can receive the down-converted signal and outputting the overflow output signal Overflow output terminal and - a second integer value round person terminal for the root

A ratio between the underface ratio and the reference frequency is determined based on the first integer value and the second integer value. - According to the above concept, the size of the ΔΣ modulator is d bits, and the ratio is m*2d/ii when the input value of the first integer value is m and the input value of η is input to the input terminal. According to the above concept, the ΔΣ modulator is a first-order ζ\Σ modulator. Cheng, 3 back to the idea that the first-order ΔΣ modulator is composed of - accumulators, the accumulator can have a first input and a second round to use the - The two values of the input of the Kaohsiung J brother add up the rear position wheel and generate the overflow level when the total value of the two additions is overflowed. The diagnosis is: wherein the first input is the whole The value of the younger brother - the wheel end is connected to the output of the summed output. According to the concept of the second embodiment, the rainbow modulator is a second-order rainbow modulator, and the overflow output signal of the output of the akisaki device has an adjustable - internal tUf member to learn more. The present invention is not to be construed as limiting the invention. 12 200807974 [Embodiment] In the second figure, the size of the first-order ΛΣ modulator (four), the first value 5 is taken as an example 'representing every 16 clocks, △[the modulator overflow output terminal (9) ^ is triggered 5 times. Observed from the point of view of the solution, it can be regarded as every 16 clocks. The position of the bit wheel (9) will produce 5 _ pulses, that is, the overflow output, the frequency of the input frequency of the tree, and the frequency of the input end, so according to the round The first value (η) of the second can determine the frequency of the overflow output terminal (9) so that the frequency of the overflow wheel outlet (〇) and the frequency of the clock input terminal become a fractional relationship; In the 〇, the integer 200 is taken as an example, the adder 65, the output is fine or 201 is supplied to the multi-integer frequency divider 55 for frequency division, and the long-term viewing is equivalent to the frequency division 2_5/16, but the multi-integer frequency divider The implementation is complex and prone to glitch (s solution) on the spectrum. Please refer to the fourth figure' which is shown as a phase-locked loop frequency synthesizer with a fraction N of the present invention. The phase-locked loop frequency synthesizer includes a phase frequency Detector 210 and a charge pump (Charge)

Pump) 220, Loop Filter 23〇, Voltage Controlled 〇scillator 240 and ΔΣ modulator 25〇. The reference signal having the 'Fr*ef' is input to the phase frequency detector 21 by the reference signal generated by the reference oscillator (not shown) and the overflow output signal (Overflow Output Signal). Hey. The phase frequency side device 21G can side the difference between the phase and the frequency between the reference signal and the overflow signal, and then a phase difference is transmitted to the charge pump. The load pump (10) generates a phase _ (for example, a proportional relationship) according to the magnitude of the phase difference signal, and the current of the phase difference signal is -2 to 3 〇. Then, the loop filter 23 〇 smoothes the wheel current and converts the voltage control unit 24 (). The voltage suppression two control signal generation-rounding signal, ‘ it ^ ^ (FVC〇) 〇 ^ΔΣ 1^1 250 ^^ , the input ^ can receive the output signal, and the Δ Σ word variator 25 〇 the sound level 2:. The overflow output signal can be output for rounding to the phase frequency: 贞 = the size of the Δ 250 250 is d and the first value is connected to the δ ς modulation when the wheeled signal with a voltage control frequency such as 〇) The sigmoid input, the average η/2, _, overflow (four) can be ^ pulse, therefore, the ΔΣ modulator 25G can be based on the clock of the clock wheel to the south of the low level signal. Therefore, the frequency of the overflow output = signal generated by the overflow output is the voltage control frequency (Fve.) n/2d times. The signal _ rate is equal to the reference solution (5) f), so it can be = Fref = n / 2d * FVC0, that is, Fvc 〇 = 2 VFref. In (4): : For example, the present invention has a phase-locked loop frequency synthesizer with a fractional N: 16/5=3+1/5. That is to say, from the modulator 25, according to the clock output of the clock input, the clock signal having the score of the high and low level of the score is Δ Σ 周 _ _ 取代 取代 取代 取代 取代 取代 取代 取代 取代 取代Circuit wood structure. Therefore, 'the present invention has a fractional N _ phase loop frequency 14 200807974 The synthesizer has the advantages of simple structure and easy design. For the first practical example, say d=32, n=235,260,482 ’ (232/235260482) two 18.25622. When the reference frequency (Fref) is 4.92 ,, the voltage control frequency (Fvco) is 89·82 ΜΗζ.

In order to improve the voltage control frequency (Fvco), the present invention can provide a single positive (N, for example, 33) frequency divider, which is connected between the voltage controlled oscillator 240 and the ΔΣ modulator 250 in the fourth figure. . This single integer divider can also be referred to as the previous downscaler (Pre_Scaler). In the actual -, for example, when d two 32, n two 235, 260, 482, (2 /23526G482): 18.25622. When the reference frequency (Fref) is 4 92MHz, 'Because the previous frequency reduction ratio (Pre_Scaler) has a frequency division ratio of 33, the voltage control frequency can reach: Fvc〇=(33) * (^2 ribs) (4.92MHz) ^2.964Ghz - — ...,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Figure. And the fifth _, the actual distribution

Uner Transformatl〇n ‘short for fft) (10)). It can be seen from the fifth (a) diagram that the electric crying FT := state I will produce - chopping two;: the represented i ΛΣ modulator to explain, from the table by = d = 4, with 16 clocks - Cycle, overflow output end = _ 疋 after __ 崎, ^ ~ five: owed = 15 200807974 Batches over three clocks 'such periodic generation. This will cause the voltage = signal to go back and forth around the steady state. Furthermore, the first-order ΔΣ modulator from the fifth _ spectrum can produce an unwanted glitch C Spurs at high frequencies. In order to P-low dog wave (SpUrS), the second-order ΔΣ-meaning can be used in the present invention. . Laibei is now, 5 green 苓 according to the sixth picture, which is shown as the second-order modulation = turn time (DlsereteTlme) function. This second-order 调%%°°° is realized by a single loop (single) by Cascade. This second-order ΔΣ modulator has four increments of a, b, c, and e.疋 is 1, and further, the shape of the quantization noise can be appropriately adjusted by adjusting the values of a, b, c, and e (turning to the shape of the shape), 1 does not affect the desired score, Preferably, the values of &, b, c, and e are appropriately selected as powers of 2, such as 1/2, 1/4, 1/8^ on the digital domain circuit, 2 powers The square can be shifted by the temporary storage iU_register), so the circuit complexity can be greatly simplified, and the desired noise shape can be obtained. The second-order modulator can select the output of the first comparator 252 of the last stage or the output of the second comparator 54 as the overflow output. Wherein, the first comparator 252 is on the round-trip routing, and the threshold value is the maximum value that the second-order modulator can represent; and the second comparison H 254 is on the independent transmission path, and the threshold is The value can be arbitrarily set such that the duty cycle of the signal at the overflow output is variable. Preferably, the value set by the second comparator is half of the maximum value that the second-order modulator can represent, so the 'first comparator 252 and the second comparator 254 will rotate the same phase phase 16 200807974 The same frequency signal, the difference is that the responsibility of the second comparator is that, when the frequency division ratio (N) is large, the binary π modulator can maintain a signal with a duty cycle of about 5〇%. White Again, the biggest advantage of the second-order ΔΣ modulator is the de-frequency ratio and the irregularity of the overflow signal. Take the second-order ΔΣ modulator of (4), = as an example, each time with 16 clocks - = ' can be triggered five times, but the time of the trigger is not regular. = The time of the trigger is triggered. ? Use the second-order ΔΣ modulator f顼 and the ancient eight # Θ 施 施 施 施 施 施 ( ( ( 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四= seven (_, fine _ is _ the side of the real △ Σ 所 所 所 不 不 不 不 不 不 不

Ft AV ^ 1 ^ N phase-locked loop frequency synthesis The spectrum of the fast Fourier transform of the white clock (4) knows that the voltage-controlled oscillator (:) diagram does not generate chopping. Furthermore, by the increase (4), the modulator will have been effectively reduced at high frequencies, and the Σ white ΔΣ field / Shizhen purs). The loop frequency is crying, you ~ early with a fractional μ lock phase effect reduction L skin L " road design can be significantly simplified, and there is a small U) and the H and the hair is based on ΔΣ The large phase value (η) of the transformer has a fractional value of ν, which is the frequency division value (score Ν) of the sheep's mouth. In the above, the present invention has not been used to limit the present invention, and the present invention is not limited to the above. However, it is not necessary for those skilled in the art to fall within the spirit and scope of the invention of the present invention. When it is possible to make various changes and retouchings, the insufficiency of the application for patents is subject to the scope of the patent application. - [Simple description of the schema] By the following diagram and detailed description, Chad - more = WVf knows that the phase-locked rate of the integer N = the edge of the spear is a fraction with the fractional phase-locked loop frequency: Two devices. The first-order ΔΣ modulation of the test should be added. The figure =) shows the discrete-time (7) muscle coffee τ first-order ΔΣ modulator. 7 w demon said that the fourth picture is expected to reduce the frequency of the frequency synthesizer. Phase-locked back with fraction N The fifth (a) diagram shows the electrical phase of the phase-locked loop frequency synthesizer with a fractional-N signal versus time graph. The voltage control of Chen Yingzhai's rotation is shown in the figure 5).

In the phase-locked loop frequency synthesizer, a spectrogram with a fractional N-change is implemented.快速, the fast Fourier turn of the patriarch:: Schematic diagram of the discrete time function. The phase lock achieved by the device with the fractional ν is forced to use the voltage of the second-order modulator and the voltage control of the generator to determine the time of the machine. 18 200807974 The seventh (b) diagram (5) is a spectrum diagram of the fast Fourier transform with a fractional N and a fast Fourier transform according to this = using a two-frequency synthesizer to adjust the second-order Δ Σ 【 [mainly Description of component symbols] The components included in the diagram of this case are listed below...

10 phase frequency detector 30 loop filter 50, 55 frequency divider 62 adder 65 adder 100 phase lock loop 210 phase frequency detector 230 loop filter 250 ΔΣ modulator 254 brother two comparator 20 charge pump 40 voltage control oscillator 6 〇 Σ Σ modulator 64 comparator 70 register 200 phase-locked loop frequency synthesis cry 220 charge pump 240 voltage control oscillator 252 first comparator 19

Claims (1)

200807974 - X. Patent application scope: 1. A phase-locked loop frequency synthesizer with fraction N, comprising: a phase frequency detector capable of receiving a reference signal having a reference frequency and an overflow output signal and detecting Detecting a phase difference signal between the reference signal and the overflow output signal, and outputting a phase difference signal; a charge pump 'for receiving the phase difference signal and generating a correlation according to the magnitude of the phase difference signal An output current of the phase difference signal; a first loop filter for receiving the output current and smoothing the output current to convert and output a voltage control signal; a voltage controlled oscillator for receiving the voltage control signal Generating an output signal having a voltage control frequency according to the voltage control signal; and a ΔΣ modulator having a clock input terminal for receiving the output signal, an overflow output terminal for outputting the overflow output signal, and An integer value - an input terminal for determining a ratio between the voltage control frequency and the reference frequency. 2. The phase-locked loop frequency synthesizer having a fraction N according to claim 1, wherein the ratio of the ΔΣ modulator is d bits and the integer value input terminal inputs η, the ratio is 2d/n, Where d and η are both integers. 3. The phase-locked loop frequency synthesizer having a fraction Ν as described in claim 1, wherein the ΔΣ modulator is a first-order ΔΣ modulator. 4. The phase-locked loop frequency synthesizer having a fractional chirp as described in claim 3, wherein the first-order ΔΣ modulator is composed of an accumulator, wherein the accumulator may have a first input terminal, a second input end and a total input-output end for adding two values of the first input end and the second input end to 20 200807974, and then outputting the total output end, and when the first When the two values of the input end and the second input add up to generate an overflow, the overflow output end outputs a pulse; wherein the first input end is the integer value input end, and the second input end is The summed output outputs are connected to each other. 5. The phase-locked loop frequency synthesizer having a fraction N as claimed in claim 1, wherein the chirp modulator is a second-order delta-sigma modulator. 6. The phase-locked loop frequency synthesizer having a fraction N as claimed in claim 5, wherein the overflow output signal output by the second-order ΔΣ modulator has a β-reversible period. 7. The phase-locked loop frequency synthesizer having a fraction N as claimed in claim 5, wherein the second-order ΔΣ modulator has a plurality of gain units that adjust the quantization noise shape. 8. The phase-locked loop frequency synthesizer having a fraction N as claimed in claim 5, wherein the gain values of the gain units are all powers of two. 9. The phase-locked loop frequency synthesizer having a fraction N according to claim 1, wherein the charge pump receives the phase difference signal and generates an output current proportional to the phase difference signal according to the magnitude of the phase difference signal. . 10. A phase-locked loop frequency synthesizer having a fraction N, comprising: a phase frequency detector capable of receiving a reference signal having a reference frequency and an overflow output signal, and detecting the reference signal and the Outputting a phase difference signal after a phase difference between the overflow output signal and a frequency; a charge pump for receiving the phase difference signal and generating a phase difference signal according to the magnitude of the phase difference w signal An output current; 21 200807974 chill circuit filter for receiving the round current and smoothing the output of the output signal after the output is added; Also 丨咕 ) ) 役 役 ) 役 役 役 役 役 役 役 役 役 役 役 役 役 役 役 役 役 役 役 役 役 役 役 役 役 役 役 役 役 役 役 役 役 根据 役 役 役 役 役 役 役 役 役 役屮兮 夕 、 4 4 4 4 4 守 守 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 输入 ^ ^ ^ ^ ^ ^ ^ With the mouth of the sheep The ratio of the frequency of the test. The value of the pin axis rate and the reference u. As described in Shen Qing Patent Range 10, there is a synthesizer, wherein the size of the ΔΣ modulator is the phase-locked loop frequency value input 岐 the second value of the input ^ = yuan ^ The first integer m*2% 〇 input n day inch 'this ratio is 12 · as described in the patent scope 1 具有 with a synthesizer, wherein the 锁1 number N of the phase-locked loop frequency A such as the first-order rainbow Transformer. Synthesizing the phase-locked loop frequency with a fraction N as described in C2; the device is composed of an accumulator: the XUU has a first input end and a round output end for the first input end and the first: After the input, the sum and the sum total are output, the sum of the two values of the input and output terminals produces an overflow:; =: the ingress and the second out-pulse; wherein The first round entry is the == 22 200807974, and the second input is connected to the summed output output. 14. The phase-locked loop frequency synthesizer having a fraction N as claimed in claim 10, wherein the chirp modulator is a second-order delta-sigma modulator. 15. The phase-locked loop frequency synthesizer having a fraction N as recited in claim 14, wherein the overflow output signal output by the second-order ΔΣ modulator has an adjustable duty cycle. 16. The phase-locked loop frequency synthesizer having a fraction N as recited in claim 14, wherein the second-order ΔΣ modulator has a plurality of gain units, wherein the quantized noise shape is adjustable. 17. The phase-locked loop frequency t synthesizer having a fraction N as claimed in claim 14, wherein the gain values of the gain units are all powers of two. 18. The phase-locked loop frequency synthesizer having a fraction N as claimed in claim 14, wherein the ΔΣ modulator is a single-loop second-order ΔΣ modulator. 19. The phase-locked loop frequency having a fraction N as recited in claim 10 is synthesized as 'where the electrical hub receives the phase difference signal and produces an output current proportional to the phase difference signal based on the magnitude of the phase difference signal. twenty three