TW200807870A - Rail-to-rail operational amplifier with an enhanced slew rate - Google Patents

Abstract

A rail-to-rail operational amplifier is provided with a high-side current adjusting circuit and a low-side current adjusting circuit. On a basis of a comparison between a first input voltage and a second input voltage, the high-side current adjusting circuit adjusts a high-side bias current. Under a condition that the first input voltage is smaller than the second input voltage, the high-side current adjusting circuit increases the high-side bias current when an absolute of a difference between the first and the second voltages increases. On a basis of the comparison between the first and the second input voltages, the low-side current adjusting circuit adjusts a low-side bias current. Under a condition that the first input voltage is larger than the second input voltage, the low-side current adjusting circuit increases the low-side bias current when the absolute of the difference between the first and the second voltages increases.

Description

200807870 IX. Description of the invention: ‘Technical field to which the invention pertains. The present invention relates to a rail-to-rail n +. t Λ rail-shifting amplifier (Rail-to-Rail)

Operational Amplifier), especially j: confession ’About iSlew with a high conversion rate

Rate) rail-to-rail operational amplifier. (4) Material (Slew [Prior Art,] Figure 1 shows a circuit diagram of a conventional rail-to-rail operational amplifier 1。. Figure 1, a rail-to-rail operational amplifier 10 Town A external negative complementary differential input stage, its brother - With the second P-type transistor PQ1 and PQ2

The transistor is composed of NQ1 and NQ2. , brother, a N on the wind brother one? The polarity of the transistor PQ1 is the same as that of the second phase, and the source of the transistor PQ2 is in contact with each other. The drain of the first P-type transistor PQ1 and the drain of the second P-type transistor PQ2 are coupled to the 1-port total output stage 11, respectively. The fixed upper bias current source ICH is in contact with the upper side supply voltage VH and the source between the first and second p-type transistors PQ1 and pQ2. The first input voltage Vinp is applied to the gate of the first P-type transistor PQ1, and the second input voltage Vinn is applied to the gate of the second P-type transistor PQ2. The potential difference between the first input voltage Vinp minus the second input voltage ν·I can be defined as a differential voltage DV, also DVr(rnp-Vinn). At the control of the differential voltage Dv, the fixed upper side bias current source ICH is divided and flows through the first and second p-type transistors PQ2. ”

The source of the N-type transistor NQ1 is coupled to the source of the second N-type transistor NQ2. The drain of the first N-type transistor nqi is combined with the second pole of the second N 4 200807870 transistor NQ2 to add the total wheel stage j丨. The fixed lower bias current source ICL is coupled between the source of the mutual coupling of the first and second N-type transistors and NQ2 and the supply voltage of the lower side. The first input voltage Vinp is applied to the gate of the N-type transistor NQ1, and the second input voltage V, inn is applied to the gate of the second N-type transistor NQ2. Under the control of the differential voltage DV, a fixed lower bias current source is divided and flows through the first and second N-type transistors NQ1 and NQ2.

The summed output stage 11 is used to combine four current signals from the complementary differential input stage, i.e., four current signals from the drains of transistors pQ1, pQ2, nqi, and NQ2, respectively. Finally, summing the output stage 11 converts this current combination into an output voltage. The operation of the rail-to-rail operational amplifier 10 can be divided into three ranges depending on the common mode (C〇mm〇n Mode) voltage v(3). In the low range of nCM < (VL + Vtn) (here, the conduction voltage of the N-type transistor) 'the first and the second N-type transistors NQ1 and NQ2 are in the state of no operation, so the rail pair The operation of the operational amplifier 10 is performed separately. _ ~ The power generation day and the body PQ1 and PQ2 constitute the upper side differential = the pair is engaged. In the high range of (VH-lvtPl) <vCM<vH (where vtp: the on-state threshold voltage of the P-type transistor), the first and second p-type transistors 1 and PQ2 are in a non-operating state, The operation of the rail-to-operator op amp 10 is composed of the first Kim Kyung-sing two N-type transistors NQ1 and NQ2, and the lower differential input pair > t is executed at 0 (VL + Vtn) <VCM< (VH-|Vtp|) in the middle of the dry circumference, because 筮 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ NQ2 can operate normally, 5

容内明发200807870 To perform the operation of the fecal visit |, Λ, r, . ^ The operation of the large 10 is performed by the upper differential input pair and the lower differential input pair. The advantage of the singer is that the common mode voltage CM can be allowed to operate effectively from the range of & to %. In today's trend toward power supply for electronic products, this advantage has prompted the operating range of rail-to-rail operation to be effectively utilized with a limited range of power supply relocations. On the other hand, today's electronic products are also being asked to smash the electronic data as much as possible. He said that when the input of the operational amplifier is called and / or vanning changes, the output voltage of the operational amplifier is v. 〇ut will change from the original state to another state in response to this change. The rate of change of V°ut over time is called “sle: rate”. The higher the conversion rate, the faster the operating speed of the op amp (4). However, the conventional rail-to-rail operation amplification shown in ® 1 is specifically designed to have a higher conversion ratio than other types of operational amplifiers. Therefore, it is expected that someone can provide an operational amplifier with a high slew rate. In view of the foregoing, it is an object of the present invention to provide a rail-to-rail operational amplifier having a conversion ratio. According to one aspect of the present invention, an orbital operation amplifier is provided, comprising: an upper differential input pair, a lower differential input pair, a total wheel output stage, an upper side current adjustment circuit, and Side current adjustment circuit 2 200807870 The upper differential input pair is controlled by a -first input voltage and a second input voltage for dividing an upper bias current into a first current and a second current. The lower differential input pair is controlled by the second input voltage of the first input voltage to divide the lower bias current into two third currents and a fourth current. The summing wheel stage sums the first to the fourth currents and generates a wheeling voltage based on the sum. The upper current regulating circuit adjusts the upper bias current based on a comparison between the first and second input voltages. The upper side current adjustment circuit increases the upper side bias current when the first input voltage is less than the second input voltage 'when the absolute value of the difference between the first and the second input voltage increases' . The lower current adjustment circuit adjusts the lower bias current based on a comparison between the first and the second input voltages. When the first input voltage is greater than the second input voltage, when the difference between the first and the second input voltage is greater, the lower current adjustment circuit makes the lower side bias The voltage is increased. The foregoing and other objects, features and advantages of the present invention will become apparent from DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments in accordance with the present invention will be described in detail with reference to the drawings. Figure 2 shows a circuit diagram of the rail-to-operation operational amplifier 20 in accordance with the present invention. The rail-to-rail operational amplifier 20 in accordance with the present invention is different from the conventional operational amplifier 10 in that the slave operating circuit 20 according to the present invention employs an upper current regulating circuit 22 to provide An adjustable upper side of the 200807870 bias current ι ' and a lower side current adjustment circuit 23 is used to provide an adjustable lower bias current ιΑί.

Referring to Fig. 2, the rail-to-rail operational amplifier 2 is provided with an upper differential input pair and a lower differential input pair. The upper differential input pair is composed of first and second-type transistors PQ1 and PQ2, and the lower differential input pair is composed of first and second 电-type transistors PQ1 and PQ2. Therefore, the upper differential input pair and the lower differential input pair together form a complementary differential input stage. Please note that although the p-type electro-crystal system shown in Fig. 2 is implemented by pM〇s electric body, it is also implemented by a pnρ double-carrier transistor. Please note that although the 所示 雷 雷 辨 Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以The source of the first P-type transistor PQ1 and the source of the second p-type transistor pQ2 are coupled to each other. The drain of the first P-type transistor PQ1 and the drain of the second p-type transistor PQ2 are respectively coupled to the summed output stage 21. The first __@ ^ voltage Vinp is applied to the open end of the -P type transistor pQ1, and the second input voltage Vinn is applied to the gate of the second P type transistor pQ2. The fixed upper bias current source IcH is coupled to the upper supply voltage Vh, and is also coupled to the source of the first and second p-type transistors 叩 and PQ2 via the upper current adjustment circuit 22. The upper current regulating circuit is controlled by the first and second input voltages ¥_ and Vinn to generate an adjustable upper bias current w and thus a fixed upper (four) current source Ich: is applied to the upper current with * The reference current of circuit 22 is adjusted. Based on the comparison between the first input electric magic νίηρ and Vinn, the upper current regulating circuit "converts the fixed upper bias current source ICH into an adjustable upper side 8 200807870 bias current ιΑΗ. Subsequently, the adjustable upper side A bias current is applied to the mutually coupled sources of the first and second P-type transistors PQ1 and PQ2.

The source of the N-type transistor NQ1 is coupled to the source of the second n-type transistor PQ2. The drain of the first N-type transistor Nq i and the drain of the second N-type transistor NQ2 are coupled to the summed output stage 2 i, respectively. The first input voltage vinp is applied to the gate of the first N-type transistor NQ1, and the second input pen voltage Vinn is applied to the gate of the second n-type transistor NQ2. The lower bias current source Icl fixed to the φ is coupled to the mutually coupled source of the first and second N-type transistors NQ1 and NQ2 via the lower current adjustment circuit 23, and is also coupled to the lower supply voltage V1. The lower current regulating circuit 23 is controlled by the first and second input voltages Vinp and Vinn to generate an adjustable lower bias current IAL. Therefore, the fixed lower side bias current source Icl acts as the reference current applied to the lower side current adjusting circuit 23. Based on the comparison between the first and second input voltages Vinp and %, the lower current regulating circuit 23 causes the fixed lower bias current source icl to be adjusted to a lower bias current Ial. Subsequently, an adjustable lower bias current iAL is applied to the mutually coupled sources of the first and second N-type transistors NQ1 and NQ2.

Figure 3 shows a detailed circuit diagram of a first example 22a of the overcurrent adjustment circuit 22 in accordance with the present invention. Referring to Fig. 3, P-type transistors 31 and 32 constitute a differential adjustment unit. The source of the P-type transistor 31 is coupled to the source of the p-type transistor 32. A fixed upper bias current source iCH is coupled to the mutually coupled sources of the p-disk bodies 31 and 32. The first input voltage is applied to the gate of the P-type transistor 3 1 and the second input voltage vinn is applied to the gate of the P 9 200807870 type transistor 3 2 . The N-type transistor 34 itself becomes a one-pole body. The gates of the Ν-type electric f 34 are mutually _ _, and are lighter. The drain of the N-type transistor 34, the electric solar body 32 is used to the lower side supply voltage VN type transistors 33 and 35 and /, the voltage should be 1, ^ 电 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日Into a current mirror unit. N-type electro-crystal 骅u — day and day j structure The gate of Hongri Japanese body 33 is coupled with the gate of N-type thunder crystal 骅u. N-type transistor 33 夕 & ^ % 日日体 35 曰 曰 ^ 人 人 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日The crystal 3...$T source is all transferred to the lower side of the supply voltage U-type transistor. The opening of the transistor.37 is lightly coupled with each other. The p-type transistor is reported to be coupled to the poleless pole. More preferably, the transistor of the p-type transistor 36 and the source of the P-type transistor 37 are coupled to the upper supply voltage VH. The drain of the P-type transistor 37 is adjustable. The upper bias current IAH to the upper differential input pair formed by the first and second p-type transistors pQi and PQ2 shown in Fig. 2. The upper current adjustment circuit 22a is based on the first input voltage Vinp and the second input The comparison is performed between the voltages Vinn. First, it is considered that the fixed upper bias current source ICH is divided into two partial currents which respectively flow through the p-type transistors 31 and 32. When the first input voltage Vinp becomes larger, The proportion of the current flowing through the p-type transistor 3 1 gradually becomes smaller, and the proportion of the current flowing through the p-type transistor 32 gradually becomes larger. Conversely, When the second wheel-in voltage gradually becomes larger, the current ratio flowing through the P-type transistor 32 gradually becomes smaller, and the current ratio flowing through the P-type transistor 3 1 gradually becomes larger. Provided by the current mirror unit The mirror function, the current flowing through the P-type transistor 3 1 is transmitted to the drain of the P-type transistor 37 correspondingly to the 10 200807870 example, and is used as the adjustable upper bias current 1AH. Therefore, based on the first input voltage The upper side current adjustment circuit 22a is effective to provide an adjustable upper side bias current ΙΑίΙ compared to the second input voltage vnn. In one embodiment of the invention, the width-to-length ratio of the p-type transistor 3 1 (W) The /L)!^ system is designed to be smaller than the width-to-length ratio (W/L) p32 of the p-type transistor 32, for example (W/L) P31: (W/L) P32 =; h5. Therefore, when the first input voltage When _ is equal to the first input voltage Vinn, the majority of the fixed upper bias current source ICH flows through the P-type transistor 3 2 , and only a small portion flows through the p-type transistor 3 1 . If the first input voltage becomes greater than the second input voltage Vinn, the current ratio flowing through the P-type transistor 3 i is only slightly Reduced, while conversely if a first division input voltage Vi becomes smaller than the second input voltage Vinn, the current flowing through the ratio of the p-type transistor 31 is substantially Increasing degrees.

Note that although the P-type electro-crystalline system shown in Figure 3 is implemented by a pM〇s transistor, it is also implemented by a pnp bipolar transistor. Please note that although the N-type cell system not shown in Figure 3 is implemented by a 〇8 transistor, it is also implemented by an npn bipolar transistor. Fig. 4 is a view showing a thickness, a field, and a road view of the first example 23a of the lower side current adjusting circuit 23 according to the present invention. Referring to Fig. 4, n-type transistors 41 and 42 constitute a differential adjustment unit it. The source of the N Μ transistor 41 is coupled to the source of the N-type transistor 42. The fixed lower transistors 41 and 42 are coupled to each other. The gate side bias current source ICL applied to the N type transistor 41 is coupled to the source of the N type. The first input voltage Vinp is applied and the second input voltage Vinn applies 11 200807870 to the gate of the N-type transistor 42. The P-type transistor 44 itself is coupled into a gate and a poleless coupling, and the seedling is extremely polar. ? The transistor 44, the gate and the * are more coupled to the poles of the N-type electrode body 42. P-type transistor 44 P of the solar body 42, coupled to the upper side supply voltage VH. t% crystals 43 and 45 and the N-type electric current-current mirror unit. P-type transistors 4 - 47 together constitute f, ^ Gate of H ^ 3 and P-type transistor 45

Further, the gate of the '1 type transistor 43 is coupled to the drain and the drain of the N-type transistor 41. ? The type of transistor 4^45 ^ pole W is combined with the upper side supply voltage type transistor "between poles: the gates of the type transistor 47 are coupled to each other. The gates of the N type transistors 46 are coupled to each other, and The source of the drain type 1 transistor 46 and the source of the N type transistor 47 are coupled to the lower side voltage VL. The drain of the N type transistor 47 is supplied. The adjustable lower side bias electric chucking IAL to the lower differential input pair formed by the first and second transistors nqi and NQ2 shown in Fig. 2. The lower side current adjusting circuit 23a is based on the first input voltage and the first The ratio of the two input voltages Vinn is interspersed. First, consider that the fixed lower bias current source ICL is divided into two partial currents, which respectively flow through the 曰-type elders 4 1 and 4 2 . When the input voltage V丨np gradually becomes larger, the proportion of the current flowing through the n-type transistor 41 gradually becomes larger, and the proportion of the current flowing through the n-type transistor 42 gradually becomes smaller. Conversely, when the second input voltage vinn As it gradually becomes larger, the proportion of current flowing through the N-type transistor 42 gradually becomes larger, and the proportion of current flowing through the N-type transistor 41 gradually changes. By means of the mirroring function provided by the current mirror unit, the current flowing through the N-type transistor 41 is transmitted to the drain of the ν-type transistor 47 correspondingly to 12200807870, for use as an adjustable lower-side bias current. Therefore, based on the comparison between the first wheeling voltage Vi" and the first input voltage Vinn, the lower side current adjusting circuit 23a is effective to provide the adjustable lower side bias current iAL. In the embodiment according to the present invention, the aspect ratio of the rN type transistor 41 (W/Lhq is designed to be smaller than the aspect ratio (w/l) n42 of the N type transistor 42, for example, (W/L) N41: (W/L) N42 = 1: 5. Therefore, when the first input voltage vpn _ is dedicated to the input voltage Vinn, most of the fixed lower bias current source ICL flows through the N-type transistor 4 2 And only a small portion flows through the n-type electric βθ body 41. In this case, 'if the first input voltage vNTP becomes greater than the second input voltage Vinn, the proportion of current flowing through the N-type transistor 41 is greatly increased. Increasing, conversely, if the first input voltage becomes smaller than the second input voltage Vinn, the current ratio flowing through the N-type transistor 41 is only slightly reduced. Note that although the P-type electro-crystal system shown in FIG. 4 is composed of pM〇s The transistor is implemented, but it must be implemented by a PnP dual-carrier transistor. Note that although the N-type transistor system shown in Figure 4 is implemented by an NMOS transistor, it also has to pass an npn bipolar transistor. The method of operating the operational amplifier 20 in accordance with the present invention will be described below with reference to Figures 2 and 5. Ding 1, the first input voltage Vinp rises instantaneously (or the input voltage Vinn drops instantaneously), so that the differential voltage DV instantaneously becomes much higher than zero (that is, the stepwise rising change). Therefore, the current regulating circuit from the upper side The adjustable upper bias current IAH generated by 22 becomes smaller, and the lower-side bias current iAL of the 13200807870 full-scale generated from the lower current adjustment circuit 23 becomes larger. The degree to which the current Ial becomes larger is compared with:: by the extent that the voltage current Uh becomes smaller, so that the total bias current formed by the lateral bias is still significantly increased. f, 俺 俺 俺 漭 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' 'Make it quickly change from low to high: the rail line is shown as 51. In contrast, 'since the conventional rail wire'1总 total bias current is fixed, so the conventional implementation The output voltage of the differential amplifier 10 is as slowly as shown by 円52. The dotted line in point 5 is next assumed that at time T3, the first input voltage, the instantaneous drop (or the second input voltage Vinn rises instantaneously), so that the differential voltage becomes less than zero (that is, the ladder) Therefore, the adjustable upper side dust current Iah generated from the upper side current adjusting circuit 22 becomes larger, and the lower side current adjusts the lightning loss (the adjustable lower side bias current AL generated by the vertical path 23)篗 small. As can be clearly seen in Figure 5, since the adjustable upper bias current Iah^ is much larger than the adjustable lower bias voltage & The total bias current formed by the summation is still increasing. In the case where the total bias current is increased, the operation speed of the operation of the pair is increased. Therefore, during the period T3 to T4, the conversion rate of the output voltage v〇ut of the rail-operated alien amplifier 20 is retrieved, so that it rapidly changes from a high level to a low level, as shown by the solid line in FIG. . In contrast, since the conventional rail-to-operator amplifier 1 0 14 200807870 total bias current is fixed, the output voltage V of the conventional rail-operated amplifier is called the point in Figure 5. It descends as slowly as indicated by the dashed line 54. Figure 6 shows a detailed circuit diagram of the second J sub = of the overcurrent adjustment circuit 22 in accordance with the present invention. The second example 22b shown in Fig. 6 is different from Fig. 3: the second example 22a in that the second example 22b is further provided with a fixed upper side current source I 〇 h. As previously described with reference to Figure 5, the adjustable upper bias current AH is reduced during the period from τι to T2. _ " H-rail-to-rail differential amplifier 20 is operated in vL<vCM<(vL + vtn) low-fee, since only the upper differential input pair 1 /, PQ2 is enabled in the complementary input stage Therefore, the operating speed of the rail-to-rail operational amplifier is determined solely by the adjustable upper bias current Uh. In order to avoid the decrease of the upper side bias current Iah, the operation speed is adversely affected. The upper side current adjustment circuit 4 22b is further provided with an upper compensation current source I〇H at the output end for use as an adjustable upper side bias. The lower limit of the voltage current "Η". _ Incidentally, the second example 22b shown in Fig. 6 is further provided with an upper side and a resistor Rsh coupled to the fixed upper bias current source ICH and p. Between the sources of the body 31. Since the finite magnetic potential difference dVH caused by the current flowing through the upper side setting Rsh must be considered, the upper current regulating package 22b starts to increase the operating condition of the adjustable upper bias current Iah. (Vinp + dVH) <Vinn. In other words, the upper side setting resistor Rsh can be appropriately selected to effectively manipulate the operating conditions of the upper side current adjusting circuit 22b. /, Fig. 7 shows the second 15 of the lower side current adjusting circuit according to the present invention. 200807870 The detailed circuit diagram of the example 23b. The second example 23b shown in FIG. 7 is different from the first example 23a shown in FIG. 4 in that the second example 23b is further provided with a fixed lower side auxiliary current source I〇L. As described above in Fig. 5, during the period T3 to T4, the adjustable lower bias current ial becomes smaller. If the rail-to-rail operational amplifier 20 is operated at (Vh-|Vtp|) < In the high range of VCM<VH, since only the lower differential input pair NQ1 and NQ2 are enabled in the complementary input stage, the operation speed of the rail-to-rail operation amplifier φ 20 is separately based on the adjustable lower bias The current IAL is determined. In order to avoid the adverse effect on the operation speed due to the decrease of the adjustable lower bias current Ial, the lower current adjustment circuit 23b is further provided with a fixed lower compensation current source I0L at the output end for use as The lower limit of the lower bias current IAL of the mode is mentioned. The second example 23b shown in FIG. 7 is further provided with a lower side setting resistor RSL, which is coupled to a fixed lower bias current source Icl and n type. Between the sources of the crystal 41. Since the finite magnetic potential difference dVL caused by the current flowing through the lower side setting _ resistance must be considered, the upper current adjusting circuit 22b starts to increase the operating condition of the adjustable lower bias current to become Vinn<;(Vinp + dVL). In other words The lower side setting resistor rs1 can be appropriately selected to effectively manipulate the operating conditions of the lower side current adjusting circuit 23b. Although the present invention has been described by way of illustration of preferred embodiments, it should be understood that the invention is not limited thereto. Rather, the invention is intended to cover various modifications and equivalent arrangements of those skilled in the art. Similar configuration. 16 200807870 [Simple description of the diagram] Figure 1 shows the circuit diagram of a conventional rail-to-rail operational amplifier. Figure 2 shows a circuit diagram of an operational amplifier in accordance with the present invention. Figure 3 is a detailed circuit diagram showing a first example of the overcurrent adjustment circuit in accordance with the present invention. Figure 4 shows a detailed circuit diagram of a first example of a lower current regulating circuit in accordance with the present invention. Figure 5 is a timing diagram showing the operational waveforms of the rail-to-operation operational amplifier in accordance with the present invention. Fig. 6 is a detailed circuit diagram showing a first example of the overcurrent adjusting circuit according to the present invention. - Figure 7 shows a detailed circuit diagram of a lower current regulating circuit according to the present invention. [Major component symbol description] 10 conventional rail-to-rail operational amplifier 11 total output stage 20 in accordance with the present invention, the operational amplifier 21 is added to the total output stage 22, 22a, 22b upper side current adjustment circuit 23, 23a, 23b Side current adjustment circuit 3 1,32, 36, 3 7, 43, 44, 45 P type transistor 33, 34, 35, 41, 42, 46, 47 N type transistor 17 200807870 51, 53 Conversion according to the present invention Rate 52, 54 Conventional conversion rate NQ1, NQ2 Upper differential input pair PQ1, PQ2 Lower differential input pair

Vh upper side supply voltage Vl lower side supply voltage Vinp first input voltage Vinn second input voltage vout fm output voltage DV differential voltage IcH fixed upper bias current. Source ICL fixed lower bias current source I AH adjustable Side bias current Ial Adjustable lower bias current I〇H Upper compensation current source I〇L Lower compensation current source Rsh Upper setting resistor Rsl Lower setting resistor 18

Claims (1)

200807870 X. Patent application scope: 1 · A rail-to-operation operational amplifier, comprising: an upper differential input pair, controlled by a first input voltage and a #1 voltage, for dividing an upper bias current and a round inflow The two differential electric differential input pairs are controlled by the first input voltage and the heng #一-voltage to divide the side bias current two: the wheel current; and the outer two parts The output stage ' is configured to combine the two partial currents and the partial current, and generate an output voltage based on the combination, further characterized by: an upper current adjustment circuit, based on the first and second input voltages Adjusting the upper bias current so that when the voltage of the first voltage is less than the second input voltage, when the absolute value of the difference between the first and the first input voltage is increased, The upper bias current port and the lower side current adjustment circuit adjust the lower bias current based on the comparison between the first and the second input voltage, so that the first input When the voltage is greater than the second input voltage, when the absolute value of the difference between the first and the second input voltage is increased, the lower bias current is increased by ϋ 〇 2. as claimed in the patent scope The rail-to-rail operational amplifier, wherein: when the first input voltage is greater than the second input voltage, when 19 200807870 the absolute value of the difference between the first and the second input voltage increases, The upper current adjustment circuit reduces the upper bias current, and when the first input voltage is less than the second input voltage, and the absolute value of the difference between the first and the second input voltage increases, : The lower side current adjustment circuit reduces the lower side bias current.忒 3. The orbital operational amplifier of claim 1, wherein the upper current adjustment circuit comprises: a differential adjustment unit controlled by the first input voltage and the second: voltage for dividing one The fixed upper bias current source is: - the current - the second current, such that when the first input voltage is less than: the input ink, when the first and the second input voltage are two different absolute When the value is increased, the first current is increased, and a is used to transmit the first current as the upper side current mirror unit bias current. 4. For example, the rail-to-rail operational amplifier of the third application patent scope. The differential adjustment unit includes: a type of transistor having a source, a gate, and a gate is controlled by the fixed upper bias current source, the gate element and the w Μ are controlled, and the immersion is lightly coupled to the current mirror And the *-p-type transistor 'has a source, a gate, a disk, and a pole, and the source is coupled to an upper bias current source of the gate, and the gate 20 200807870 is Controlled by an input voltage, the drain is coupled to a lower side supply voltage, wherein the first P-type transistor has a width to length ratio that is less than a width to length ratio of the second p-type transistor. 5. The rail-to-rail operational amplifier of claim 3, wherein the difference between the first input voltage and the second input voltage is greater than the second input voltage When the absolute value increases, the first current is lowered. 6. The rail-operated operational amplifier of claim 5, wherein: the upper current regulating circuit further comprises: an upper compensation current source for use as a lower limit of the upper bias current. • The rail-to-rail operational amplifier of claim 1, wherein: the lower current adjustment circuit comprises: a differential adjustment unit controlled by the first input voltage and the second input voltage to divide a fixed lower bias current source becomes a third current and a fourth current, such that the difference between the first and second input voltages is greater than the first input voltage is greater than the first input voltage When the absolute value is increased, the third current is increased, and a current mirror unit ' is used to convert the third current as the lower bias current. 21 200807870 8. The rail-to-rail operational amplifier of claim 7, wherein: the differential chirping unit comprises: a first germanium transistor having a source, a gate, and a pole J The source is lightly coupled to the fixed lower bias current source, the idle pole is controlled by the first input voltage, the drain is coupled to the current mirror unit, and the first transistor is a source, a gate, and a / / and a pole 'β source are coupled to the fixed lower bias current source, the idle pole is controlled by the second input voltage, and the drain is coupled to one The side supply voltage, ^ wherein the aspect ratio of the N-type transistor is designed to be smaller than the aspect ratio of the second N-type transistor. 9. The method of claim 7, wherein: the first input voltage is less than the second input voltage, and the difference between the first and the second input voltage is absolute When the value increases, the third current is lowered. 10. The rail-to-rail operational amplifier of claim 9 wherein: the lower current regulating circuit further comprises: a lower side compensation current source for use as a lower limit of the lower bias current. twenty two