TW200807593A - Flip-chip interconnection with a small passivation layer opening - Google Patents

Flip-chip interconnection with a small passivation layer opening Download PDF

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Publication number
TW200807593A
TW200807593A TW096122745A TW96122745A TW200807593A TW 200807593 A TW200807593 A TW 200807593A TW 096122745 A TW096122745 A TW 096122745A TW 96122745 A TW96122745 A TW 96122745A TW 200807593 A TW200807593 A TW 200807593A
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TW
Taiwan
Prior art keywords
contact
bump
coupling
electrical
passivation layer
Prior art date
Application number
TW096122745A
Other languages
English (en)
Inventor
Wojtek Sudol
Original Assignee
Koninkl Philips Electronics Nv
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Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Publication of TW200807593A publication Critical patent/TW200807593A/zh

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    • A61B8/44—Constructional features of the ultrasonic, sonic or infrasonic diagnostic device
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  • Wire Bonding (AREA)

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200807593 九、發明說明： 【發明所屬之技術領域】 本系統係關於使用具有-相對小的鈍化層開口之曰 ί灵日白 矢員型之電互連之一互連方法及器件。 【先前技術】 積體電路（ic)技術之當前狀態係尺寸不斷減小而複雜度 不斷增加。隨著組件之密度增加，由於物理互連佔有有^ 表面積之顯著邛为而減低此區域中定位電路之能力，電 ’耦接組件之系統變得非常關鍵。 以口-電互連技術，纟中該互連之一部分係藉由一接觸 凸塊形成，而該互連之另一部分係藉由一接觸接點或表面 形成。在製造程序期間，該凸塊與接點相互接觸以形成電 互連。以弓I用方式整體併人本文之美國專利第6,〇15,652號 揭示一種此一互連系統之類型，該互連系統稱為關於安裝 於一基板上之1C之”覆晶接合"。此典型互連系統減少與其 藝他電互連系統相關聯之一些問題，但仍然佔用很多有效的 表面積’否則遠4有效表面積可由電組件加以利用。當電 互連係直接作用於一積體電路（例如特定應用積體電路 (ASIC))土時，此問題係更加嚴重。 以引用方式整體併入本文中之PCT專利申請案w〇 2004/052209揭示一系統，該系統將一 ASIC電耦接至複數 個4子元件用於形成一小型化的轉換器陣列。在所示系統 中，該凸塊係電耦接至聲學元件或ASIC之一者，而該接點 係電耦接至該聲學元件或ASIC之另一者。此系統實現一小 121833.doc 200807593 電封裝’其（例如）可形成 ,ν Λ 或用以創建可用於經食管、腹腔鏡 式以及心内檢查之一超聲 。 ^ 轉換裔。但是，由於此等產品 採取直接在該聲學元件下 心早兀電路之一間距匹配，所 以需要進一步減低該間距。適去 ^ 週田才呆作所需之當前混合信號 ASIC程序與電壓仍然限制該聲 〆耳予7G件與控制電路之進一步 縮減。例如，對於使用定位 、185 間距陣列上之柱形 凸塊之一覆晶互連系統，由 丄 %此等凸塊，大約40%之該
A SIC之區域係無法用於電路。 在已知以及實踐程序中’例如柱形凸塊及電鍍凸塊，該 等凸塊係實質上透過該純化層開σ定位於該等接點上，血 型地，該凸塊很少或沒有重疊在該純化層i。換言之，在 先前^統中’該凸塊之涵蓋表面之大小係轉接近該接觸 接點之大小。並在先前系統中，餘形凸塊與接觸接點之 間之此較大之互連以及電純該柱形凸塊與接觸接點之限 制係主要導致ASIC之不可用部分之主要因素。 【發明内容】 本系統之一目的係克服先前技術中之缺點及/或進行改 良。本系統之一目的係產生一高凸塊之同時，最小化該 ASIC實際佔用面積（real estate)之消耗。 ^ 依據本系統，一覆晶電耦接係形成於第一與第二電組件 之間。該耦接包含一凸塊以及一接觸接點。該第一電組件 包含一接觸接點，其係電編接至該第一電組件·，以及 化層’其覆蓋該第一電組件與該接觸接點。該鈍化層係配 置成具有定位於該接觸接點上之一開口。— Λ换在丄 。現1糸加以定 121833.doc 200807593
位以覆蓋該開口並實質上覆蓋該鈍化層。該凸塊係形成用 以與該接觸接點電接觸。該凸塊係配置成用以在覆日輛接 程序期間㈣該等第-與第二電組件。在—具體實曰施例 中，該開口之一表面積對藉由該凸塊覆蓋之該鈍化層之— 表面積之一比率係位於5·至0或$至3(?之範圍内。具 體實施例巾’㈣-電組件包含—凸塊下金屬化層，該^ 塊下金屬化層係組態成用以將該接觸接點電麵接至該凸 塊。該凸塊可係配置為在—電鍍程序期間沈積之複數個 層。在—具體實施例中，該第一電组件係一八狀及/或該 第二電組件係一轉換器陣列。 Λ 本系統亦包含-種用於在第一與第二電組件（間形成_ 覆晶電耦接之方法’其中該第一電組件係藉由一鈍化層覆 蓋。該方法包含以下動作：在該第—電組件之—接觸接點 上之該純化層中形成_開口 ；沈積—凸塊，使其覆蓋該開 口並實質上覆蓋該純化層；以及將該凸塊電輕接至該接觸 接點。 在沈積該凸塊之動作之前’該方法可包含沈積與該接觸 接點電接觸之-凸塊下金屬化層之動作。在此具體實_ 中，將該凸塊電耦接至該接觸接點之動作包含將該凸塊電 搞接至該凸塊下金屬化層之動作。未藉由該凸塊覆蓋之該 凸塊下金屬化層之部分可移除。該凸塊下金屬化層可加以 濺鍍沈積。該凸塊可藉由電鍍該凸塊之複數個層來加以沈 積直至該凸塊高度係位於7〇至1〇〇 um之範圍内。 該第二電組件可係覆晶輕接至該凸塊。在該覆晶輕接之 121833.doc 200807593 以從該第二電組件形 動作之後，該第二電組件可切成方格 成複數個元件。 在相同或另一具體實施例中，該第一電組件可係一聲學 兀件及/或該第二電組件可係— ASIC。㈣接可係呈現於 小於150 um之間距陣列中之複數個電耦接之一者。 【實施方式】
以下係說明性具體實施例之說明，其將結合以下圖式說 明以上表述以及進一步之特徵及優點。在以下說明中，目 的係說明而非限制，提出之諸如架構、介面、技術等之特 定、、田節係用於5兒明。但是’熟悉此項技術人士應明白，背 離此等細節之其他具體實施例仍應理解為屬於隨附申請項 之範疇。而且，為清晰起見，省略眾所周知之器件、電路 以及方法之詳細說明’以便不模糊本系統之說明。此外， 應清楚瞭解，所包含之圖式係用於說明目的而非表示本系 統之範疇。在該等附屬圖與說明中，相同參考數字用於指 定類似的元件。 圖員示依據本系統之一具體實施例之製備用於一覆晶 互連之一積體電路（例如ASIC 110)之一說明性俯視圖1〇〇。 該ASIC 110係由一鈍化層13〇覆蓋，該鈍化層13〇絕緣並保 護該ASIC 110之一底部層。與先前系統相比，該純化層 130係具有一較小之開口 12〇。該俯視圖1〇〇包含兩個覆蓋 元件之一指示，例如聲學元件18〇，其依據本系統經由開 口 120以及一凸塊（圖.丨中未說明）耦接至該ASIC u〇。 圖2顯示依據本系統之一具體實施例之一覆晶互連系統 12I833.doc 200807593 200之一說明性斷面。在此具體實施例中，-高方位凸塊 240顯示為—柱形 ^ 一舞與_ /塊形式，在製造期間，其係電耦接至 每學凡件之—解匹配層表面（圖中未顯示）。說明性地， 該凸塊240可係任何形式’其包含球形及/或柱形。該聲學 7G件可係種I生可用於—超聲波轉換器應用中之超聲波 旎發射之一聲學元件之類型。如上述，該凸塊240說明性
地係一高方位凸塊’心解決電偏至A.SIC 21〇之元件之 製造及製備中之容限。 、，圖4顯示依據本系統之-說明性元件，例如一聲學元件 平板480，其可係♦馬接至一電組件，例如趟。說明 性地，對於其中該ASIC 410係覆晶耦接至一聲學陣列之應 用’需要一相對較大之凸塊高度，例如70至100 um。此等 類型之二維陣列（例如圖4中所示）典型地具有非常多的（例 如，2,000至1〇5〇00)聲學元件48〇(轉換器材料），該等聲學 儿件透過該凸塊直接定位並覆晶接合至該ASIC 41〇上。該 等凸塊至該聲學陣列之接合可藉由任何適當的接合程序獲 仟，包含利用應用於該等凸塊或該聲學陣列之一接觸表面 之一導電黏合劑，以及超聲波柱形凸塊接合等。 该ASIC 410之實體尺寸典型地大於聲學材料之平板之尺 寸。在將該平板覆晶接合至該ASIC 41〇後，可應用一側填 滿490來相對該ASIC 410穩定該平板，其共同地成為一裝 配件。該未充滿孔型有助於保護該等凸塊免受環境狀況之 影響，向該裝配件提供額外的機械強度，可充當一散熱座 來’助该ASIC之活動組件驅‘散熱量.，以及可幫助補償在該 121833.doc -10« 200807593 等耳予元件480與該ASIC 4 10之間的任何熱膨脹差異。 ^例如，使用一切割機（例如，細粒金剛石錯）切割 〇平板（例如，苓見切割488)，以將該平板分離成個別的聲 學元件480,該等聲學元件在覆晶接合程序期間及此後定 位於各凸塊上（為清晰起見，凸塊未顯示於圖4中）。應很容 易瞭解，该等聲學元件48〇可係任何類型及組態，包含有 助於諸如可用於3_D超聲波成像應用及/或矩陣轉換器組態
之3維（3-D)成像之一組態。 電耦接該ASIC 410至該等聲學元件48〇之難度係藉由一 所需切割公差所混合。分離該等個別聲學元件480之該等 切』488必須足夠深，以便可將該平板分離成個別的聲學 元件480。但是，切割過深將導致一風險，其會損壞底部 ASIC 410(例如，該切割可通過該ASI(：表面積）。存在數種 組件，其可獲得一較大切割深度公差之需求，同時可導致 一較大凸塊高度（例如，7〇至1〇〇 um)之需求。首先，該平 板之厚度存在變化。典型地，該平板係三個或多個材料之 一層板，即一解匹配層486(例如，碳化鎢）、一壓電晶體 484(其係轉發器）以及一匹配層482(例如，石墨）。該等三 個層壓材料（例如，各具有不同的物理屬性）可導致平板非 較佳之平整。 此外，進行如此多之切割（例如，數千次）可導致該切割 機之鋸條磨損。因Λ，即使對—給定深度之㈣，由於鑛 條磨損，最後之切割與初始之切割具有不同之深度，所以 所做之該等切割可典型地解释為對於較後之切割係較淺。 121833.doc -11 · 200807593 V ’匕含在先前數個分離程序中接合（例如，層壓）在 起=多個零件之一結構具有累積公差之一問題。例如， 人旱度之公差加上該等層之乎直度之一公差再加上接 —旱度之公差導致一大的累積公差。 以上列出之所有組件在該平板與ASIC之間合計至一相 對大（例如，70至100 um)之間隙之需要。針對一大間隙之 此而求可轉換為一對應的大的凸塊高度。 _ 圖3顯不依據本系統之一具體實施例之說明性覆晶互連 系、在300之一詳細的斷面區域。該覆晶互連系統300包含一 電組件，例如— ASIC 3 10以及一凸塊340。該ASIC 3 10具 有接觸接點315，例如由一鈍化層33〇(例如，氮化矽層）覆 盍之鋁接點。依據本系統之具體實施例，與先前系統相 比’形成之該等接點315係較小，例如，直徑為5至3〇 ·。 使用 適¥的程序將透過該鈍化層330之一開口 320製作為 在該等接觸接點315之上部並透過該等接觸接點315，例士 • 藉由一電子平版印刷術钱刻程序，電漿回濺（back sputter) 等。在該鈍化層之移除期間或在一後續程序期間，從該等 接觸接點3 1 5移除氧化物（例如氧化銘），以確保下一形成之 與凸塊下金屬化層（UBM)35〇2良好的電接觸。該U]BM 350可形成於具有不同冶金學品質（頂部具有鍍金之鈦）之多 個層内。該UBM 350典型地重疊該鈍化層330，以確保至 該等接觸接點315之良好的導電黏合（例如，電鍍）。該 UBM 350亦保濩該asIC(例如，密封該接觸接點）免受環境 狀況的影響’例如可在後續步驟中使用之氧化及化學程 121833.doc •12- 200807593 序。該UBM 350可藉由任何適當的程序形成，例如在該 ASIC 310之頂部表面上之濺鍍沈積、電解電鍍、光沈積 然後’該凸塊340形成於透過鈍化層33〇之開口 32〇上。 該凸塊340實質上覆蓋該鈍化層33〇之一部分。典型的先前 技術之凸塊只覆蓋該鈍化層之非常小之一部分（例如， <3%)，如上述，該凸塊與該底部接爾接點具有典型地同樣 的大小。在先前系統中，該凸塊至該接觸接點之大小定制 係減少該ASIC之浪費之實際佔用面積之一方法。在本系統 中，在該鈍化層330上之該凸塊34〇之實質覆蓋在ASIC31〇 之實際佔用面積之使用中獲得更好之改良。例如，互連之 本系統適於應用於15〇 um及更小之細密間距陣列中。如本 文使用，術語在該鈍化層上之該凸塊之實質覆蓋意味該凸 塊之10%與95%之間（1〇%<覆蓋<95%)之涵蓋表面覆蓋於該 鈍化層。在一具體實施例中，超過50%(例如，70%至95%) 之遠凸塊之涵蓋表面可覆蓋該鈍化層，而該接觸接點之大 小仍然維持相對小，其導致一潛在改良之電路密度。 該凸塊340可使用任何製造程序來加以製造，例如電 鍍加工、成形、導線接合3 10、電子平版印刷術等。在 一具體實施例中，該凸塊340在一電鍍程序期間形成。該 電鍍程序含創建一電鍍遮罩，該電鍍遮罩定義該ASIC 310 之表面上加以電鍍之區域。此電鍍遮罩亦定義該凸塊34〇 之涵蓋表面。 在一特定具體實施例中，其可能需要使用多個、分離的 121833.doc -13- 200807593 電鍍程序來形成凸塊，以致能所需的特徵解析度以及凸塊 高度。而且，如果-電鐘遮罩使用過深，該電鏡狀況（例 如，化學、溫度以及時間）可導致該電鍍遮罩損壞。一多 步電鍍程序可導致如圖3中說明性說明之一金字拔形狀之 凸塊340。在此具體實施例中，可針對各電鍍步驟使用一 不同的遮罩。該凸塊340之連續電鍍層級342、344、3钧之 每個之大小可係較小，以致能該等電鍍遮罩之定位。一同 馨 樣大小之遮罩可導致正確定位該遮罩之問題，其將導致一 未受控制之該凸塊之形狀。該凸塊34〇可由任何所需之冶 金形成，例如鎳及/或鎳組成物3 60。 完成之凸塊340(例如）在兩或多個電鑛程序之後，其高 度可係位於50至120 um之範圍内（如100 ^^高），並具有5〇 至80 um之範圍内之涵蓋表面（例如6〇 um之涵蓋表面在 該凸塊340完成後，除了定位於該凸塊34〇下面之部分，該 UBM 350可藉由任何適當的程序移除，例如藉由一化學蝕 • 刻程序。此後，該凸塊34〇可藉由任何適當程序（例如藉由 一無電極鍍金程序（無電極））加以電鍍，其導致該凸塊Ιο 上之一電鍍層370(例如，金）。 有利地係，依據本系統之互連系統消耗較少之用於接觸 接點之ASIC區域，並可導致更多之可用於電路（例如，添 加之特徵）之該ASIC之實際佔用面積或與現存系統相比可 致月b更小的間距設計。 當然，應瞭解以上具體實施例或程序之任一者可依據 本系統與一或多個其他具體實施例或程.序相結合來提供進 121833.doc -14- 200807593 一步之改良。 最後，以上說明係意欲為本系統之僅說明性而不應解釋 為限制隨附專利申請範圍至任何特定之具體實施例或具體 實施例之群組。因此，雖然本系統已參考其特定範例性具 體實施例（例如，ASIC、聲學元件等）以特定細節加以說 明，亦應瞭解在不背離以下申請專利範圍所提出之本系统 之廣泛及所期.望.之精.神及範_之情況下，熟悉此項技術人 士可作出夕種修改及可替換具體實施例。因此，說明及等 圖式係^為δ兒明性方式而非意欲限制隨附申請專利範圍 之範_。 在說明該等隨附申請專利範圍時，應瞭解： &)單詞"包含"並不排除―給^請求項中列出之此等元件 或動作之外之其他元件或動作之存在。 ，件前之單詞"一，，或”一個"不排除複數個此 存在。 勾明求項中任何參考符號不限制其範疇； d)數個”構件”可益；— 體或軟體加以表1由貝施之結構或功能之相同項目或硬 接1)任何揭示之元件可包含硬體部分（例如，包含離散之及 合； 刀（例如，電腦程式設計）以及其任何組 f) 硬體部分可白人半 g) 任何揭— 類比與數位部分之-者或兩者； 壬订揭不之器件1八 之部分σ刀σ、、且口在一起或分離成其他 除非另外特別說明；以及 121833.doc -15- 200807593 h)未意欲要求動作或步驟之特定壙序 【圖式簡單說明】 除非明確指示。 中： 已以範例方式並參考附圖進一步詳細說明本發
圖1顯不依據本车綠之_ θ μΑ + *m款㈣貫施例之製剌於一覆晶 互連之一 ASIC之一說明性俯視圖； 圖2顯示依據本系統之一具體實 說明性斷面； •施例之一覆晶互·連之一 圖3顯示依據本系統之一具體實施例之圖？中所示之說明 性覆晶互連系統之一詳鈿的斷面區域；以及 圖4顯示依據本系統之可耦接至一電組件之一說明性元 件（例如一聲學元件平板）。 【主要元件符號說明】
100 覆晶電柄接 110 第一電組件/ASIC 120 開口 130 純化層 180 第二電組件 200 覆晶電耦接 210 第一電組件/ASIC 220 開口 230 純化層 240 凸塊 300 覆晶電搞接 121833.doc •16- 200807593
310 第一電組件/ASIC 315 接觸接點 320 開口 330 鈍化層 340 凸塊 342 電鍍層級 344 電鍍層級 346 電鍍層級 350 凸塊下金屬化層 360 鎳及/或鎳組成物 370 電鍍層 410 第一電組件/ASJC 480 第二電組件 482 匹配層 484 .壓電晶體 486 解匹配層 490 側填滿 121833.doc -17-

Claims (1)

  1. 200807593 十、申請專利範圍： 1· 一種在第一與第二電組件（11〇、18〇 ; 410、480)之間的 覆晶電耦接（100、200、300)，該耦接（1〇〇、200、300) 包含： 該第一電組件（110、210、310、410)包含： 一接觸接點（315)，其電耦接至該第一電組件（no、 210、310、410);以及 一鈍化層（130、230、330)，其覆蓋該第一電組件 (110、210、310、410)以及該接觸接點（315)，其中該鈍 化層（130、230、33 0)係組態成用以具有定位於該接觸接 點（3 15)上之一開口（120、220、320);以及 一凸塊（240、340)，其覆蓋該開口（120、220、320)以 及實質上覆蓋該鈍化層（130、230、330)，該凸塊（240、 340)係與該接觸接點（3 15)電接觸並係組態成用以在覆晶 耦接期間耦接該等第一與第二電組件（11〇、180 ; 410、 480) 〇 2·如請求項1之耦接（100、200、300)，其中該開口（120、 220、320)之表面積對由該凸塊（240、340)覆蓋之該鈍化 層（130、230、330)之表面積之比率係位於5%至85%之範 圍内。 3·如請求項1之耦接（1〇〇、200、300)，其中該開口（120、 220、320)之表面積對藉由該凸塊（240、340)覆蓋之該鈍 化層（130、230、33 0)之表面積之比率係位於5%至30%之 範圍内。 121833.doc 200807593 4·如請求項1之耦接（100、200、300)，其中與開口（120、 220、320)相比’該凸塊（240、340)覆蓋該鈍化層（13〇、 230、330)之一較大表面積。 5·如請求項1之耦接（100、200、300)，其中該第一電組件 (110、210、310、410)包含一凸塊下金屬化層（35〇)，該 凸塊下金屬化層係組態成用以將該接觸接點（3丨5)電耦接 至該凸塊（240、340)。 6·如請求項1之耦接（100、200、3 00)，其中該凸塊（240、 340)係組態成為在一電鑛程序期間沈積之複數個層 (342 ' 344、346)。 7·如請求項1之耦接（1〇〇、200、300)，其中該第一電組件 (110、210、310、410)係一 ASIC。 8. 如請求項1之耦接（100、200、300)，其中該第二電組件 (180、480)係一轉換器。 9. 一種在第一與第二電组件（11〇、18〇 ; 41〇、480)之間形 成一覆晶電耦接（100、200、300)之方法，其中該第一電 組件（110、210、310、4 10)係藉由一鈍化層（130、230、 33 0)覆蓋，該方法包含以下動作： 在忒苐一電組件（11〇、210、310、410)之一接觸接點 (315)上之該鈍化層（13〇、23〇、33〇)中形成一開口（12〇、 220、320); 沈積一凸塊（240、340)，使其覆蓋該開口（120、220、 3 20)並實質上覆羞該鈍化層（13〇 、230、330);以及 將該凸塊（240、340)電輪接·，至該接觸接點（315)。 121833.doc -2- 200807593 ι〇·如睛求項9之方法，其中在沈積該凸塊（240、340)之動作 之岫，該方法包含沈積一凸塊下金屬化層（3^〇)與該接觸 接點（315)電接觸之動作；以及其中將該凸塊（24〇、34〇) 電祸接至該接觸接點（3 1 5)之動作包含將該凸塊（240、 34〇)電輕接至該凸塊下金屬化層（35〇)。 11.如明求項1〇之方法’其包含移除未由該凸塊、mo) 覆盍之該凸塊下金屬化層（35 0)之部分。 12·如請求項1〇之方法，其中沈積該凸塊下金屬化層（35〇)之 動作包含濺鍍沈積該凸塊下金屬化層（35〇)之動作。 13·如明求項9之方法，其中沈積該凸塊（24〇、34〇)之動作包 έ電鑛遠凸塊（240、340)之複數個層（342、344、346)直 到凸塊咼度係位於7〇至1 〇〇unl之範圍内之動作。 14·如请求項9之方法，其中沈積該凸塊（24〇、34〇)之動作包 含沈積該凸塊（240、340)以重疊5%至30%之範圍内之該 開口（120、220、320)對該鈍化層（130、230、330)之表 面積之一比率之動作。 15·如凊求項9之方法，其包含將該凸塊（24〇、34〇)覆晶耦接 至該第二電組件（18〇、48〇)之動作。 1 6·如巧求項15之方法，其包含在覆晶耦接動作後將該第二 電組件（180、480)切成方塊之動作。 17·如印求項15之方法，其中該第二電組件（18〇、48〇)係一 聲學元件。 18·如清求項15之方法，其中覆晶耦接之動作係在小 於 150 um 之間距陣列内成形之複數個電耦接之一者。 121833.doc 200807593 胃求貝18之方法，其包含覆晶輕接動作後將該第二電 、，且件（180、480)切成方塊以從該第二電組件（刚、_) 形成複數個聲學元件（480)之動作。 20.如請求項15之方法，其中該第一電組件〇1〇、21〇、 310、410)係一ASIC’而該第二電組件〇8〇、48〇)係一聲 學元件。
    121833.doc
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