TW200805243A - Shift register - Google Patents

Abstract

A shift register comprises a couple of stage wherein the nth stage comprises first, second and third level control unit and first and second driving unit and n is a nature number. The first and second level control units provide first clock signal and first voltage to an output end respectively. The first driving unit and level control unit are connected at a first node and the voltage on which is first control signal. The first driving unit turns on and turns off the first level control unit in response to an input signal, first and second control signals. The second driving unit turns on and off the second level control unit in response to the first control signal. The third level control unit provides the first voltage to the output end in response to the front edge of the first control signal of the n+20th stage.

Description

200805243rw3165PA, IX. Description of the Invention: [Technical Field] The present invention relates to a Shift Register, and in particular to a shift of the n+1th stage or the n+2th stage The specific voltage signal of the register unit controls the shift register of the n-th stage shift register unit operation. [Prior Art]

In the current era of rapid technological development, liquid crystal displays have been widely used in electronic display products such as televisions, computer screens, pen computers, mobile phones or personal digital assistants. The liquid crystal display system includes a material Ddver, a scan driver (9), and a liquid crystal display panel, wherein the liquid crystal display panel has a pixel array, and the broom = actuator is used to sequentially open the corresponding pixel in the pixel array. Column, in order to sweep the output of the halogen data to the cat, to display the image to be displayed. 0 Today's technology is more to shift register (Shift (four) called to achieve the corresponding sequence in the pixel array扫 昼 的 的 的 。 。 。 。 。 。 。 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于 由于The performance and liquid crystal display quality is one of the directions that the industry is working for. One"

"turning to zero rW3165PA 200805243 [Description of the Invention] The present invention relates to a shift register (Shift R 邙 wherein each stage of the shift register unit has the advantages of long service life, output signal " The advantage of the quality of the liquid crystal display of the shift register is better. [,,, according to the present invention, a shift register is provided, which has a connected shift register unit, wherein the first stage shift Transmitting;, (3) output signal, which is the input signal of the !1+1 shift register unit = the natural number. The nth shift register unit includes the first, second, and "#1 The level control unit and the first and second control units. The first level control is used to provide the first timing signal to the output end. The first driving unit and the input end of the 70th quasi control unit are coupled to the first node. , the first node voltage = the first control signal. The first axis unit (4) should be used to sew the first level control unit before the wheel signal, and used for the second control signal, the level is higher than the first The position of the three-control dragon is on time - the level control - early το. The second level control unit is configured to provide the first voltage to the output. The second driving unit is configured to close the second level control unit in response to the leading edge of the first control signal, and align the second solution unit after the first (four) signal. The third level control unit is configured to respond to the first voltage of the first control signal of the 3 n+2 stage shift register unit to the output end. According to the present invention, another shift register is provided, which has a plurality of shift register units connected in series with each other, and the n-th shift of the towel is temporarily stored in the unit output round-out signal, which is the n+1th level. Shift register signal to the scratchpad unit,

TW3165PA 200805243 n is a natural number. The nth stage shift register unit comprises: a three-position quasi-control unit, and the first and second driving units, the first one and the second control unit respectively for providing the first timing signal and the first: the first first level control unit Turn in _ at the first point, the voltage is - the first control signal. The first-drive unit uses = in response to the input signal, the first-level control solution, the work, the early% of the driver's drive unit is used to respond to the first control signal before the second-level quasi-control solution If p-level control unit is to be turned on at the trailing edge of the (-)th signal. The third level control unit is configured to respond to the first control signal of the n+1th stage shift register unit to provide the low voltage level of the first timing signal to the wheel output. According to the present invention, a shift register is provided, which has a plurality of shift register units connected in series with each other, wherein the nth stage shift register unit outputs an output signal, which is the n+1th shift. The input signal of the memory unit, η is a natural number. The nth stage shift register unit includes first and second level control units and first and second driving units. The first and second level control units are respectively configured to provide the first timing signal and the first voltage to the output. The first driving unit and the input end of the first level control unit are coupled to the first node, and the voltage is the first control signal. The first driving unit is configured to turn on the first level control unit in response to the leading edge of the input signal, and to close the first level control unit in response to the leading edge of the first control signal of the n+2th stage shift register unit . The second driving unit is configured to close the second level control unit in response to the leading edge of the first control signal, and respond to the first control signal

:W3165PA 200805243 • The edge is used to turn on the second level control unit. According to the present invention, another shift register is provided, which has a plurality of shift register units connected in series with each other, wherein the output signal outputted by the nth stage shift register unit is the n+1th shift. The input signal 'η of the register unit is a natural number. The nth stage shift register unit includes first and second level control units and first and second driving units. The first and second level control units are respectively configured to provide the first timing signal and the first voltage to the output. The first driving unit and the input end of the first level control unit are coupled to the first node, and the voltage is the first control signal. The first driving unit is configured to respond to the input of the §fl5 tiger leading edge first level control early element ' and is used to respond to the driving edge of the first control signal of the n+1th stage shift register unit (Triggering Edge) To close the first level control unit. The second driving unit is configured to turn off the second level control unit in response to the leading edge of the first control signal, and turn on the two level control unit 0 in response to the trailing edge of the first control signal to make the above content of the present invention more obvious. It is to be noted that a preferred embodiment is described below in detail with reference to the accompanying drawings, and is described in detail below: [Embodiment] The first embodiment of the shift register of the present embodiment has m levels equal and connected in series with each other. The bit register unit, the output signal outputted by the shift register unit of each stage is the round signal of the lower stage shift register unit. The shift register is applied, for example, to a Scan Driver of a liquid crystal display.

rW3165PA 200805243 It is used to sequentially rotate out the signal. _ Signal system is turned to LCD display =,, _ News Start liquid crystal display + by + liquid in the day display panel to write to each book. m : m 昼 昼 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The nth unit of the embodiment, the first drive: the level unit includes a first level control and a third level (four) unit. The first phase 2 system early 70, the second driving unit sequence signal to the output terminal unit is used to provide the first time into the Wei Wei u 1 moving early 70 and the first level control unit of the input 1 π temple point, which The voltage is the first control signal. The first drive is ahead of the front of the wheel signal (Fr_Edge). The first position = the level of the second control signal is higher than the third control signal = bit material_first-stitch unit. The first quasi-tanning unit is used to provide the first voltage to the output. The second driving unit is configured to return to the first level control unit by closing the second position register, the single unit 70, and responding to the first control signal after the first control signal is turned on. . The third level control unit is configured to provide the first voltage to the output end in response to the leading edge of the fourth (fourth) signal of the first stage shift temporary storage unit. n is a natural number. Next, a plurality of implementation structures will be described in detail for the operation of the n-th stage shift register unit. First Embodiment FIG. 1 is a block diagram showing a shift register in accordance with a first embodiment of the first embodiment of the present invention. The shift register 1 includes m shift register units connected in series to each other, for example

200805243TW3165PA • Has an equal structure. In this embodiment, the shift register units S(1) to S(m) include an input terminal, an output terminal out, a control terminal RT, a node P1, a timing terminal c, and a timing terminal CB. The shift register unit s(1)~s(m) causes the output terminal OUT to output the output signals v〇(l)~Vo according to the signals of the input terminal IN, the control terminal RT, the timing terminal c and the timing terminal cb. (m). The input terminal IN of the shift register unit S(1) receives the start signal STV, and the input terminals of the shift register unit s(2)~s(m) receive the previous stage shift register sequentially. Output signal outputted by the output terminal OUT • ν〇(1)~Vo(ml) 〇 Shift timing signal received by any two adjacent timing terminals c in the temporary storage unit S(l)~S(m) The enabling time is staggered from each other, and the enabling time of the sequence signal received by the timing terminal CB is also shifted from each other, and the timing end CB and the n+1th shift of the nth stage shift register unit S(n) are shifted. The enable time of the timing signals received by the timing terminal C of the bit register unit s(n+l) is also shifted from each other. In this embodiment, the timing terminals C and CB of the odd-numbered shift register units in the shift register units S(1) to s(m) receive the timing signals CLK and CLKB', respectively. The timing terminals c and CB of the stage shift register unit receive the timing signals CLKB and CLK, respectively, as an example. In this embodiment, the enable time of the timing signal CLKB and the enable time of the timing signal CLK are, for example, staggered (in the present embodiment, the timing signal CLKB and the timing signal CLK are inverted signals). The control terminal RT of the shift register unit S(1)~S(m_2) receives the voltage signal of the P1 node of the shift register unit S(3)~S(m) as the control signal Vcl(3), respectively. ) ~Vcl(m). Next, the shift register unit s(l)~S(m) - Γ.. -- -- -- ... _ 11 2008〇ϋ3, 3na the nth stage shift register unit S(n As an example, a plurality of circuit embodiments of the shift register unit S(n) of the present embodiment will be described, and n is a natural number. Please refer to the figure of the second figure, which is a soldering circuit diagram of the circuit-input method of the shift register unit g(n) of Fig. 1. The shift temporary storage crying unit S(n) of the present embodiment includes drive units 202a, 202b and level control units 204a, 204b, and 204c. The driving unit 202a includes transistors ΤΙ, T3 and T8, and the driving unit 202b includes transistors T4 and T5, and the level control units 204a, 204b and 204c respectively include transistors T2, T7 and T6. In the present embodiment, an example in which the transistors T1 to T8 are N-type thin film transistors (TFTs) will be described. The gate 1 (6) of the transistor T6 of the level control unit 204c is coupled to the output terminal OUT, and the gate receives the control signal Vcl of the n+2th stage shift register unit S(n+2). (n+2), the source receives the voltage VSS. The level of the voltage VSS is, for example, equal to the low voltage level of the shift register ι00. The transistor T6 is configured to provide a voltage level VSS to the output terminal OUT in response to the leading edge of the control signal vcl(n+2), so that the output signal V〇(n) is equal to the voltage VSS. In the present embodiment, the leading edge of the control signal vci(n+2) is, for example, a rising edge (Rising Edge), the drain receiving timing signal CLK of the transistor T2 of the level control unit 2〇4a, and the source of the gate and the transistor Τ1. The drain of the transistor Τ3 is coupled to the node P1 to receive the control signal Vcl(n), and the source is coupled to the output terminal OUT. The transistor T2 is used to provide a high voltage level of the timing signal clk to the output terminal OUT 〇 12 - a '- t when turned on.

t · rW3165PA 200805243

The drain receiving voltage vdd of the transistor T i of the driving unit 2 0 2 a is received, and the output signal ν〇(η-ι) of the first and second shift register registers is outputted to the source signal ν〇(η-ι) Node P1. The level of the voltage vdd is, for example, the high voltage level of the shift register. The transistor is used to conduct the transistor T2 in response to the leading edge of the output signal VcXn-D to output the signal V. (8) is equal to the voltage VSS. In the present embodiment, the output signal (4) is called the rising edge. The secret of transistor T3 is pure to node ρι, the gate receives timing signal CLKB, and the source receives voltage v〇(lM). The transistor τ3 is used to turn off the transistor 回应2 in response to the rising edge of the timing signal CLKB. The gate of the transistor Τ8 is coupled to the node ρ′′ and the gate is coupled to the node ρ2 to receive the source receiving voltage vss of the control signal Vc2(n). The transistor D is used to provide a voltage vs. node to the rising edge of the control nickname Vc2(n). The gate of the transistor 位 of the level control unit 204b is coupled to the output terminal OUT, and the gate of the gate and the source of the transistor T4 and the diode of the transistor T5 are connected to the node Ρ2 to receive the control signal vC2(n). ), the source receives the voltage VSS. The transistor 7 is used to provide a voltage vss to the output terminal OUT when turned on. The drain and gate of the transistor T4 of the driving unit 202b are coupled to each other to receive the voltage VDD, and the source is coupled to the node P2. The transistor T4 is used to continuously conduct the transistor T7 such that the output signal v 〇 (n) is equal to the voltage VSS. The drain of the transistor T5 is lightly connected to the node P2, and the gate receives the control signal Vcl(n) ' source receiving voltage VSS. The transistor T5 is used to turn off the transistor T7 in response to the leading edge of the control signal Vcl(n). The leading edge of the control signal Vcl(n) is, for example, a rising edge. In the present embodiment, the length and width of the transistor T5 13 200805243

TW3165PA

• The ratio (Width/Length) is, for example, larger than the aspect ratio of the transistor T4. Thus, when the transistor T5 is turned on, the transistor T5 can make the level of the control signal Vc2(n) substantially equal to the low voltage VSS to turn off the transistor T7. The transistors T4 and D5 are, for example, biasing units 302 for lowering the level of the control signal Vc2(n) in response to the leading edge of the control signal Vcl(n) to turn off the transistor T7 and respond to the control signal Vcl ( n) The trailing edge is used to raise the level of the control signal Vc2(n) to conduct the transistor T7. Please refer to FIG. 3, which shows the timing sequence of the shift register unit s(n) in FIG. Figure. In the time period TP1, the output signal V〇(n-i) is equal to the voltage VDD, and the timing signal CLK and the control signal vci(n+2) are equal to the voltage VSS. At this time, the transistor T6 is turned off, the transistor T1 is turned on and the transistor T2 is turned on, so that the output signal Vo(n) is equal to the timing signal CLK, that is, the voltage VSS. The transistor T1 further causes the control signal Vcl(n) to be equal to the high voltage level: Vcl(8) = VDD - VtM. Where Vthl is the junction of the transistor T1 and the boundary voltage. The transistor T3 is also turned on, and its threshold voltage is, for example, equal to the threshold voltage of the transistor T1. The transistor T3 and the transistor T1 raise the control signal Vcl(n) to VDD-Vth1. The transistor T5 is also turned on to turn off the transistors T7 and T8 by controlling the signal Vc2(n) to approach the voltage VSS. In the time period TP2, the output signal Vo(n-1), the timing signal CLKB and the control signal Vcl(n+2) are equal to the voltage VSS, and the timing signal CLK is equal to the voltage VDD. At this time, the transistors T6, T1, and T3 are turned off, so that the node pi is floating. The timing signal CLK is boosted by the voltage VSS equal to the voltage VDD during the time period TP2. This huge voltage change causes the voltage signal Vc 1 (η) to further increase a difference r # J" due to the push-strapping effect. · f

r # J"· f : W3165PA 200805243 -/*cc/i7rrojtvu . Voltage Δν, so that the voltage signal Vcl(8) is equal to Vcl(8)^VDD-Vthl + ΔV. In the present embodiment, the difference voltage Δ ν is equal to: Δ (listening, where Cgs is the internal parasitic capacitance of the transistor T2, and Cpl is the equivalent capacitance seen by the node pi. At this time, the voltage signal vci(8) enables the transistor T2, the output signal Vo(n) is quickly charged to the voltage VDD. The transistor T5 is also turned on, so that the control signal vc2(n) is close to the low voltage VSS to turn off the transistor T7. In the time period TP3, the timing signal CLKB And the control signal • Vcl(n+2) is high level, the output signal Vo(nl) is equal to the voltage VSS. At this time, the transistor T6 is turned on to supply the voltage vss to the output terminal OUT to make the output signal Vo(n) equal Voltage VSS. The transistor T1 is turned off and the transistor T3 is turned on, so that the control signal Vcl(n) is equal to the voltage VSS, and the transistor T2 is turned off. The transistor T5 is turned off, and the transistor T4 is boosted by the control signal Vc2 ( The level of n) is equal to the voltage VDD-Vth. The transistors T7 and T8 are both turned on to supply the voltage VSS to the output terminal QUT and the node: P1, respectively, so that the output signal Vo(n) and the control signal Vcl(n) are equal to Voltage VSS. 10 where from time period TP3 to the next time period τρι The signal signal Vc2(n) is continuously equal to the voltage VDD_Vth. The transistor T7 continuously keeps the output signal v〇(n) equal to the voltage vss to avoid noise interference caused by other parasitic capacitances. However, the scanning operation of the liquid crystal display causes an error in the display surface. However, the long-time conduction causes the threshold voltage of the transistor T7 to rise due to the stress effect (&% effect), thereby failing to supply the voltage V%. The power month b ' to the output terminal Q' causes the pay shift to be temporarily stored as 1 〇〇 to cause a malfunction (Maifuncti〇n).

200805243 TW3165PA The shift register of the present embodiment is provided with a transistor in the early element S(n) to compensate for the abnormal operation of the transistor Τ7 due to the voltage increase of the Sa boundary, and the voltage signal Vcl(n+2) can be used. Helps to pull the output signal Vo(n) low to low voltage VSS. Thus, even if the transistor T7 is operated abnormally, the shift register unit S(n) of the present embodiment can make the signal level of the output signal Vo(n) less susceptible to errors. The n-th stage shift register unit of the embodiment generates a control signal via its own circuit design, and uses the control signal to control its own circuit and the n+2 stage shift register unit. Operation is controlled. Thus, the nth stage shift register unit of the present embodiment does not use its output signal to control the circuit operation & itself or other stage shift register unit. In this way, the n-th stage shift temporary storage crying unit and the scan driver using the same have the advantages that the output signal delay time is relatively slight, and the liquid crystal of the n-th stage shift register unit of the embodiment is applied. The display has the advantages of better quality of the display screen. In addition, the nth stage shift register unit of the embodiment is provided with two level control units for lowering the output signal level. When the one of the level control units is subjected to the abnormal operation due to the stress effect due to the long-time conduction, the n-th stage shift register unit of the present embodiment may be via another level control unit. Help to pull down the output signal to equal the low voltage value. For example, the n-th stage shift register unit of the present embodiment can make the level of the round-out signal less likely to be wrong due to abnormal operation of the level control unit, and has the advantage of long service life.

rW3165PA 200805243 Ming Mai makeup Fig. 4' is a detailed circuit diagram showing a second circuit embodiment of the shift register unit s(n) of the second embodiment. The nth stage shift temporary storage unit s(n) of the present embodiment is different from the nth stage shift register unit s(n) of the second figure in that the transistor T3 in the driving unit 2〇2a is changed to The wiring method of the transistor 。. The pole face of the transistor T9 is connected to the node ρι, and the gate receives the control signal VCl(n+2)' source receiving voltage VSS. The transistor T9 is used to provide the electrical waste vss to the node in response to the rising and the edge of the control condition number Vcl(n+2), so that the control §fl number Vcl(n) is equal to the voltage vss. ...in the timing periods TP1 and TP2, the control signal Vcl(n+2) is equal to the electric C VSS 'this #电晶 Ts> is off. In the timing period TP3, the control signal Ve 1 (η+2) is equal to the voltage _ vth to conduct the transistor Τ9, 3 to supply the voltage VSS to the node to make the voltage signal Vcl(8) or the like VSS' to turn off the transistor T2. ^ The nth stage shift register unit s (8) of the present embodiment is thrown by a transistor::: transistor T3 ' However, it is substantially similar to the transistor, and the nth stage shift register is substantially similar to the transistor. The unit also has the advantages of low load and long service life, and the application of the embodiment of the present embodiment of the η-level shift temporary storage 5 § set; #, 六曰_ u, the quality of the advantages of the early liquid is obvious Do not have a display of the face of May, reference to the 5th figure of the face, the network + only the third pure temporary storage of the unit of the state of the United States, the detailed circuit diagram of the n-circuit mode. The 17th embodiment of the present embodiment 200805243 TW3165PA ^ ^ ^ rT The difference between the shift register unit S(n) and the sense shift register unit of Fig. 4 is that the drive unit 202b further includes a transistor T3. The transistors Τ3 and T9 have substantially The similar function is used to control the Vel (8) equal to the voltage signal vss in the timing period τί> 3. Thus, the n-th stage shift register unit of the present embodiment also has the advantages of lower output load and longer service life. 'The liquid crystal display to which the shift register unit of the first embodiment of the present embodiment is applied has The advantage of the quality of the picture is better. ^ Please refer to Fig. 6, which shows the detailed circuit of the fourth embodiment of the shift register unit of Fig. 4. The nth stage shift of the embodiment The difference between the temporary storage of hS(n) and the η-level shift register of the :: map includes a transistor 10 in the pure _ unit. () Transistor ΤΗ) Line _ to the output end guess, the gate CLKB' source receives the voltage vss. The transistor Τ1() is used to return ??? CLKB to provide a turn vss bribe, so that the signal Vo(8) is equal to the voltage VSS. In the timing period τρι and T = equal to voltage _, at this time, the transistor T1 〇 is conducting: 上升 the rising edge makes the wheel * signal v ° (8) equal to electric = ss ' = in the (four) period TP2, the timing signal clkb and other VSS, this Day t transistor T10 is off. In the n-th stage shift register unit 204c of the present embodiment, the transistor T1 〇 U factory is set, and the current control is set to decrease and decrease V. (Transfer to electricity $ v : : 5 2 and TP3 output signal V. (8) The signal level. So, 200805243 2?//7/5· Πν3ΐ65ΡΑ dr The display with lower load and longer service life has more display 昼The quality of the surface is more than the first - the second of the liquid sputum is shown in Figure 1 is the shift register unit S (8) 2 temporarily ^ = W ° the implementation of the η-level shift register early and The second figure of the second figure is different from the n-stage shift register unit.

In the drive unit leg, a transistor Tu is further included. As early as the transistor ΤΙ 1, the receiving voltage VD is I VUD, and the gate receives the timing signal ΙΓα ^ point Ρ2. The transistor TU is used to respond to the timing voltage to the section __ so that the control signal Μ (8) is at the voltage VDD. Among them, the transistor τ 11 且 and * 八丁私曰 菔 菔 U1 is longer than the transistor 丁5, $ when the crystal T5 and T i! are both on, the control signal w (8) is pulled down to the voltage by the transistor T5 VSS. In the timing cycle TP and TP3, the timing signal CLKB is equal to the voltage VDD, and the transistor T11 is turned on to make the control signal W(8) equal to the voltage VDD-Vth. However, the transistor T5 is enabled during the timing period so that the control signal Vc2(n) is pulled down to the voltage vss. In the timing period TP2, the timing signal CLKB is equal to the voltage vss, and the transistor T11 is turned off. The n-th stage shift register unit s(n) of the present embodiment is provided with a transistor T11 in the level control unit 204b, and has a substantially similar function to the transistor 14 for use in the timing period TP3. Raise the level of the voltage signal Vc2(n) to be equal to the voltage VDD-Vth. Thus, the present embodiment 19 200805-243 丽継. The 11th stage shifting temporary storage unit also has the advantages of lower output load and longer service life, and the nth stage shift temporary storage of the present embodiment is applied. The liquid crystal display of the J-element has the advantage of showing the better quality of the face. Referring to Figs. 8 to 1 , there are shown detailed circuit diagrams of the sixth to eighth circuit embodiments of the shift register unit S(n) of Fig. 2, respectively. The nth stage shift register unit s(n) of the sixth to the eighth embodiment is respectively based on the nth stage shift register unit s(n) of the 4th to 6th figures. In the embodiment, the sixth to eighth embodiments are different from the shift register unit S(n) of the fourth to sixth embodiments in that the driving unit 2〇2b further includes a transistor 11 . Thus, the operations of the shift register unit S(n) of the third, eighth and eighth embodiments can be analogized according to the description in the fifth embodiment. Please refer to FIG. 11 for the analog timing diagram of the output signal Vo(8) of the shift register 第 of FIG. In the structure of this embodiment. The stray resistance of each of the crystals T1 to T11 is 45 kq (kiloohm), and the capacitance 15Pf (PiC0Farad) is used to simulate the output signal v 〇 (8). Curve (7) _ nA map shift register unit s (8) output signal v 〇 (8) signal waveform diagram 'and curve 1; 1 is the following level shift register unit's turn signal ν 〇 (η +1) Output signal V when controlling transistors T9 and T6. , (8) signal waveform simulation diagram. From the curves 1〇 and η, it can be seen that the MV (8) of the apricot case of the apricot case has the advantage of delaying the micro-threshold and the short-term rise and fall time. 20 200805243 -3⁄43⁄4.. ΓΨ3165ΡΑ Second Embodiment Structure Referring to Fig. 12, there is shown a block diagram of a shift register in accordance with a first embodiment of the first embodiment of the present invention. The shift register 2 (10) is different from the shift register 1 of the first embodiment of the present embodiment in that the shift register units U(1) to U(m-2) include two The control terminals RT1 'two RT2' are respectively receiving the nodes of the shift register unit identification ^~u(4)? ! The control signals Vcl(3)~Vcl(m) and the shift register unit U(2)~ Gong...1) output signals V〇(2)~Vo(m_l). Next, the shift temporary storage of the present embodiment is exemplified by taking the structure of shifting the 10-bit temporary storage into the n-th stage shift register unit u(n) in the units U(1) to U(m) as an example. Further implementation of the various implementations of the unit u(n), η is a natural number. Referring to Fig. 13, there is shown a detailed circuit diagram of a first circuit embodiment of the shift register unit U(n) of Fig. 12. The shift register unit U(n) of the present embodiment is different from the shift register unit s(n) of FIG. 2 in that the drive unit 202b includes the transistor T12 and replaces the second with the transistor T12. The transistor 移位3 in the shift register unit §(η). The drain of the transistor T12 is coupled to the node pi, the gate receives the output signal Vo(n+1) of the n+1th stage shift register unit U(n+1), and the source receives the voltage VSS. The transistor T12 is configured to supply the voltage VSS to the node Pi in response to the leading edge of the output signal γ〇(η+1) such that the control signal Vcl(n) is equal to the voltage VSS. In the timing periods τρί and TP2, the output signal v〇(n+1) is equal to the voltage VS S, at which time the transistor 12 is off. In the timing period τρ3, the control signal Vo(n+1) is equal to the voltage VDD, so the transistor T12 is 21

-TW3165PA 200805243 ~:r" ϋ..·^ ^ Control ^ to provide voltage vss to node n, so that voltage W (8), etc. & I pressure vss m closed transistor T2. τ" ί: ί5 type nth stage shift register unit U (8) with transistor 立 / _, 2 in the shift register unit S (8) transistor Τ 3, then i period has the effect of the real f 'Used for timing' ', the middle start control signal Vcl(n) is equal to the voltage VSS. Thus, the liquid phase of the η-stage shift temporary storage material 70 of the present embodiment is applied. The day display 11 has the advantage of showing that the quality of the face is better. Chuanxi / 2,,, Figure 14, which is a detailed circuit diagram of the embodiment of the shift register unit circuit of Fig. 12. The shifting latitude=early 7"(8) of the present embodiment is different from the shift register unit S(8) of Fig. 13: the =w moving unit 202bt further includes the transistor Τ3. However, (= the function of the electric body Τ3 and the Τ12 shift of the transistor /12/1 type η stage shift temporary storage unit also has the advantage of output negative == long life, and the application of the second negative element The liquid crystal display has the characteristics of the display screen uf uf, two "," Figure 15, which is shown in Figure 12 shift temporary storage crying (8) ring brother 14 map shift register single itu (8) not 22

lW3165PA 200805243 is that the level control unit 204c further includes a transistor T10. In this way, the nth stage shift register unit of the present embodiment can make the round-out signal Vo(8) equal to the voltage VSS in the timing periods ΤΡ1 and ΤΡ3, so as to avoid the noise generated by the parasitic capacitance affecting the output signal v〇. (n) The signal level. Therefore, the n-th stage shift register unit of the embodiment also has the advantages of lower wheel load and longer service life, and the liquid crystal display of the n-th stage shift register unit of the embodiment has more Shows the advantages of better quality of the face. Please refer to the 16th to 18th drawings, which respectively show detailed circuit diagrams of the fourth to sixth circuit embodiments of the shift register unit U(n) of FIG. 12, wherein the fourth to sixth embodiments are The nth stage shift register unit U(n) is an embodiment derived from the nth stage shift register unit U(n) of the 13th to 1st $. The fourth to sixth embodiments are different from the shift register unit u(n) of the first to fifteenth embodiments in that the driving unit 2 further includes a transistor T11 which is substantially similar to the transistor T4. The power month b is used to raise the level of the voltage signal Vc2(n) in the timing period τρ3 to be the voltage VDD-Vth. In this way, the nth stage shifting temporary storage unit of the embodiment also has the advantages of lower output load and longer service life, and the liquid crystal display of the nth stage shift register unit of the embodiment has more display. The advantage of the quality of the picture is better. SECOND EMBODIMENT A shift register of the present embodiment and a shift register of the first embodiment 23

ΐ One,: ΐ. 200805243...

2; ^ face; m * iW3165PA • The difference is that the drive unit of the shift register unit is used to respond to the first control signal of the n+2 shift register unit. Level-level control unit. n is a natural number. Next, the implementation structure will be enumerated to explain the operation of the n-th stage shift register unit in detail. , the first implementation structure 纟 implementation of the structure of the shift register and the first! The first embodiment shown in the figure ▲ The shift register of the first embodiment is substantially equal, and the description is shown. Please refer to the detailed circuit diagram of the ninth circuit embodiment of the 19th (the fourth) is the L shift register unit S (8). The color register register unit S (8) of the present embodiment and the shift register of the eighth figure The difference in the unit is that it does not have the level control unit core, but only the level control unit f 204b is used to make the output signal γ0(8) equal to the voltage, affecting the reduction of the center of the heart "V. (8). For example, ά S circuit _ level The shift register unit also has the advantage of output negative: the n-th stage shift register of the first embodiment (four) shows that the quality of the surface is better. The detailed shift of the tenth circuit embodiment of the S(n), the register of the register unit bit register unit S(n) and the figure of FIG. 19: the shift of the present embodiment is in the drive unit 202a thereof. It also includes the difference between the Thunder and the early days of the 电 电 电 乃 乃 乃 乃 ' ' ' 其 其 200 200 200 200

PW3165PA

The timing signal CLKB provides an output signal ν〇(η·1) to a node ρι. Therefore, the n-th stage shift register unit of the embodiment also has the advantage of the round-off load=low, and the liquid crystal display of the n-th stage shift register unit of the embodiment has the quality of displaying the surface. The advantage is better. SECOND EMBODIMENT Structure The shift register of the present embodiment is substantially equal to the shift register of the second embodiment in the first embodiment shown in Fig. 12. Please refer to the description. Referring to FIG. 21, a detailed circuit diagram of a seventh circuit embodiment of the shift register unit U(n) of FIG. 12 is shown. The shift register unit U(n) of the present embodiment is different from the shift register unit of FIG. 20 in that it does not have the transistor T11, and further includes a level control unit 204c including a transistor. T13. The drain of the transistor T13 is coupled to the output terminal 〇υτ, and the gate receives the output signal ν〇(η+ι) of the n+th stage shift register unit u(n+1), and the source receives the electric dust. Vss. The transistor Τ13 is configured to provide VSS to the output terminal in response to the leading edge of the output signal ν〇(4)), so that the round-out signal ^(8) is equal to the voltage VSS 〇 in the day-sequence period TP1, and the output signal v〇(n+]:) Equal to the voltage vss, the output signal Vo(8) is equal to the voltage vss. In the timing period τρ2, the output signal V〇(n+1) is equal to the voltage vss, at which time the transistors 3 are turned off so that the output signal Vo(n) is equal to the voltage VDD. And in the timing period τρ3 * - . 25 V 'j j J ^' *

In V 'j j J ^' * -TW3165PA 200805243, the output signal Vo(n+1) is equal to the voltage VDD'. At this time, the transistor m is turned on so that the output signal Vo(n) is equal to the voltage VSS. The n-th stage shift register unit u(n) of the present embodiment is provided with a transistor T13 in the level control unit 204c to make the round-out signal Vo(8) equal to the voltage VSS in the timing period 1?3 to avoid circuit miscellaneous The signal affects the signal level of the output signal Vo(n). Since the n-stage shift register unit of the embodiment controls the operation of a transistor according to the output signal of the n+1th-order shift register unit, the n-th shift of the present embodiment is temporarily suspended. The memory device has the advantages of lower output load and longer service life, and the liquid crystal display of the n-th stage shift register unit of the present embodiment has the advantage of better quality of the display surface. . Referring to Fig. 22, a detailed circuit diagram of an eighth circuit embodiment of the shift register unit U(n) of Fig. 12 is shown. The shift register unit U(n) of the present embodiment is different from the shift register unit of FIG. 21 in that the driving unit 202a further includes a transistor 3 for providing in response to the time signal CLKB. The signal Vo(nl) is output to the node P1. In this way, the n-th stage shift register unit of the embodiment also has the advantages that the wheel load is lower and the service life is longer, and the liquid crystal display state in which the n-th stage shift storage unit of the embodiment is applied has a display. The quality of the picture is better. Referring to Fig. 23, there is shown a detailed circuit diagram of a ninth circuit embodiment of the shift register unit U(n) of Fig. 12. The implementation of the ^ ^ = 26 200805243 ~

· ^W3165PA, the bit temporary storage unit U(n) is different from the shift register unit of FIG. 22, f further includes a transistor T10 in the level control unit 204c, which is used for the k-sequence period TP1 And Ding! > 3 makes the output signal ¥ 〇 (11) equal to the voltage ^8, to avoid circuit noise affecting the signal level of the turn-off signal v 〇 (n). Therefore, the nth stage shift register unit of the embodiment also has the advantages of lower output load and longer service life, and the liquid crystal display of the nth stage shift register unit of the embodiment has more display. The advantage of better quality of the noodles.

Please refer to pages 24 to 26, which respectively show the detailed electric diagrams of the tenth to twelfth circuit embodiments of the shift temporary stock benefit το U(n) of the figure. The first stage shift register unit U(n) of the tenth to twelfth embodiments is derived from the nth stage shift register unit U(n) according to the 21st to 23rd graphs, respectively. Implementation. The multi-digit temporary storage unit U(n) of the tenth to twelfth embodiments is different from the shift register unit of the 21st to 23rd drawings in that the driving unit 202b further includes a transistor τη to In the timing period TP3, the level of the voltage signal ve2(4) is raised with the transistor T4 to be substantially equal to the voltage VDD. In this way, the n-th stage shifting temporary storage H unit of the present embodiment also has the advantage of having a longer life (4), and the application of the n-th shifting temporary flipping unit of the present embodiment has more display. The advantage of better quality. Third Embodiment Structure Referring to Figure 27, it is shown in accordance with the present invention 27 200805243, with the following:

, Ershi lion catch. rW3165PA • Block diagram of the shift register of the second implementation structure. The shift register 3〇0 differs from the shift register 2〇〇 of the second embodiment of the first embodiment in that each stage of the shift register unit w(1)~w(m-2) The control terminal RT1 and the D2 system receive the control signals Vcl(2)~Vcl(mi) and the shift register on the node ρι of the shift register unit w(2)~w(m·), respectively. The control signals Vcl(3) to Vcl(m) at the point P1 of the unit w(7)~w(m). Next, the shift register unit of the present embodiment is listed as an example of the nth stage shift register unit (8) in the shift register units W(1) to w(m). Further, the 酿(η) brewing implementation circuit is further described, and n is a natural number. Referring to Figure 28, there is shown a detailed circuit diagram of a first circuit embodiment of the shift register unit W(n) of Figure 27. The shift register single sw(8) and the 帛8 map shift of the present embodiment differ only from the register unit S(8) in that the level control unit 204c has a transistor Τ6, and replaces the transistor 〇 〇 age transistor with it. Τ6' is not connected to the node, and the gate receives the control signal %(4) of the (n+1)th stage shift register unit w(n+1), and the source receives the timing signal CLK. The crystal T6 is used to provide a timing job to the output terminal OUT when the level of the control signal ~1 (11+1) is higher than the timing minus CLK (4). In the timing periods m and TP2, the control signals Vcl(n+1) are equal to the power C VSS and the voltage VDD-Vth', respectively, and the timing signals CLK are equal to the power VSS and the voltage VDD, respectively. So, in the timing cycle? 1 and τρ2 The transistor T6 is turned off. In the timing period τρ3, the control signal 28

200805243 • Two-way navigator · rW3165PA vcl_) advances step-by-step with the difference voltage Δν compared to its level in the timing period ΤΡ2, while the timing signal CLK is equal to the power M VSS . In this way, the transistor 76 is turned on during the timing period to provide the low voltage level of the timing signal CLK to the output terminal 〇υτ, so that the output signal voltage VSS is in the nth stage shift register unit of the present embodiment. The transistor T6' is replaced by a transistor D' to enable the output signal V in the timing period τρ3. (8) Equal to the voltage VSS to prevent circuit noise from affecting the output signal ν〇(η). The hole number is $ and the private day body Τ6' can lower the output signal when the transistor η is called for a long time due to the influence of the stress effect, so that the material is at the lowest level. In this way, the first shifting device of the present embodiment also has the advantages of lower output load and longer material life, and the liquid (four) display of the n-th stage lung register unit of the present embodiment is applied. It has the advantage of showing better quality of the face. Referring to FIG. 29, a detailed circuit diagram of a second circuit embodiment of the shift register unit W(n) of FIG. 27 is shown. The shift register unit a (4) of the j-bit register unit W (8) and the 帛 28 diagram of the present embodiment is not included in the drive unit 202a, and the transistor T3 is further included in the timing signal CLKB. The output signal vo^q) is provided to the node ^. Thus, the nth stage shift register unit of the embodiment has the advantages of lower load and longer service life, and should be shifted by the jth stage of the embodiment. The liquid crystal display of the register unit has the advantage of better quality of the display surface. ' 29 200805243 , ^

^ 二达缅航· FW3165PA, ... Please refer to Figure 3, which shows the detailed circuit diagram of the implementation of the shift register unit η of the 27th figure. The orientation register unit W(8) of the present embodiment and the shift register unit w(n) of FIG. 29 are in that the level control unit includes a transistor 10, which is used for the timing periods TP1 and τρ3. The intermediate output signal ν 〇 (8) is equal to the voltage VSS ' 1 to avoid circuit noise affecting the signal level of the output signal ν 〇 (8). In this way, the n-th stage shift register unit of the present embodiment also has the advantages of negative turn-off, low turn, and long service life, and the liquid crystal device of the _th and bit temporary storage n units of the present embodiment is applied. It has the advantage of being good and good. Third Embodiment The shift register of the present embodiment is the same as the shift register of the first embodiment in that the third level control unit 70 of the nth stage shift register unit is used. The low voltage level of the first timing signal is provided to the output terminal in response to the month il edge of the first control signal of the n+1th stage shift register unit. η is a natural number. Next, the implementation structure will be described in detail for the operation of the n-th stage shift register unit. First Embodiment Architecture Referring to Figure 31, there is shown a block diagram of a shift register in accordance with a first embodiment of the third embodiment of the present invention. The shift register 400 differs from the shift register 1 of the first embodiment of the first embodiment in the control of the shift register units x(1) to x(m-2) of each stage. End RT receives 30 200805243,

^ Erlian Fuhang·TW3165PA _ Shift temporary storage control signal on node PI of unit X(2)~X(m-l)

Vcl(2)~Vcl(m-l). Next, taking the structure of the nth stage shift register unit χ(n) in the value shift register unit (1) to x(m) as an example, the shift temporary storage unit of the present embodiment is listed as a unit. Further description of various implementation circuits of (n), η is a natural number. A detailed circuit diagram of a first circuit embodiment of the shift register unit Χ(η) of FIG. 31 is shown in FIG. The shift register unit Χ(n) of the present embodiment is different from the shift register unit s(n) of FIG. 2 in that the level control unit 204c has a transistor T6 and is replaced by The transistor T6 is configured to prevent the output signal Vo(n) from being equal to the voltage VSS during the timing period TP3 to prevent the circuit noise from affecting the signal signal of the output signal Vo(8); and the transistor T6 is more likely to be in the transistor T7 for a long time. When the conduction is abnormal due to the influence of the stress effect, the output signal is pulled down to be equal to the lowest voltage level. Therefore, the n-th stage shift register unit of the embodiment has the advantages of lower output load and longer service life, and the liquid crystal display of the n-th stage shift register unit of the embodiment has more Shows the advantages of better quality of the face. Referring to Figure 33, there is shown a detailed electrical circuit diagram of the embodiment of the circuit of the shift register unit Χ(η) of Fig. 31. The shift register unit Χ(n) of the present embodiment is different from the shift register unit S(n) of FIG. 32 in that the drive unit 202a has a transistor T9, and replaces the transistor T3 with it. 〇2〇〇8〇5243rW3l65PA ' — The drain of a transistor T9' is coupled to the node PI, and the gate receives the control signal Vci of the n+1th shift temporary storage unit η(η+1) (n+ 1) The source receives the timing signal CLK. The transistor T9 is configured to provide the timing signal CLK to the node P1' to make the control signal Vcl(n) equal to the timing signal CLK when the level of the control signal Vcl(n+1) is higher than the level of the timing signal CLK. In the timing periods TP1 and TP2, the control signals vcl(n+l) are equal to VSS and voltage (VDD-Vth), respectively, and the timing signals CLK are equal to the voltage VSS and the voltage VDD, respectively. Thus, in the timing periods TP1 and τρ2, the intermediate power body T9' is turned off. In the timing cycle TP3, the control signal

Vcl(n+1) further increases a difference voltage Δν compared to its level in the timing period τρ2, and the timing signal CLK is equal to the voltage vss. Thus, in the timing period TP3, the transistor T9 is turned on to provide the low level of the timing signal CLK to the node ρ, so that the control signal is equal to the voltage VSS 〇, the nth stage shift register of the local mode The cell χ(η) replaces the transistor T3 with a transistor T9. However, T9, with the transistor, has a substantially close function to control the signal Vd(8) in the timing period τρ3: at the voltage VSS. Thus, the n-th stage shift register of the present embodiment has a rhyme that has a long life, and the liquid crystal display of the n-th shift register unit of the present mode is more visible. The advantage of better quality. 32

TW3165PA 200805243 • Road map. In the shift register unit of the ^ to H mode t (8) system / knife is the shift register unit port in the brother 5 ~ brother 10 picture: the χ = the third is to (4) the deposit is early ^ (8) The transistor 吖 and T9 in the shift register unit are replaced by transistors '6' and Τ9', respectively. Thus, the third to the eighth implementation: the formula: private: the operation and function of the temporary register unit can be obtained according to the description in the first and second consistent manners. The second embodiment of the present invention is a block diagram of a shift register in accordance with a third embodiment of the present invention. The shift register 5 is different from the shift register of the second embodiment of the second embodiment. The difference is in the control terminal of the shift register unit γ(1)~Y(m_2) Receive = save ... γ (2) ~ node ρι on the control signal C () ~ Vcl (ml), and each level shift register unit 丫 (1) melon system receives the next stage shift register single pass γ (10) Output condition number Vo(2)~Vo(m). Next, taking the structure of the nth stage shift register unit γ(8) of the shift register unit as an example, the various implementation circuits of the shift register unit (8) of the local _ register are further explained, and η is natural. number. Temporary storage = two t The sub-riding is shown in Figure 40 (10) The detailed circuit diagram of the sixth circuit implementation of the 'early XY (8) brother. In the sixth embodiment, the shift register unit γ(η)^ '...一---------- 33

2008〇5243TW3165PA is not the shift temporary storage crying in the 13th to 18th, except that the first to the first;:I (n) derivative implementation unit Y(n) will be the 13th ~ In Figure 18, the transistor T6 of the register is replaced by a transistor T6. Thus, the first shift register unit in the first = ^ η) and the # % / 弟 A, 司方乍 and the function can be the first according to the first embodiment of the shift register And the second sinus gets. The description of the fourth embodiment of the present invention is different from the shift temporary storage of the second embodiment in that the n-th stage shift register is driven first. The unit is configured to close the first level control unit when the level of the first control signal of the n+1th shift register unit is higher than the level of the first timing signal. n

For natural numbers. Next, the implementation structure will be described in detail, and the operation of the nth stage shift register unit will be described in detail. TO First Embodiment Architecture The shift register of the present embodiment is substantially equal to the shift register of the first embodiment in the third embodiment shown in Fig. 31. Please refer to the related description. Referring to Figures 47 and 48, there is shown a detailed circuit diagram of the ninth and tenth circuit embodiments of the shift register unit X(n) of Figure 31. In the ninth and tenth embodiments, the shift register unit χ(η) is 34 200805243

* Derivative embodiment of shift register unit s (8) in TW3165PA-S 19 and 2G diagrams, wherein the shift register unit X(8) of the ninth and tenth embodiments is a shift register The electro-ceramic T9 in the unit s(n) is replaced by a transistor T9. Thus, the operation and the operation of the shift register unit in the ninth and tenth embodiments can be obtained by analogy in the second embodiment of the shift register of the third embodiment of the third embodiment. SECOND EMBODIMENT STRUCTURE The shift register of the present embodiment is substantially equal to the shift register of the second embodiment in the third embodiment of Fig. 4G. Please refer to the related description. Ming Ludi 49~54, the display is moved as early as (8) the second pin circuit implementation saves the seventh to twelfth embodiment of the shift ^,, · Tian circuit diagram. The shift register unit named in the 21st to 26th diagrams is as early as: Y (8) is different from the seventh to twelfth implementations, and the unit Y(n) is shifted. The memory unit is replaced by a uniform Chinese shift register body T9. Thus, the operation and the function of the seventh to twelfth implementations of the transistor 11 in the form of an electro-crystal can be performed according to the second embodiment of the shift register of the second per-a mode. The first implementation of the example is analogous. The third implementation architecture shows the second actual implementation structure of the shift register fish.

200805243

^ 二理w muscle.xW3165PA is substantially equal, please refer to the shift staging of the third implementation structure of the example t.罝- $ ft55~π diagram, which is a detailed circuit diagram of the implementation of the fourth to sixth circuit of the shift register of the 27th figure. The shift temporary section in the fourth = 'th' mode The meta-system is the derivative implementation of the 28th to 3rd #图#^^^ unit. The uniqueness of the towel is that the shift register unit of the fourth to the fourth mode will be the first 如图~ The operation of the transistor T9 and the butyl 6' in the memory, and the operation of the shift register unit of the fourth embodiment of the fourth embodiment, and the force A system can be implemented according to the second embodiment. The description of the second embodiment of the shift register of the architecture is obtained by analogy. In the above embodiments, only the shift registers 1〇〇, 2〇〇, 3〇Q, 400, and 500 are responded. The operation is performed by operating the timing signals CLK and CLKB which are mutually offset between the two enable times. However, the shift registers 100 to 500 can also use three or more timing signals to shift the levels. Bit register units S(n), U(n), W(n), X(n), and Y(n) are controlled, as shown in blocks 58Α, 58Β, 59Α, and 59Β, 58th and 5th 8Β The figure shows a block diagram and a timing signal waveform diagram of a shift register stored in a first embodiment of the first embodiment applied to three timing signals, and FIGS. 59 and 59 respectively illustrate the first embodiment. The shift register of the first implementation structure is applied to the block diagram and the timing signal waveform diagram of the four timing signals. As can be seen from the above, as long as any two adjacent shifts of the shift register 1〇〇~500 are- - ^ ..... ....... - , · _ _ _ _ __ ... - ' 36

200805243 . Sanda number: The enable time of the timing signal received by the timing terminal C of the TW3165PA bit register unit is staggered, and the timing terminal CB and the n+1th shift of the nth stage shift register unit are temporarily suspended. The enabling time of the timing signal received by the timing terminal C of the memory unit is also staggered, and the operator who can perform substantially the same as the above embodiment does not deviate from the technical scope of the present invention. η is a natural number less than or equal to m. The shift register disclosed in the above embodiment of the present invention includes a multi-stage shift temporary storage unit, and each shift register unit has a circuit node. The nth stage shift register unit in the shift register of the present invention inputs the voltage signal on the circuit node of one of the n+1th stage or the n+2th stage shift register unit. The stage shift register is used to control its operation. As such, the shift register disclosed in the above embodiments of the present invention has the advantages of an output load ratio and an output signal that is not easily distorted. Therefore, the liquid crystal display of the shift register disclosed in the above embodiments of the present invention is preferably of a better quality. The shift register disclosed in the above partial embodiment of the present invention is further provided with one, and the quasi-cell unit pulls the output signal level down to the monthly pressure. Thus, when the transistor in one of the level control units is raised due to the influence of the stress effect, causing the operation to be abnormal, the shift register disclosed in the above embodiments may be additionally crying. The control unit pulls the output signal to the ground voltage to cause the shift to temporarily malfunction. As described above, the above-mentioned partial embodiments of the present invention have the advantage of extending the service life of the shift register unit.

37

fW3165PA 200805243 - * In summary, although the invention has been disclosed above in a preferred embodiment, it is not intended to limit the invention. It will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

200805243 二达编现.TW3165PA [Simple diagram of the drawing] Fig. 1 is a diagram showing the second diagram of the implementation of the first embodiment of the first embodiment of the first embodiment of the present invention. It. t+ ^ n is a detailed circuit diagram of the first circuit of the cell S(n). Figure 3 shows the timing diagram of the listening/private suppression in Figure 2. The relay of the medium shift temporary stolen unit S (8) Fig. 4 is a detailed circuit diagram of the first embodiment of the road. The second electric circuit of the unit 11 s (8) Fig. 5 is a detailed circuit diagram of the first embodiment. The third circuit of the register unit s (8) is shown in Fig. 6. The detailed circuit of the embodiment of the circuit ^ / bit temporary storage 11 unit S (8) of the fourth power Figure 7 is the first picture

The detailed circuit of the circuit (four) mode ^ the fifth power of the shift register unit S (8) The eighth figure shows the detailed circuit diagram of the lffiI road. The sixth electric power of the temporary storage of the early element S (n) Figure 9 shows the detailed circuit diagram of the implementation of the transfer of the i-th diagram. The seventh circuit of the memory register s s (8) Fig. 10 shows the detailed circuit diagram of the circuit type of the first figure (4). Shift (four) register unit _ eighth Figure 11 shows the timing diagram of the shift ν 〇 (η) in Fig. 10. The output signal of the shift register unit is shown in the second embodiment of the present invention.

TW3165PA 200805243 A moving face: "Children." Block diagram of the shift register. Figure 13 is a detailed circuit diagram showing a first circuit embodiment of the shift register unit U(n) of Figure 12; Fig. 14 is a detailed circuit diagram showing the second circuit embodiment of the shift register unit U(n) of Fig. 12. Fig. 15 is a detailed circuit diagram showing a third circuit embodiment of the shift register unit U(n) of Fig. 12. Fig. 16 is a detailed circuit diagram showing a fourth embodiment of the shift register unit U(n) of Fig. 12. Fig. 17 is a detailed circuit diagram showing the fifth circuit embodiment of the shift register unit U(n) of Fig. 12. Fig. 18 is a detailed circuit diagram showing the sixth circuit embodiment of the shift register unit U(n) of Fig. 12. Fig. 19 is a detailed circuit diagram showing a ninth circuit embodiment of the shift register unit S(n) of Fig. 1. Fig. 20 is a detailed circuit diagram showing the tenth _ circuit implementation of the shift register unit S(n) of Fig. 1. Fig. 21 is a detailed circuit diagram showing a seventh circuit embodiment of the shift register unit U(n) of Fig. 12. Fig. 22 is a detailed circuit diagram showing the eighth circuit embodiment of the shift register unit U(n) of Fig. 12. Fig. 23 is a detailed circuit diagram showing a ninth circuit embodiment of the shift register unit U(n) of Fig. 12. Figure 24 is a detailed circuit diagram showing an embodiment of the circuit of the second lion arc H165PA of the shift register unit U(n) of Fig. 12; Fig. 25 is a detailed circuit diagram showing an eleventh circuit embodiment of the shift register unit U(n) of Fig. 12. Figure 26 is a detailed circuit diagram showing a twelfth circuit embodiment of the shift register unit u(n) of Fig. 12. Figure 27 is a block diagram showing a shift register of a third embodiment in accordance with a second embodiment of the present invention. Figure 28 is a detailed circuit diagram showing the first φ circuit embodiment of the shift register unit w(n) of Figure 27. Figure 29 is a detailed circuit diagram showing a second circuit embodiment of the shift register unit w(n) of the second figure. FIG. 30 is a detailed circuit diagram showing a circuit embodiment of the shift temporary storage element W(n) of FIG. 27, and FIG. 31 is a schematic diagram showing the shifting of the first embodiment according to the third embodiment of the present invention. The block diagram of the register. Fig. 3(2) is a detailed circuit diagram showing a first circuit embodiment of the shift register unit (8) of Fig. 31. =3 _ shows the shift register unit X (8) of Fig. 31: Detailed circuit diagram of the circuit implementation mode. 5 two? The drawing is not the same as the shift register unit X (8) of Fig. 31: The detailed circuit diagram of the circuit integration mode.

Ϊ: 5 2 f is the detailed circuit diagram of the E circuit of the shift register unit X (8) of Fig. 31. Figure 36 Figure 1 shows the fifth of the shift register unit X (8) of Figure 31

TW3165PA 200805243 * Migration / 1 lung 7 / several · Detailed circuit diagram of the circuit implementation. Figure 37 is a detailed circuit diagram showing a sixth circuit embodiment of the shift register unit X(n) of Figure 31. Figure 38 is a detailed circuit diagram showing a seventh circuit embodiment of the shift register unit X(n) of Figure 31. Fig. 39 is a detailed circuit diagram showing an eighth circuit embodiment of the shift register unit X(n) of Fig. 31. Figure 40 is a block diagram showing a shift register of a second embodiment of the third embodiment of the present invention. Fig. 41 is a detailed circuit diagram showing the first circuit embodiment of the shift register unit Y(n) of Fig. 40. Figure 42 is a detailed circuit diagram showing a second circuit embodiment of the shift register unit Υ(η) of Figure 40. Fig. 43 is a detailed circuit diagram showing a third circuit embodiment of the shift register unit Υ(η) of Fig. 40. Figure 44 is a detailed circuit diagram showing a fourth embodiment of the shift register unit Υ(η) of Fig. 40. Fig. 45 is a detailed circuit diagram showing the fifth circuit of the shift register unit Υ(η) of Fig. 40. Fig. 46 is a detailed circuit diagram showing a sixth circuit embodiment of the shift register unit Υ(η) of Fig. 40. Fig. 47 is a detailed circuit diagram showing a ninth circuit embodiment of the shift register unit Χ(η) of Fig. 31. Figure 48 is a diagram showing the tenth portion of the shift register unit Χ(η) of Fig. 31, 200805243—

A detailed circuit diagram of the implementation of the rW3165PA circuit. Fig. 49 is a detailed circuit diagram showing a seventh circuit embodiment of the shift register unit Y(n) of Fig. 31. Fig. 50 is a detailed circuit diagram showing an eighth circuit embodiment of the shift register unit Υ(η) of Fig. 31. Fig. 51 is a detailed circuit diagram showing the ninth circuit embodiment of the shift register unit Υ(η) of Fig. 31. Figure 52 is a detailed circuit diagram showing a tenth circuit embodiment of the shift register unit Υ(η) of Figure 31. Fig. 53 is a detailed circuit diagram showing an eleventh circuit embodiment of the shift register unit Υ(η) of Fig. 31. Fig. 54 is a detailed circuit diagram showing a twelfth circuit embodiment of the shift register unit Υ(η) of Fig. 31. Fig. 55 is a detailed circuit diagram showing a fourth circuit embodiment of the shift register unit W(n) of Fig. 27. Figure 56 is a detailed circuit diagram showing a fifth embodiment of the circuit of the shift register unit W(n) of Figure 27. Fig. 57 is a detailed circuit diagram showing a sixth circuit embodiment of the shift register unit W(n) of Fig. 27. Fig. 58A and Fig. 58B are respectively a block diagram and a timing signal waveform diagram of the shift register used in the first embodiment of the first embodiment for three timing signals. FIG. 59A and FIG. 59B respectively show a block diagram of the four shift timings used by the shift register of the first embodiment of the first embodiment, and a 43 2 〇〇 8 〇 H 1 1 timing signal waveform diagram. . [Description of main component symbols] 100, 200, 300, 400, 500: shift register S(l)~S(m), U(l)~U(m), W(l)~W(m) , X(l)~X(m) Y(l)~Y(m) ··Shift register unit IN: input terminal OUT··output terminal • RT, RT1, RT2: control terminal C: timing terminal CB : Reverse timing terminal PI, P2: Node ST^V: Start signal Vo(l)~Vo(m): Output signal CLK, CLKB: Timing signal VDD, VSS: Voltage 10 T1~T13, T6', T9' ··Optocrystal

Vcl(l) to Vcl(m), Vc2(l) to Vc2(m): control signals 202a, 202b: drive unit 204a, 204b, 204c: level control unit 302: bias unit ΔV: difference voltage

Vthl: threshold voltage TP1, TP2, TP3: timing cycle 200805243

-LmmwL· * IW3165PA

Cl : Capacitance Cgs : Parasitic capacitance 10, 11 : Curve

Claims (1)

200805243 二理»m · Πν:31ό5ΡΑ Patent application scope: 1. The H register has a shift register with multiple levels connected to each other in series „„早7〇' its towel fn-level shift register unit In the output, the output signal is one of the input of the n+1th shift register unit, and η is a natural number, and the nth stage shift register unit includes: a first level control unit, For providing a first timing signal output terminal; unit, (4) the input terminal of the (-)th (four) (four) unit is even--the first node, the voltage of the first node is a first control signal, and the brother-drive unit is configured to respond The first level control element is turned on by the gamma of the input signal, and is used to close the first level control unit 7 when the second control signal is at the level of a third control signal. a first quasi-control unit for providing a first voltage to the output-second driving unit for closing the second level control unit in response to the leading edge of the first control signal, and responding to the first a control edge (Rear Edge) to turn on the second level The unit and the second-order quasi-control element are provided in response to a first transistor (Transistor), the gate of the first n+2 shift register unit of the gate (the gate) The first voltage is to the wheel end. 2. The shift register according to claim 1, wherein the second level control unit comprises: receiving the n+2th shift register unit 46 200805243 ^ 2; TW3165PA • a first control signal, a first source/drain is coupled to the wheel, and a second source/drain receives the first voltage, the first transistor responding to the »11 +2, the first control signal leading edge of the stage shift register unit provides the first voltage to the output terminal. 3. The shift register according to claim 2, wherein the second level control unit further comprises a second transistor, the gate receives a second timing signal, and the source-source/no-pole Subtracting to the output end, the second source is ruptured to receive the first voltage, and the second transistor is responsive to the rising edge of the second timing signal to provide the first voltage to the wheel output; The enabling time of the second timing signal is offset from the enabling time of the first timing game. ° 4, as claimed in the scope of application of the invention, the shift register, the middle drive unit of the basin includes a third transistor, and the gate receives the second control signal to break the 'first source/secret _To the first node, the second source & pole receives the third control signal. The shift register according to claim 4, wherein the second and third control signals are respectively the first control signal of the n+2th shift register unit and The first voltage. ^ 6. The shifting register according to claim 5, wherein the first driving unit further comprises a fourth transistor, the gate receiving the second signal, and the first key is connected to the first The node, the second source/no pole receives the input signal. ^ 7' The shift register according to claim 4, wherein the second and the third control signals are respectively the n+1th shift register unit. The TW3165PA participates in the first control signal and the first timing signal. 8. The shift register of claim 7, wherein the driving unit further comprises a fourth transistor, the gate receiving the second timing signal, and the first source/drain coupling To the first node, the second source/drain receives the input signal. 9. The shift register of claim 4, wherein the second and third control signals are the second timing signal and the input signal. The shift register according to claim 9, wherein the first driving unit further comprises a fifth transistor, and the gate receives the output signal of the n+1th shift register unit. The first source/drain is coupled to the first node, and the second source/drain receives the first voltage. 11. The shift register according to item 4 of the patent application scope, wherein the 4th and 1st control signals are respectively the output signal of the η + 1 shift temporary storage crying unit and the first voltage . 12. The shift register according to claim 1, wherein the first drive unit further comprises a sixth transistor, the gate receives the input signal, and the first source/drain receives the input signal. The second voltage, the second source/drain is coupled to the first node. 13. The shift register of claim 1, wherein the second driving unit comprises a biasing unit, and the input end of the second level control unit is coupled to a second node, The voltage of the second node is a fourth control signal 'the biasing unit controls the level of the fourth control signal in response to the first control flag to close the second level control list 48 200805243 one % two The TW3165PA .=, and = the level of the first control signal should be controlled to open the second level control unit. The second driving unit further includes: a seventh transistor, a gate receiving the second timing signal, and a ―/ pole receiving the second power. Waste, a source of the source. The first source/bungee receives the fourth control message <15. The shift register as described in the patent application scope item, 1 the first quasi-control unit includes an eighth unit, ^β system U Lu, 篦, Β,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,弟一源1一6. As for the shift register described in the application of the article, the shaidi quasi-control unit includes a tribute to the eight batches of 曰, 包日日, The gate receives the fourth & 弟, and the source-source/polar-polar wheel receives the first voltage. A source of a younger brother / 汲 1 7 · such as Shen Qing patent scope item 1. One of the first stage shift register units receives the ^^' in the first stage shift register and uses the start signal as the input; , the private register of any two of the shift register units, and the enabling time of the remote register received by the center and the two adjacent shift register units In order to stagger, · In the second stage of the reception of the second-stage shift register unit, the enabling time of the Lu-energy time and the n+1-th shift temporary suspension is also staggered. The first timing signal received by the early release of the first time is the shift register according to the item i of claim 1, wherein the n+1th shift register unit receives one The third timing signal and the first timing signal, wherein the enabling time of the third timing signal and the enabling time of the first and second timing signals are staggered. The shift register according to claim 1, wherein the 1 n+1 shift register unit receives a third timing signal and a fourth timing signal, wherein the first Second, the enabling times of the third and the fourth timing signals are all staggered. # 21·^ — A shift register having a shift register in which a plurality of stages are connected in series, a single 70, wherein the first stage shift register unit outputs an output tiger, and the round signal is n One of the +1 stage shift register unit inputs k ' η is a natural number, and the first stage shift register unit includes: a round out: a first level control unit 'to provide a first The timing signal is connected to the input terminal of the first level control unit. The voltage of the first and second motions is -the first control. The first leading edge of the control level is turned on (F_t_; higher than a third The second level of the control signal is a second driving unit, and the second leveling unit is turned off to provide a first voltage to the front edge of the output first control signal and is responsive to the first After the control signal 50 200805243 two s fine m · TW3165PA edge (Rear Edge) to turn on the second level control unit; and a second level control unit for responding to the first control of the n+1th stage shift register unit The signal provides a low voltage level of the first timing signal to the output. 22. The shift register according to claim 21, wherein the 5th position control unit comprises: a first transistor (Transistor), a gate (Gate) receiving a first (fourth) stage shift register unit - a control signal 'first source (s_e) / no drain (Drain) coupled to the wheel end The second source/drain receives the first timing signal, and the first transistor is used for the first control signal of the n+1th shift register unit to be higher than the first timing The signal bit provides the low voltage level of the first timing signal to the output on time. / 2 3. The shift register according to claim 2, wherein the third level control element further comprises a second transistor, the gate receives two second timing signals, and the first source a pole/drain is coupled to the output terminal, a second source pole receives the first voltage, and the second transistor responds to the rising edge of the number to provide the first voltage to the output terminal j wherein the enabling time of the second timing signal and the enabling time of the first timing are staggered. The source of the tiger is extremely extreme and extremely 25. As described in the scope of claim 24, the shift register, - ' ... - a... I 24. As described in the scope of patent application 帛 21, only temporary crying, The first drive unit includes a third transistor, and the first source/drain is coupled to the first node, and the first control signal is received. 2〇〇8°1243rw3165PA The second and third control signals are respectively the first control signal of the n+1th stage shift register unit and the first timing signal. The shift register according to claim 25, wherein the first driving unit further comprises a fourth transistor, the gate receives the second timing signal, and the first source/drain coupling Connected to the first node, the second source/drain receives the input signal. The shift register according to claim 24, wherein the second control signal is the first control signal of the n+2 shift register unit and the first A voltage. The shift register according to claim 27, wherein the first driving unit further comprises a fourth transistor, the gate receives the second timing signal, and the first source/source is connected. To the other node, the second source weave receives the input signal. #29. The shift register according to claim 24, wherein the second and the third control signals are the second timing signal and the input signal, respectively. ^30· If the shift register is described in claim 29, the arrow is further included with a fifth transistor, and the gate receives a state-level 4: early: output signal 'first-source The pole/汲 pole is coupled to the s point, and the second source/drain receives the first voltage. For example, the shift register described in claim 24 of the patent application is the output signal of the second and third control signal subsystems and the first-voltage step-by-step shift register 52 200805243 The second drive unit further includes a sixth transistor, the gate receives the input signal, the first source/drain receives a second voltage, and the second source/drain is coupled to the The first node. The shift register according to claim 21, wherein the second driving unit comprises a biasing unit, and the input end of the second level control unit is coupled to a second node, The voltage of the second node is a fourth control signal, and the biasing unit is configured to control the level of the fourth control signal in response to the leading edge of the first control signal to close the second level control unit and respond to The trailing edge of the first control signal controls the level of the fourth control signal to activate the second level control unit. 34. The shift register according to claim 33, wherein the «Haidi drive unit further comprises: a seventh transistor, the gate receives the second timing signal, the first source // The pole receives the second voltage, and the second source/drain receives the fourth control signal. σ ^ 士 申 申 申 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利The first timing signal, _ pole/drain is coupled to the output. - 36. The shift register as described in claim 4, wherein: the Si unit includes a "ninth transistor" gate receiving the pole receiving web _ to the output, , ~ · Shift register as described in claim 21 of the patent scope - 53 200805243 one 12 two violation of the muscle. Ding W3165PA These levels shift "save H single wealth 1 - level single temporary (four) single to receive a start signal, and (4) material signal as the round of people signal 38. Item 21 (4) (4) In this case, any two adjacent shift register registers in the unit "the receiving of the first-order timing signal is staggered; : the middle na shift temporary storage unit receiving The enabling time of the second timing sequence and the first _ timing ^ received by the n+1th shift register unit are also staggered.守斤 afl said 39. As described in the scope of claim 21, the second-level shift register unit receives the third-order signal to sequence 3 = three timing signals and the enable time The time of the first and the younger brothers was staggered. _ 40. The shift register described in claim 21, wherein the 苐η+1 shift temporary storage of the crying totals ^ ', 士% οα early 接收 receives a younger three timing signals and a fourth huayanghu, wherein the first, the second, the third, and the fourth timing signal are all _ 41. _ kinds of shift register, the plurality of stages are connected in series with each other Shifting the temporary sneak 兀 'where the nth stage shift register unit rotates an output signal 'the input (4) number is the η+i level shift temporary storage H unit one input number 'n is - The natural number, the nth stage shift register unit comprises: a first level control unit, using a subtraction-first-order signal to an output; a second, a moving unit, and the first level control The input end of the unit is connected to the first point, and the voltage of the first node is a first control signal 54 200805J43tw316spa. " :J - 2..., 乂兰士ή:-:---二二二二:- • -: 一·,:二'...:一*~~~ The first driver 7〇 is used to turn on the first bit in response to the leading edge of the input signal (Fr〇nt Edge) a control unit, configured to close the first level control unit in response to a leading edge of the first control signal of the n+2 stage shift register 7G; a second level control unit for providing a first a voltage is applied to the output terminal; and a second driving unit is configured to turn off the second level control unit in response to the leading edge of the first control signal, and to be turned on in response to the first control signal (Rear Edge) The second level control unit. 42. The shift register according to claim 41, wherein the driving unit comprises a first transistor (Transist〇r), and a gate (Gate) receiving a first control signal of the n+2 stage shift register unit, a first source/drain is connected to the first node, and a second source/no pole receives the first voltage The third transistor is configured to provide the first voltage to the first node in response to the leading edge of the first control signal of the n+2th stage shift register unit. 43. As claimed in claim 42 The shift register, wherein the first driving unit further comprises a second transistor, the gate Receiving a second timing signal, the first source/drain is connected to the first node, and the second source/drain receives the input signal, and the second transistor is configured to respond to the rise of the second timing signal The Rising Edge provides a low voltage level of the round signal to the first node; wherein the enabling time of the second timing signal and the enabling time of the first timing signal are staggered. "- . — . I. τ — · - - - —. 一 — — — — _ ——, _ — _ 55 200805243 ... • —mmm · TW3165PA • 44· Move as described in item 41 of the patent application a bit register, further comprising a third level control unit for providing the first voltage to the output end in response to the leading edge of the output signal of the n+1th stage shift register unit, the third The level control unit includes a second transistor, the gate receives an output signal of the n+1th shift register unit, the first source/drain is coupled to the output, and the second source/ The bungee receives the first electric grinder. The shift register according to claim 44, wherein the third level control unit further comprises a ···, a fourth transistor, and the gate receives a second timing signal, a source and a pole are connected to the output terminal, and the second source/no pole receives the first voltage, and the second transistor responds to the rising edge of the second timing signal to extract the first voltage to the output. end. The shift register according to claim 41, wherein the second driving unit comprises a biasing unit coupled to the second level of the second level control unit a node, the voltage of the second node is a -> amp; the bias unit is configured to control the level of the fourth control signal in response to the first control signal to control the second level control The single, the singular, the sub-response to the position of the control number at the trailing edge of the first control signal to turn on the second level control unit. System ▲ / 7 · If you apply for the shift register described in item 46 of the patent scope, the φ 5 弟 一 驱动 drive unit further includes: *, a sixth transistor, the gate receives the second timing signal, The first source//and the pole receives the second voltage, and the second source/drain receives the fourth control signal 56 rtfrrr 20080_5243TW3165PA, as described in item 4i, the shifting (four) register, the younger bit The quasi-control unit comprises a "seventh transistor", the gate is connected to (four) the first control signal 'the first source, the source receives the first timing signal, and the gate/drain is coupled to the wheel terminal. Λ弟一源 49. As disclosed in the scope of claim 41, the shift register, The first level control unit 1 includes a U-crystal, the gate receives the fourth control signal, and the first source/no-pole is connected to the output, and the first pole receives the first voltage. 5〇. If the shifting temporary storage piano described in the scope of claim 2, the shifting temporary storage unit in the unit-level shift register unit & receive-start signal, and The start signal is used as the round signal. 51. The shift register of claim 41, wherein the first timing signal received by any two adjacent shift register units of the shift register unit The enabling time is staggered; wherein, the enabling time of the second timing signal received by the nth stage shift register unit and the enabling of the first timing signal received by the n+1th shift register unit Time is also staggered. 52. The shift register according to claim 41, wherein the η+1 stage shift register unit receives a third timing signal and the first timing signal, wherein the third timing The enabling time of the signal is offset from the enabling time of the first and second timing signals. 53. The shift register according to claim 41, wherein the n+1th shift register unit receives a third timing signal and a fourth ϊί¥Γϊ~ ϊί¥Γϊ~ TW3165PA 200805243 The second, the third and the fourth time sequence signal, wherein the first number is staggered on the day. 54. Two kinds of shifting (four) storing, having a plurality of stages connected to each other in series 邙: ':::... wherein the nth, stage shift register unit output - round out. k. The nickname is the n+1th shift temporary storage element number 'n is a natural number, and the nth stage shift register is input to the first level control unit for providing - the first · · · output Connected to: 'The input terminal of the first level control unit is coupled to the younger point, 'the first node of the electric making sound, the first drive unit is used to return to the division wheel 4 m tiger' Ede·, lose The leading edge of the mirror (the RisinS shift register unit Hi is configured to respond to the first level Edge) to close the first level (four) single 1; the driving edge (5) ggeHng a second level control unit for 徂And a first voltage to the output first driving unit, in response to turning off the second level control unit, and the front edge of the signal is turned on to turn on the second level first control After the signal, the first driving unit includes a shift register of the -th electric item, wherein the n+1th shift register unit is received: (_^: nsistor), gate (Gate (Source) / 极无(Dmi_ is connected to the first -: control signal, the first source receives the first - timing signal, the third power = point 'second source / no pole connection - ... one _______________ The Japanese body is used to respond to the n+1th shift 58 . , · 二 二···一·θ' ΈΓ 'gs------ ·»— ^ * I mi I 200805243^ —TW3165PA ” The driving edge of the first control signal of the register unit provides the first voltage to the first node. 56. The shift register according to claim 55, wherein the driving unit is further The second transistor includes a second timing signal, the first source/drain is coupled to the first node, and the second source/drain receives the round signal. The second transistor is used for the second transistor. Providing a low voltage level of the input signal to the first node in response to a rising edge of the second timing signal; wherein, the enabling time of the second timing signal and the first timing The enabling time of the signal is staggered. 57' The shift register as described in claim 54 of the patent application, further comprising a third level control unit for responding to the n+1th shift Providing the first voltage to the output terminal of the output signal of the descent unit, the third level control The unit includes: _ a second transistor, the gate receives the output signal of the n+1th stage shift register unit, »-source/no pole is connected to the output terminal, and the third source/no pole The first voltage is received as described in claim 57, wherein the third-level control unit further comprises: a fourth transistor 'gate receiving-second timing signal, The first source is connected to the input _, the first source is connected to the first voltage, and the second transistor is responsive to the rising edge of the second timing signal to provide the voltage to the output. 59·If you apply for a shift register as described in item 54 of the patent scope, where – one —.../ . . . ~ ~ one-: ----------------- ------- -Γ -> - - :r I f 4 1 200805243 TW3165PA The second driving unit includes a biasing unit coupled to the second end of the second level control unit The voltage of the second node is a fourth control signal, and the biasing unit is configured to control the level of the fourth control signal to close the second level control unit in response to the leading edge of the first control signal. And controlling the level of the fourth control signal to open the second level control unit in response to the trailing edge of the first control signal. 60. The shift register according to claim 59, wherein the driving of the first one further comprises: a sixth transistor, the gate receiving the second timing signal, the first source// The pole receives a voltage from the remote, and the second source/no pole receives the fourth control air number. The shift register according to claim 54, wherein the first level control unit comprises a seventh transistor, and the gate receives the first control signal 'first-source/汲The pole (4) first timing signal, / pole /; and the pole shore horse connected to the output. ’, ^ A § Month of the range of the shift register described in item 54 of the profit-seeking range, 苴, »Hai-level control unit % includes -m body ^ control signal 'first-source her fine money input ^ pole receiving The first voltage. Strictly original Θ 63 · If applying for patent ribs, the shift register of the four-stage shifting temporary wire unit, in which the receiving-start signal, and (four) f-level shift The register unit is 64. If the patent application range y is started as the input signal. The shift register unit 54 of the shift register unit is arranged to be connected to the two adjacent shift register units. . . . , 60 A - 200805243 The enabling time of the first timing signal is staggered; wherein the enabling time of the second timing signal received by the nth stage shift register unit is received by the n+1th shift register unit The enabling time of the first timing signal is also staggered. 65. The shift register of claim 54, wherein the n+1th shift register unit receives a third timing signal and the first timing signal, wherein the third timing The enabling time of the signal is offset from the enabling time of the first and second timing signals. 10 66. The shift register according to claim 54, wherein the n+1th shift register unit receives a third timing signal and a fourth timing signal, wherein The enabling times of the second, third, and fourth timing signals are all staggered. . —61