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Application filed by Winbond Electronics CorpfiledCriticalWinbond Electronics Corp
Priority to TW95115240ApriorityCriticalpatent/TWI299500B/en
Publication of TW200741741ApublicationCriticalpatent/TW200741741A/en
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Publication of TWI299500BpublicationCriticalpatent/TWI299500B/en
A memory row decoder is disclosed, comprising a first depletion NMOS transistor having a second source/drain coupled to a first partially decoded signal, and a gate coupled to a second partially decoded signal, a first enhancement PMOS transistor having a second source/drain coupled to the second partially decoded signal, and a gate coupled to a first source/drain of the first depletion NMOS transistor, first and second enhancement NMOS transistors coupled in parallel between a first source/drain of the first enhancement PMOS transistor and a first reference potential, and gates thereof respectively coupled to the first partially decoded signal and a reset signal. The first enhancement PMOS transistor has reduced GIDL current and thus the memory row decoder consumes less power in an unselected mode.
A cmos device comprising an nmos transistor with recessed drain and source areas and a pmos transistor having a silcon/gernanium material in the drain and sou