TW200735269A - Method of generating wiring routes with matching delay in the presence of process variation - Google Patents

Method of generating wiring routes with matching delay in the presence of process variation

Info

Publication number
TW200735269A
TW200735269A TW095114494A TW95114494A TW200735269A TW 200735269 A TW200735269 A TW 200735269A TW 095114494 A TW095114494 A TW 095114494A TW 95114494 A TW95114494 A TW 95114494A TW 200735269 A TW200735269 A TW 200735269A
Authority
TW
Taiwan
Prior art keywords
wiring
path
traverse
wiring path
paths
Prior art date
Application number
TW095114494A
Other languages
English (en)
Inventor
Peter A Habitz
David J Hathaway
Jerry D Hayes
Anthony D Polson
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of TW200735269A publication Critical patent/TW200735269A/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
TW095114494A 2005-04-27 2006-04-24 Method of generating wiring routes with matching delay in the presence of process variation TW200735269A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/908,102 US7418689B2 (en) 2005-04-27 2005-04-27 Method of generating wiring routes with matching delay in the presence of process variation

Publications (1)

Publication Number Publication Date
TW200735269A true TW200735269A (en) 2007-09-16

Family

ID=37195277

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095114494A TW200735269A (en) 2005-04-27 2006-04-24 Method of generating wiring routes with matching delay in the presence of process variation

Country Status (3)

Country Link
US (3) US7418689B2 (zh)
CN (1) CN100440229C (zh)
TW (1) TW200735269A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI689833B (zh) * 2014-06-18 2020-04-01 英商Ａｒｍ股份有限公司 調整用於靜態時序分析的時序降額的方法與電腦設備

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US7412680B1 (en) * 2005-09-15 2008-08-12 Altera Corporation Method and apparatus for performing integrated global routing and buffer insertion
JP2007164427A (ja) * 2005-12-13 2007-06-28 Matsushita Electric Ind Co Ltd 多電源集積回路のレイアウト設計方法
US20070174803A1 (en) * 2006-01-20 2007-07-26 Lizotech, Inc. Method for concurrent search and select of routing patterns for a routing system
US7509609B2 (en) * 2006-03-15 2009-03-24 Agere Systems Inc. Methods and apparatus for reducing timing skew
US7844931B2 (en) * 2007-03-01 2010-11-30 International Business Machines Corporation Method and computer system for optimizing the signal time behavior of an electronic circuit design
US20090199143A1 (en) * 2008-02-06 2009-08-06 Mentor Graphics, Corp. Clock tree synthesis graphical user interface
US20090217225A1 (en) * 2008-02-22 2009-08-27 Mentor Graphics, Corp. Multi-mode multi-corner clocktree synthesis
US9310831B2 (en) 2008-02-06 2016-04-12 Mentor Graphics Corporation Multi-mode multi-corner clocktree synthesis
US8024690B2 (en) * 2008-05-19 2011-09-20 Arm Limited Method, system and computer program product for determining routing of data paths in interconnect circuitry providing a narrow interface for connection to a first device and a wide interface for connection to a distributed plurality of further devices
US8191024B2 (en) * 2009-03-16 2012-05-29 Qualcomm Incorporated Customizable H-tree synthesis tool
JP2011086267A (ja) * 2009-10-19 2011-04-28 Fujitsu Ltd 設計支援プログラム、設計支援装置、および設計支援方法
US8448110B2 (en) * 2009-11-24 2013-05-21 International Business Machines Corporation Method to reduce delay variation by sensitivity cancellation
TWI425890B (zh) * 2011-07-14 2014-02-01 私立中原大學 Differential sprite - like delay line structure
US20130326451A1 (en) * 2012-06-01 2013-12-05 International Business Machines Corporation Structured Latch and Local-Clock-Buffer Planning
KR20140031688A (ko) * 2012-09-05 2014-03-13 삼성전자주식회사 스토리지 시스템을 위한 마모 관리 장치 및 방법
US9372952B1 (en) * 2014-03-07 2016-06-21 Cadence Design Systems, Inc. Methods, systems, and articles of manufacture for enhancing metrics of electronic designs using design rule driven physical design implementation techniques
CN106682314A (zh) * 2016-12-29 2017-05-17 北京华大九天软件有限公司 一种通过指定图层进行布线端口匹配的布线方法
US10769345B1 (en) * 2018-12-20 2020-09-08 Cadence Design Systems, Inc. Clock tree optimization by moving instances toward core route
US10936773B1 (en) * 2019-08-26 2021-03-02 International Business Machines Corporation Sink-based wire tagging in multi-sink integrated circuit net
US11836000B1 (en) * 2022-09-29 2023-12-05 Synopsys, Inc. Automatic global clock tree synthesis

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US5109168A (en) * 1991-02-27 1992-04-28 Sun Microsystems, Inc. Method and apparatus for the design and optimization of a balanced tree for clock distribution in computer integrated circuits
US5550748A (en) * 1994-03-22 1996-08-27 Cadence Design Systems, Inc. Region search for delay routing and signal net matching
KR100352009B1 (ko) * 1995-04-28 2002-12-12 마츠시타 덴끼 산교 가부시키가이샤 논리집적회로의 신호전파 지연시간 평가방법
US6301693B1 (en) * 1998-12-16 2001-10-09 Synopsys, Inc. Non-linear optimization system and method for wire length and delay optimization for an automatic electric circuit placer
US6311313B1 (en) * 1998-12-29 2001-10-30 International Business Machines Corporation X-Y grid tree clock distribution network with tunable tree and grid networks
US6466008B1 (en) * 2000-10-06 2002-10-15 Hewlett-Packard Company Method for matching the lengths of signal traces
US7003754B2 (en) * 2000-12-07 2006-02-21 Cadence Design Systems, Inc. Routing method and apparatus that use of diagonal routes
JP3564539B2 (ja) * 2001-07-31 2004-09-15 独立行政法人産業技術総合研究所 超伝導論理集積回路のパタンレイアウト方法
JP4108418B2 (ja) * 2002-09-10 2008-06-25 松下電器産業株式会社 半導体集積回路の設計方法
CN1279480C (zh) * 2002-12-17 2006-10-11 清华大学 考虑耦合效应进行时延优化的标准单元总体布线方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI689833B (zh) * 2014-06-18 2020-04-01 英商Ａｒｍ股份有限公司 調整用於靜態時序分析的時序降額的方法與電腦設備

Also Published As

Publication number Publication date
US20080195993A1 (en) 2008-08-14
US20060248488A1 (en) 2006-11-02
US7823115B2 (en) 2010-10-26
US7865861B2 (en) 2011-01-04
CN1855107A (zh) 2006-11-01
CN100440229C (zh) 2008-12-03
US20080201683A1 (en) 2008-08-21
US7418689B2 (en) 2008-08-26

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