TW200731459A - Substrates including a capping layer on electrically conductive regions - Google Patents

Substrates including a capping layer on electrically conductive regions

Info

Publication number
TW200731459A
TW200731459A TW095112178A TW95112178A TW200731459A TW 200731459 A TW200731459 A TW 200731459A TW 095112178 A TW095112178 A TW 095112178A TW 95112178 A TW95112178 A TW 95112178A TW 200731459 A TW200731459 A TW 200731459A
Authority
TW
Taiwan
Prior art keywords
capping layer
electrically conductive
conductive regions
dielectric region
substrates including
Prior art date
Application number
TW095112178A
Other languages
Chinese (zh)
Other versions
TWI329349B (en
Inventor
David E Lazovsky
Sandra G Malhotra
Thomas R Boussie
Tony P Chiang
Original Assignee
Intermolecular Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/132,841 external-priority patent/US7749881B2/en
Priority claimed from US11/132,817 external-priority patent/US7390739B2/en
Application filed by Intermolecular Inc filed Critical Intermolecular Inc
Publication of TW200731459A publication Critical patent/TW200731459A/en
Application granted granted Critical
Publication of TWI329349B publication Critical patent/TWI329349B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal

Abstract

A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively. Capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. The capping layer can be formed using appropriate processes.
TW95112178A 2005-05-18 2006-04-06 Substrates including a capping layer on electrically conductive regions TWI329349B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/132,841 US7749881B2 (en) 2005-05-18 2005-05-18 Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region
US11/132,817 US7390739B2 (en) 2005-05-18 2005-05-18 Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region

Publications (2)

Publication Number Publication Date
TW200731459A true TW200731459A (en) 2007-08-16
TWI329349B TWI329349B (en) 2010-08-21

Family

ID=37431723

Family Applications (1)

Application Number Title Priority Date Filing Date
TW95112178A TWI329349B (en) 2005-05-18 2006-04-06 Substrates including a capping layer on electrically conductive regions

Country Status (3)

Country Link
EP (1) EP1905072A4 (en)
TW (1) TWI329349B (en)
WO (1) WO2006124131A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9018516B2 (en) 2012-12-19 2015-04-28 Sunpower Corporation Solar cell with silicon oxynitride dielectric layer
US10176984B2 (en) * 2017-02-14 2019-01-08 Lam Research Corporation Selective deposition of silicon oxide

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6323131B1 (en) * 1998-06-13 2001-11-27 Agere Systems Guardian Corp. Passivated copper surfaces
US6641899B1 (en) * 2002-11-05 2003-11-04 International Business Machines Corporation Nonlithographic method to produce masks by selective reaction, articles produced, and composition for same
US6911400B2 (en) * 2002-11-05 2005-06-28 International Business Machines Corporation Nonlithographic method to produce self-aligned mask, articles produced by same and compositions for same
US7205228B2 (en) * 2003-06-03 2007-04-17 Applied Materials, Inc. Selective metal encapsulation schemes
US7081674B2 (en) * 2003-06-13 2006-07-25 Rensselaer Polytechnic Institute Polyelectrolyte nanolayers as diffusion barriers in semiconductor devices
US6860944B2 (en) * 2003-06-16 2005-03-01 Blue29 Llc Microelectronic fabrication system components and method for processing a wafer using such components
US7063164B2 (en) * 2004-04-01 2006-06-20 Schlumberger Technology Corporation System and method to seal by bringing the wall of a wellbore into sealing contact with a tubing

Also Published As

Publication number Publication date
TWI329349B (en) 2010-08-21
WO2006124131A3 (en) 2009-04-16
WO2006124131A2 (en) 2006-11-23
EP1905072A4 (en) 2010-11-03
EP1905072A2 (en) 2008-04-02

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees