EP1905072A4 - Substrates including a capping layer on electrically conductive regions - Google Patents

Substrates including a capping layer on electrically conductive regions

Info

Publication number
EP1905072A4
EP1905072A4 EP06740290A EP06740290A EP1905072A4 EP 1905072 A4 EP1905072 A4 EP 1905072A4 EP 06740290 A EP06740290 A EP 06740290A EP 06740290 A EP06740290 A EP 06740290A EP 1905072 A4 EP1905072 A4 EP 1905072A4
Authority
EP
European Patent Office
Prior art keywords
electrically conductive
capping layer
conductive regions
substrates including
substrates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06740290A
Other languages
German (de)
French (fr)
Other versions
EP1905072A2 (en
Inventor
David E Lazovsky
Sandra G Malhotra
Thomas R Boussie
Tony P Chiang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intermolecular Inc
Original Assignee
Intermolecular Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/132,817 external-priority patent/US7390739B2/en
Priority claimed from US11/132,841 external-priority patent/US7749881B2/en
Application filed by Intermolecular Inc filed Critical Intermolecular Inc
Publication of EP1905072A2 publication Critical patent/EP1905072A2/en
Publication of EP1905072A4 publication Critical patent/EP1905072A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
EP06740290A 2005-05-18 2006-04-03 Substrates including a capping layer on electrically conductive regions Withdrawn EP1905072A4 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/132,817 US7390739B2 (en) 2005-05-18 2005-05-18 Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region
US11/132,841 US7749881B2 (en) 2005-05-18 2005-05-18 Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region
PCT/US2006/012098 WO2006124131A2 (en) 2005-05-18 2006-04-03 Substrates including a capping layer on electrically conductive regions

Publications (2)

Publication Number Publication Date
EP1905072A2 EP1905072A2 (en) 2008-04-02
EP1905072A4 true EP1905072A4 (en) 2010-11-03

Family

ID=37431723

Family Applications (1)

Application Number Title Priority Date Filing Date
EP06740290A Withdrawn EP1905072A4 (en) 2005-05-18 2006-04-03 Substrates including a capping layer on electrically conductive regions

Country Status (3)

Country Link
EP (1) EP1905072A4 (en)
TW (1) TWI329349B (en)
WO (1) WO2006124131A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9018516B2 (en) 2012-12-19 2015-04-28 Sunpower Corporation Solar cell with silicon oxynitride dielectric layer
US10176984B2 (en) * 2017-02-14 2019-01-08 Lam Research Corporation Selective deposition of silicon oxide

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6323131B1 (en) * 1998-06-13 2001-11-27 Agere Systems Guardian Corp. Passivated copper surfaces
US20040087176A1 (en) * 2002-11-05 2004-05-06 International Business Machines Corporation Nonlithographic method to produce self-aligned mask, articles produced by same and compositions for same
US20040213971A1 (en) * 2002-11-05 2004-10-28 International Business Machines Corporation Nonlithographic method to produce masks by selective reaction, articles produced, and composition for same
US20040248409A1 (en) * 2003-06-03 2004-12-09 Applied Materials, Inc. Selective metal encapsulation schemes
US20040250755A1 (en) * 2003-06-16 2004-12-16 Ivanov Igor C. Microelectronic fabrication system components and method for processing a wafer using such components
US20050001317A1 (en) * 2003-06-13 2005-01-06 Ramanath Ganapathiraman Polyelectrolyte nanolayers as diffusion barriers in semiconductor devices

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7063164B2 (en) * 2004-04-01 2006-06-20 Schlumberger Technology Corporation System and method to seal by bringing the wall of a wellbore into sealing contact with a tubing

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6323131B1 (en) * 1998-06-13 2001-11-27 Agere Systems Guardian Corp. Passivated copper surfaces
US20040087176A1 (en) * 2002-11-05 2004-05-06 International Business Machines Corporation Nonlithographic method to produce self-aligned mask, articles produced by same and compositions for same
US20040213971A1 (en) * 2002-11-05 2004-10-28 International Business Machines Corporation Nonlithographic method to produce masks by selective reaction, articles produced, and composition for same
US20040248409A1 (en) * 2003-06-03 2004-12-09 Applied Materials, Inc. Selective metal encapsulation schemes
US20050001317A1 (en) * 2003-06-13 2005-01-06 Ramanath Ganapathiraman Polyelectrolyte nanolayers as diffusion barriers in semiconductor devices
US20040250755A1 (en) * 2003-06-16 2004-12-16 Ivanov Igor C. Microelectronic fabrication system components and method for processing a wafer using such components

Also Published As

Publication number Publication date
TWI329349B (en) 2010-08-21
WO2006124131A3 (en) 2009-04-16
TW200731459A (en) 2007-08-16
EP1905072A2 (en) 2008-04-02
WO2006124131A2 (en) 2006-11-23

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Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20080118

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC NL PL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL BA HR MK YU

DAX Request for extension of the european patent (deleted)
R17D Deferred search report published (corrected)

Effective date: 20090416

A4 Supplementary search report drawn up and despatched

Effective date: 20101005

RIC1 Information provided on ipc code assigned before grant

Ipc: H01L 21/76 20060101AFI20061206BHEP

Ipc: H01L 21/768 20060101ALI20100929BHEP

Ipc: H01L 29/00 20060101ALI20100929BHEP

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: INTERMOLECULAR, INC.

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN

17Q First examination report despatched

Effective date: 20171010

18W Application withdrawn

Effective date: 20171023