TW200731340A - Self-aligned pitch reduction - Google Patents
Self-aligned pitch reductionInfo
- Publication number
- TW200731340A TW200731340A TW095143225A TW95143225A TW200731340A TW 200731340 A TW200731340 A TW 200731340A TW 095143225 A TW095143225 A TW 095143225A TW 95143225 A TW95143225 A TW 95143225A TW 200731340 A TW200731340 A TW 200731340A
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- features
- self
- sacrificial layer
- etch
- Prior art date
Links
- 230000008021 deposition Effects 0.000 abstract 3
- 239000000945 filler Substances 0.000 abstract 3
- 239000000463 material Substances 0.000 abstract 3
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Inorganic Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Drying Of Semiconductors (AREA)
- Semiconductor Memories (AREA)
- Bipolar Transistors (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/291,303 US7560388B2 (en) | 2005-11-30 | 2005-11-30 | Self-aligned pitch reduction |
US11/558,238 US7390749B2 (en) | 2005-11-30 | 2006-11-09 | Self-aligned pitch reduction |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200731340A true TW200731340A (en) | 2007-08-16 |
TWI423302B TWI423302B (zh) | 2014-01-11 |
Family
ID=37698254
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW095143225A TWI423302B (zh) | 2005-11-30 | 2006-11-22 | 自行對準間隔縮減 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7390749B2 (zh) |
KR (1) | KR101318976B1 (zh) |
MY (1) | MY150207A (zh) |
TW (1) | TWI423302B (zh) |
WO (1) | WO2007064499A1 (zh) |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7695632B2 (en) * | 2005-05-31 | 2010-04-13 | Lam Research Corporation | Critical dimension reduction and roughness control |
US7560388B2 (en) * | 2005-11-30 | 2009-07-14 | Lam Research Corporation | Self-aligned pitch reduction |
US7432189B2 (en) * | 2005-11-30 | 2008-10-07 | Lam Research Corporation | Device with self aligned gaps for capacitance reduction |
US7485581B2 (en) | 2005-11-30 | 2009-02-03 | Lam Research Corporation | Device with gaps for capacitance reduction |
US7429533B2 (en) * | 2006-05-10 | 2008-09-30 | Lam Research Corporation | Pitch reduction |
US8852851B2 (en) | 2006-07-10 | 2014-10-07 | Micron Technology, Inc. | Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same |
US20090209097A1 (en) * | 2008-02-15 | 2009-08-20 | Thomas Schulz | Method of forming interconnects |
US7989307B2 (en) | 2008-05-05 | 2011-08-02 | Micron Technology, Inc. | Methods of forming isolated active areas, trenches, and conductive lines in semiconductor structures and semiconductor structures including the same |
US10151981B2 (en) * | 2008-05-22 | 2018-12-11 | Micron Technology, Inc. | Methods of forming structures supported by semiconductor substrates |
US8273634B2 (en) | 2008-12-04 | 2012-09-25 | Micron Technology, Inc. | Methods of fabricating substrates |
US8247302B2 (en) | 2008-12-04 | 2012-08-21 | Micron Technology, Inc. | Methods of fabricating substrates |
US8796155B2 (en) | 2008-12-04 | 2014-08-05 | Micron Technology, Inc. | Methods of fabricating substrates |
US8268543B2 (en) | 2009-03-23 | 2012-09-18 | Micron Technology, Inc. | Methods of forming patterns on substrates |
US9330934B2 (en) | 2009-05-18 | 2016-05-03 | Micron Technology, Inc. | Methods of forming patterns on substrates |
US20110129991A1 (en) * | 2009-12-02 | 2011-06-02 | Kyle Armstrong | Methods Of Patterning Materials, And Methods Of Forming Memory Cells |
US8518788B2 (en) | 2010-08-11 | 2013-08-27 | Micron Technology, Inc. | Methods of forming a plurality of capacitors |
US8455341B2 (en) | 2010-09-02 | 2013-06-04 | Micron Technology, Inc. | Methods of forming features of integrated circuitry |
US8691697B2 (en) | 2010-11-11 | 2014-04-08 | International Business Machines Corporation | Self-aligned devices and methods of manufacture |
US8742477B1 (en) * | 2010-12-06 | 2014-06-03 | Xilinx, Inc. | Elliptical through silicon vias for active interposers |
US8575032B2 (en) | 2011-05-05 | 2013-11-05 | Micron Technology, Inc. | Methods of forming a pattern on a substrate |
US9076680B2 (en) | 2011-10-18 | 2015-07-07 | Micron Technology, Inc. | Integrated circuitry, methods of forming capacitors, and methods of forming integrated circuitry comprising an array of capacitors and circuitry peripheral to the array |
US9177794B2 (en) | 2012-01-13 | 2015-11-03 | Micron Technology, Inc. | Methods of patterning substrates |
US8748297B2 (en) * | 2012-04-20 | 2014-06-10 | Infineon Technologies Ag | Methods of forming semiconductor devices by singulating a substrate by removing a dummy fill material |
US8629048B1 (en) | 2012-07-06 | 2014-01-14 | Micron Technology, Inc. | Methods of forming a pattern on a substrate |
US9059315B2 (en) * | 2013-01-02 | 2015-06-16 | International Business Machines Corporation | Concurrently forming nFET and pFET gate dielectric layers |
US8835328B2 (en) * | 2013-02-08 | 2014-09-16 | GlobalFoundries, Inc. | Methods for fabricating integrated circuits with improved semiconductor fin structures |
CN104681429B (zh) * | 2013-11-27 | 2017-12-29 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
US10566531B2 (en) | 2017-11-17 | 2020-02-18 | International Business Machines Corporation | Crosspoint fill-in memory cell with etched access device |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5324683A (en) * | 1993-06-02 | 1994-06-28 | Motorola, Inc. | Method of forming a semiconductor structure having an air region |
US6297125B1 (en) * | 1998-01-23 | 2001-10-02 | Texas Instruments Incorporated | Air-bridge integration scheme for reducing interconnect delay |
US6340435B1 (en) * | 1998-02-11 | 2002-01-22 | Applied Materials, Inc. | Integrated low K dielectrics and etch stops |
US6605541B1 (en) * | 1998-05-07 | 2003-08-12 | Advanced Micro Devices, Inc. | Pitch reduction using a set of offset masks |
TW451402B (en) * | 1999-04-19 | 2001-08-21 | United Microelectronics Corp | Manufacturing method of inter-metal dielectric layer |
US6413827B2 (en) * | 2000-02-14 | 2002-07-02 | Paul A. Farrar | Low dielectric constant shallow trench isolation |
KR100428791B1 (ko) * | 2002-04-17 | 2004-04-28 | 삼성전자주식회사 | 저유전율 절연막을 이용한 듀얼 다마신 배선 형성방법 |
DE10220486C1 (de) * | 2002-05-07 | 2003-09-18 | Nbt Gmbh | Alkalischer Akkumulator |
US7105442B2 (en) * | 2002-05-22 | 2006-09-12 | Applied Materials, Inc. | Ashable layers for reducing critical dimensions of integrated circuit features |
US6780753B2 (en) * | 2002-05-31 | 2004-08-24 | Applied Materials Inc. | Airgap for semiconductor devices |
US6734107B2 (en) * | 2002-06-12 | 2004-05-11 | Macronix International Co., Ltd. | Pitch reduction in semiconductor fabrication |
US6774051B2 (en) * | 2002-06-12 | 2004-08-10 | Macronix International Co., Ltd. | Method for reducing pitch |
DE10228807B4 (de) * | 2002-06-27 | 2009-07-23 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung von Mikrostrukturelementen |
US7169695B2 (en) * | 2002-10-11 | 2007-01-30 | Lam Research Corporation | Method for forming a dual damascene structure |
US7090967B2 (en) * | 2002-12-30 | 2006-08-15 | Infineon Technologies Ag | Pattern transfer in device fabrication |
EP1521301A1 (en) * | 2003-09-30 | 2005-04-06 | Interuniversitaire Microelectronica Centrum vzw ( IMEC) | Method of formation of airgaps around interconnecting line |
US7018917B2 (en) * | 2003-11-20 | 2006-03-28 | Asm International N.V. | Multilayer metallization |
US7485581B2 (en) * | 2005-11-30 | 2009-02-03 | Lam Research Corporation | Device with gaps for capacitance reduction |
US7432189B2 (en) * | 2005-11-30 | 2008-10-07 | Lam Research Corporation | Device with self aligned gaps for capacitance reduction |
US7560388B2 (en) * | 2005-11-30 | 2009-07-14 | Lam Research Corporation | Self-aligned pitch reduction |
-
2006
- 2006-11-09 US US11/558,238 patent/US7390749B2/en not_active Expired - Fee Related
- 2006-11-17 WO PCT/US2006/044708 patent/WO2007064499A1/en active Application Filing
- 2006-11-17 KR KR1020087015961A patent/KR101318976B1/ko active IP Right Grant
- 2006-11-17 MY MYPI20081815A patent/MY150207A/en unknown
- 2006-11-22 TW TW095143225A patent/TWI423302B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR20080074203A (ko) | 2008-08-12 |
TWI423302B (zh) | 2014-01-11 |
WO2007064499A1 (en) | 2007-06-07 |
US7390749B2 (en) | 2008-06-24 |
US20070122977A1 (en) | 2007-05-31 |
KR101318976B1 (ko) | 2013-10-16 |
MY150207A (en) | 2013-12-13 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |