TW200731081A - A DMA controller with self-detection for global clock-gating control - Google Patents

A DMA controller with self-detection for global clock-gating control

Info

Publication number
TW200731081A
TW200731081A TW095147638A TW95147638A TW200731081A TW 200731081 A TW200731081 A TW 200731081A TW 095147638 A TW095147638 A TW 095147638A TW 95147638 A TW95147638 A TW 95147638A TW 200731081 A TW200731081 A TW 200731081A
Authority
TW
Taiwan
Prior art keywords
dma controller
dma
self
global clock
detection
Prior art date
Application number
TW095147638A
Other languages
English (en)
Inventor
Ivo Tousek
Original Assignee
Via Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Via Tech Inc filed Critical Via Tech Inc
Publication of TW200731081A publication Critical patent/TW200731081A/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
TW095147638A 2005-12-19 2006-12-19 A DMA controller with self-detection for global clock-gating control TW200731081A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US75171805P 2005-12-19 2005-12-19

Publications (1)

Publication Number Publication Date
TW200731081A true TW200731081A (en) 2007-08-16

Family

ID=38165699

Family Applications (2)

Application Number Title Priority Date Filing Date
TW095147319A TWI326828B (en) 2005-12-19 2006-12-15 A dma controller with multiple intra-channel software request support
TW095147638A TW200731081A (en) 2005-12-19 2006-12-19 A DMA controller with self-detection for global clock-gating control

Family Applications Before (1)

Application Number Title Priority Date Filing Date
TW095147319A TWI326828B (en) 2005-12-19 2006-12-15 A dma controller with multiple intra-channel software request support

Country Status (3)

Country Link
US (3) US20070162643A1 (zh)
CN (3) CN100504828C (zh)
TW (2) TWI326828B (zh)

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US10693478B2 (en) 2018-07-30 2020-06-23 Realtek Semiconductor Corporation Clock generation system and method having time and frequency division activation mechanism

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US7770077B2 (en) * 2008-01-24 2010-08-03 International Business Machines Corporation Using cache that is embedded in a memory hub to replace failed memory cells in a memory subsystem
US7925825B2 (en) * 2008-01-24 2011-04-12 International Business Machines Corporation System to support a full asynchronous interface within a memory hub device
US8140936B2 (en) * 2008-01-24 2012-03-20 International Business Machines Corporation System for a combined error correction code and cyclic redundancy check code for a memory channel
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WO2012120690A1 (en) 2011-03-08 2012-09-13 Renesas Electronics Corporation Data transferring method, dma controller and image processing device
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WO2012106880A1 (zh) * 2011-07-11 2012-08-16 华为技术有限公司 获取芯片内部状态数据的方法和装置
KR101842245B1 (ko) 2011-07-25 2018-03-26 삼성전자주식회사 시스템 온 칩 버스 장치 및 그에 따른 루트 클럭 게이팅 방법
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CN104820574B (zh) * 2015-04-23 2018-05-18 华为技术有限公司 一种访问间接寻址寄存器的方法及电子设备
CN106294233B (zh) * 2015-06-29 2019-05-03 华为技术有限公司 一种直接内存访问的传输控制方法及装置
US10776118B2 (en) * 2016-09-09 2020-09-15 International Business Machines Corporation Index based memory access using single instruction multiple data unit
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Publication number Priority date Publication date Assignee Title
TWI457753B (zh) * 2007-08-22 2014-10-21 Advanced Micro Devices Inc 記憶體控制器及用於管理記憶體存取之方法
US10693478B2 (en) 2018-07-30 2020-06-23 Realtek Semiconductor Corporation Clock generation system and method having time and frequency division activation mechanism

Also Published As

Publication number Publication date
CN1983121A (zh) 2007-06-20
CN1991810A (zh) 2007-07-04
US20070162648A1 (en) 2007-07-12
TW200739357A (en) 2007-10-16
CN100495374C (zh) 2009-06-03
US20070162642A1 (en) 2007-07-12
US20070162643A1 (en) 2007-07-12
TWI326828B (en) 2010-07-01
CN1991809A (zh) 2007-07-04
CN100504828C (zh) 2009-06-24

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