TW200719436A - Fabrication method and structure for providing a recessed channel in a nonvolatile memory device - Google Patents

Fabrication method and structure for providing a recessed channel in a nonvolatile memory device

Info

Publication number
TW200719436A
TW200719436A TW095139965A TW95139965A TW200719436A TW 200719436 A TW200719436 A TW 200719436A TW 095139965 A TW095139965 A TW 095139965A TW 95139965 A TW95139965 A TW 95139965A TW 200719436 A TW200719436 A TW 200719436A
Authority
TW
Taiwan
Prior art keywords
region
semiconductor substrate
recessed region
forming
nonvolatile memory
Prior art date
Application number
TW095139965A
Other languages
Chinese (zh)
Inventor
Sang-Pil Sim
Kwang-Soo Kim
Chan-Kwang Park
Heon-Kyu Lee
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of TW200719436A publication Critical patent/TW200719436A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

A method of fabricating a nonvolatile memory device includes preparing a semiconductor substrate including a cell array region. The method also includes forming a recessed region in the cell array region by etching the semiconductor substrate. The method includes etching at least a portion of the semiconductor substrate that partially includes the recessed region and forming first and second trenches that differ in depth, intersect the recessed region, and link with each other. The method includes forming a device isolation layer having rugged bottoms and defining an active region by filling an insulating material in the first and second trenches. The method includes forming a gate insulation layer on the semiconductor substrate of the active region including the recessed region and forming a gate structure on the gate insulation layer, to fill the recessed region, the gate structure including a floating gate, an intergate insulating pattern, and a control gate.
TW095139965A 2005-11-01 2006-10-30 Fabrication method and structure for providing a recessed channel in a nonvolatile memory device TW200719436A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR20050103866 2005-11-01
KR1020060055061A KR100726359B1 (en) 2005-11-01 2006-06-19 Method of forming non-volatile memory device having recessed channel and the device so formed

Publications (1)

Publication Number Publication Date
TW200719436A true TW200719436A (en) 2007-05-16

Family

ID=38071556

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095139965A TW200719436A (en) 2005-11-01 2006-10-30 Fabrication method and structure for providing a recessed channel in a nonvolatile memory device

Country Status (3)

Country Link
KR (1) KR100726359B1 (en)
CN (1) CN1959960A (en)
TW (1) TW200719436A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101096907B1 (en) * 2009-10-05 2011-12-22 주식회사 하이닉스반도체 Semiconductor device and method of fabricating the same
CN108987401A (en) * 2018-07-20 2018-12-11 上海华力微电子有限公司 A kind of technology integrating method improving flash cell erasing state uniformity
CN110277393A (en) 2019-06-19 2019-09-24 上海华力微电子有限公司 Flash memory and its manufacturing method
CN111403400B (en) * 2020-03-31 2023-05-26 长江存储科技有限责任公司 Array common source of memory and forming method thereof

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020091984A (en) * 2001-06-01 2002-12-11 삼성전자 주식회사 Self align type flash memory device and method of forming the same
KR100493065B1 (en) * 2003-06-03 2005-06-02 삼성전자주식회사 Semiconductor device having trench gate type transistor and manufacturing method thereof
KR100470721B1 (en) * 2003-06-30 2005-03-14 삼성전자주식회사 Method for forming pattern having region being recessed
KR100642901B1 (en) * 2003-10-22 2006-11-03 매그나칩 반도체 유한회사 Method for manufacturing Non-volatile memory device
KR100587677B1 (en) * 2004-03-18 2006-06-08 삼성전자주식회사 Field Effect Transistor and method for manufacturing at the same
KR100553712B1 (en) * 2004-05-04 2006-02-24 삼성전자주식회사 Non volatile memory device incorporating selection transistor having recess channel and method of fabricating the same
KR100673229B1 (en) * 2005-07-04 2007-01-22 주식회사 하이닉스반도체 NAND-type flash memory device and method for manufacturing the same

Also Published As

Publication number Publication date
KR20070047202A (en) 2007-05-04
CN1959960A (en) 2007-05-09
KR100726359B1 (en) 2007-06-11

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